Quantum Devices and Integrated Circuits Based on Quantum Confinement in III-V Nanowire Networks Controlled by Nano-Schottky Gates

Transcription

1 ECS 2 Joint Intenational Meeting, San Francisco Sept. 2-7, 2 Sixth International Symposium on Quantum Confinement Quantum Devices and Integrated Circuits Based on Quantum Confinement in III-V Nanowire Networks Controlled by Nano-Schottky Gates Hideki Hasegawa Research Center for Integrated Quantum Electronics (IQE) and Graduate School of Electronics and Information Engineering, Japan

2 . Introduction Outline 2. Hexagonal BDD Quantum Circuits 3. GaAs-Based Quantum BDD Node Devices and Circuits Novel nanometer-scale Schottky gates GaAs-based quantum BDD node devices Integration of BDD node devices on hexagonal nanowire networks 4. Toward Room Temperature Operation and High Density Integration Formation of InP-based high density hexagonal nanowire networks Surface related key issue 5. Conclusion Collaborators IQE staff Dr. S. Kasai, Dr. C. Jiang and Dr. T. Sato Students T. Muranaka, A. Ito and M. Yumoto

3 Speed, Delay-Power Product of Quantum Devices 6 4 τ 2 [ps] G G 2e 2 h J.E.Mooij, 993 SSDM Ext. Abs. 339 K τ = 3K C G 5 K thermal energy -5 F -6 F -7 F Single Electronics present-day semiconductor devices -8 F -2 Quantum Limit P[W]

4 Scale-down limit of Si CMOS LSIs Research on Semiconductor Nanostructure Growing demands on Information Technology (IT) Nanotechnology in wide area ~ chemistry, biology, etc. Semiconductor Nanoelectronics based on Quantum Device and Circuit delay-power product near quantum limit small-size and high-density nano-sensing, nano-control But, How to? So far no realistic approach.

5 High Density Integration? Semi-classical devices First Monolithic Integrated Circuit in the World (Noyce, 959) Current Microprocessor (2) IBM PowerPC 3µm rule 64-bit.8µm rule 7MHz.4mm x.4mm SOI technology Discrete quantum devices How to make QLSIs?

6 QWRTr-load SET inverter QWRTr (Active Load) input Example of Quantum Logic Circuits (S. Kasai and H. Hasegawa presented at D 2) 25 output 2 5 Gain =.3 V DD = 4 mv V BG = -. V V G(QWRTr) = mv 3-gate WPGSET 5 µm W = 44 nm SET: L G = 5 nm, d f = 2 nm QWRTr: L G = 3 nm V G (QWRTr) V in V DD WPG QWRTr (active load) V out WPG SET (driver Tr.) 5 T =.6 K V in (mv) small delay power product but low gain voltage mismatch poor Vth control poor drivability low temperature

7 Novel Approach for III-V QLSI. Digital Processing Architecture Binary Decision Diagram (BDD) logic architecture 2. Nanostucture Hexagonal nanowire networks by GaAs etched nanowires and InGaAs nanowires by Selective MBE 3. Nanoscale Gate Technology Schottky in-plane gate (IPG) and wrap gate (WPG) 4. Surface and Interface Control Nano-Schottky interface Interface control layer (ICL)-based passivation 5. Device BDD node devices using gate-control quantum wire (QWR) and quantum dot (QD)

8 Digital Logic Architecture Digital processing (operations on digital functions) Implementation of digital functions Representation Boolean Equation Truth Table Implementation etc. Binary Decision Diagram (BDD) Binary Logic Gate Look-Up Table using Memory BDD Device Transistor Switch ROM device

9 Hexagonal BDD QLSI Approach BDD node device BDD logic architecture entry branch messenger input X i root r x r2 x 2 QWR switch -branch tunnel barrier -branch quantum dot input terminal x 3 x n node Hexagonal network Example: Exclusive OR Logic Function BDD f Boolean Logic Gate x x 2 x 2 x x 2 f 3 devices 5 gates, 6 Trs

10 Features of Our Approach BDD is suited to quantum devices No direct input-output connection is required no precise voltage matching no large voltage gain no large current drivability no large fan-in and fan-out Conventional Logic Gate Architecture Ultra-low delay-power product near the quantum limit High density integration hexagonal closely packed nanowire network free from contact problem reduced device count Hexagonal quantum BDD input root x3 r x xi x4 r2 x2 node The circuit itself works at room temperature at sacrifice of delay-power product IPG/WPG QWRTr-based BDD devices act as classical path switching devices even under non-quantum conditions. xn terminal single electron regime few electron regime many electron classical regime

11 Basic Schottky Gate Structure Schottky In-Plane Gate (IPG) and Schottky Wrap Gate (WPG) control of AlGaAs/GaAs etched nanowires GaAs nanowire AlGaAs GaAs Schottky In-plane Gate (IPG) electrons Schottky Wrap Gate (WPG) lateral structure stronger confinement size ~ smaller AlGaAs/GaAs nanowire quantum wire suitable for planar integration high temperature operation tunnel barrier control WPGs depletion layer WPG quantum wire transistor (QWRTr) quantum dot 2-gate WPG single electron transistor (SET)

12 Gate Control Characteristics of IPG/WPG Structures IPG QWRTr SdH oscillation 4 Source T = 4.2K VG=V 3 W geo -.4V 2 IPG -.6V Drain µm B (T) Controlof W eff IPG QWR WPG QWRTr GaAs exit branch Schottky WPG W LG 5 nm 2 5 T=.6 K -.48V -.36V -.42V V VG=V B (T) VG (V) 5 WPG QWR VG (V)

13 I-V Characteristics of IPG/WPG QWRTrs AlGaAs/GaAs etched nanowire IPG QWRTr T = 3 K V G =V -.2V -.4V -.6V 5 -.8V V DS (V) W = 53 nm L G = 6 nm 2 T = 3 K WPG QWRTr T=.7K -.2 V V G = V -.5 V -. V -.5 V V DS (V) W = 75 nm L G = 3 nm T =.7 K V G (mv) V G (mv)

14 Single Electron Transport in 2-WPG SET GaAs SET WPG AlGaAs GaAs nanowire GaAs Experiment Theory d f = 6 nm, W = 82 nm.4.4 T = 3 K T = 3 K K 2 K.. 5 K 5 K K 7.5 K K 4.2 K K 2.5 K K.5 K VG (V) VG (V) Lateral resonant tunnling of single electron e I = 2 T(E) 2 [f (E) f (E+qV DS )] de h Breit-Wigner formula e 2 Γ l Γ r ~ 4kTΓ l +Γ r cosh 2 E-EF 2kT T (K) T (K)

15 Various Types of BDD Node Devices by IPG/WPG Control of III-V Nanowires QWR-based BDD node device entry IPG GaAs nanowire WPG QWR -branch -branch Single electron BDD node device tunnel barrier WPG GaAs nanowire quantum dot WPG SET

16 WPG BDD Quantum Node Device WPG QWR-based BDD device GaAs nanowire -branch QWRTr entry entry 5 nm WPG -branch GaAs nanowire -branch WPG single electron BDD devices SET entry WPG 5 nm -branch quantum dot GaAs nanowire entry WPG quantum dot µm -branch -branch branch switch type tunnel barrier branch switch type tunnel barrier node switch type

17 Switching Characteristics QWR branch- switch BDD node device QWRTr entry Branch I-V T = 3 K 4 -branch VG = V -branch -branch Switching characteristics x x T = 3 K VG (mv) 2 -branch -branch VDD = 2 mv Time (s) -

18 WPG BDD Single Electron Node Device QD-based node switch device GaAs nanowire entry µm WPG -branch -branch Conductance oscillation from single channel.6.4 T =.5 K V Gent = -3. V V Gxi =.4 V -branch: open Switching characteristics 3 T =.5 K -branch 2 -branch.2 V Gent = -2.4 V V Gxi = +.4 V V Gxi (V) V Gxi (V) Conductance oscillation due to single electron transport Clear path switching

19 Quantum BDD Implementation Quantum BDD large scale integration hexagonal nanowire network + WPG x x x2 x2 x3 x4 x4 x x2 x3 x4 x x2 x3 x4 WPG wiring branch cut-off (etching, FIB) one level metallization

20 WPG BDD OR Logic Function Block WPG single electron BDD OR circuit WPG x root x f hexagonal layout root x 2 node device x GaAs nanowire nm x 2 -terminal - terminal

21 Operation of WPG BDD OR Logic Input/Output waveform OR x x T =.6 K x x 2 output Time (s) pulse height V DD = mv x : mv clock: 2 Hz x 2 : 25 mv entry gate: mv T = 2 K x x 2 output Time (s) V DD =.2 mv clock:. Hz pulse height x : 2 mv entry gate: + mv x 2 : mv

22 WPG BDD Fundamental Logic Family OR Half adder (exclusive OR) x2 OR x x x2 x+x2 ExOR x x2 x2 x x2 x+ x2.6 x 2 K x RT.4 x 2 output x 2 output.2 2 na Time (s) pulse height x : 2 mv x 2 : mv entry gate: + mv V DD =.2 mv Time (s) pulse h offset +x:.2 V -.4 V - x: x2: x2:..6 V DD : 25 mv

23 Circuit Design and Fabrication Technology Towards BDD Quantum Integrated Circuit Example: BDD 2-bit adder circuit diagram b c root s s node a a a a b b augend: a, a addend: b, b b b a b b a b terminal- sum: s, s carry:c b a WPG/nanowire layout nanowire c s s b b a a a b b a a b b terminal augend: a, a addend: b, b sum: s, s carry:c b root WPG Fabricated 2-bit adder circuit WPG QWRTr node device GaAs nanowire c s s -terminal a b a b 5 µm

24 8 6 4 Hexagonal BDD 2 bit Adder b a hexagonal nanowire network input carry b a WPG terminal C b S a node device a b 5 µm S a a b b T = 3 K VDD = 25 mv time (s)

25 InGaAs ridge quantum wire InGaAs InGaAs Ridge Nanowires for Room Temperature Operation AlGaAs/GaAs etched nanowires: possible minimum width = 7- nm Room temperature operation requires sub- nm width InAlAs PL QWR 23meV T=2K Formation Process <> µm patterned InP sub. 3µm 4µm InP patterned sub. ()A Pre-growth etching & O desorption by atomic Hydrogen Energy (ev) narrowest QWR by H* cleaning InGaAs ridge MBE growth of InGaAs InGaAs ridge QWR. theory Effective width, Weff (nm) Growth of InAlAs/InGaAs/InAlAs Wire width of 6 nm has been achieved

26 Hexagonal InGaAs Ridge Nanowire Network SEM image of hexagonal InGaAs nanowire network AFM image µm.8.4 <> <> 3 µm µm ( Ito et al. IPRM, ICFSI-8)

27 Potential Controllability of Nanometer-Sized Schottky Gates Semiconductor surface. Strong pinning (.88 ev) 2. Unpinning n-gaas nano-schottky gate φ MS =. ev Lg = 9nm. With strong pinned surface 2. With unpinned surface gate gate 5.8 ~ -2. V step.4 V 5 (nm).8 ~ -2. V step.4 V 5 (nm) Control of an environmental Fermi level pinning is important

28 Conclusion ) 2) 3) 4) 5) A new, simple and realistic approach for quantum LSIs is presented and discussed. Architecture: BDD logic architecture Hardware: Schottky WPG control of hexagonal III-V nanowire networks. WPG QWR and single electron BDD node devices using GaAs etched nanowires have been fabricated and BDD switching was realized. Hexagonal BDD ICs using GaAs etched nanowires have been fabricated. Logic operation has been confirmed. Hexagonal InGaAs nanowire network by H* assisted selective MBE combined with IPG/WPG gate technology gives good prospect for high density BDD QLSIs that are operating at delay-power products near the quantum limit at RT. Control of surface/interface remains to be a key issue.