Performance of Near-Ballistic Limit Carbon Nano Transistor (CNT) Circuits

Transcription

1 Performance of Near-Ballistic Limit Carbon Nano Transistor (CNT) Circuits A. A. A. Nasser 1, Moustafa H. Aly 2, Roshdy A. AbdelRassoul 3, Ahmed Khourshed 4 College of Engineering and Technology, Arab Academy for Science, Technology and Maritime Transport, Alexandria, Egypt, 1 menem_1954@yahoo.com, 2 drmosaly@gmail.com, Member of OSA, 3 roshdy@ieee.org, Senior Member, IEEE, 4 ahmedkhourshed@hotmail.com. ABSRACT: In this paper, we present a performance comparison betweeen circuits implemented using short channel MOSFETs and those using carbon nanotransistors (CNT) operating near the limit of the ballistic transport circuits. The circuits included digital applications, such as an inverter, NAND and NOR gates, and analog circuit of a folded cascode amplifier. The carbon nanotube can be used in both device fabrication and circuit interconnects as a carbon nanowire (CNW). Analysis and simulation results show that the CNT is superior from the points of view of power dissipation, frequency range and noise margins. Index Terms Carbon Nano Transistor (CNT), MOSFET, Ballistic Transport, Folded Cascode Amplifier. I. INTRODUCTION Carrier transport in semiconductors follows two main mechanisms: the driftdiffusion and ballistic mechanisms. In the first, the mean free path between collisions or scattering events is much shorter than the MOSFET device channel length (λ<< L). In this case, if the device is operating above threshold region, the drift dominates diffusion. If the device operates below threshold, the diffusion dominates. Under the above condition, one can ignore scattering completely. In this case, MOSFET operates more like a vacuum tube than a conventional semiconductor device, i.e., a thermionic emission. Modern devices work between drift-diffusion and ballistic regimes. However, drift-diffusion theory is no longer strictly valid, but it actually provides some insights that may be useful when the device dimensions scale down to the submicron range. Three categories of devices are in our concern: the carbon nano field effect transistor, the quasiballistic and the ballistic MOSFET. In this paper, we presnt the performance evaluation for both carbon nanotube and short channel MOSFET operating near the ballistic limit. In [1], it was shown experimentally that ultra long elastic scattering mean free path of about 1 µm which implies ballistic or near ballistic transport leading to mobilities in the order of 10 3 to 10 4 cm 2 /V.s. The current carrying capability is in the order of 10 9 A/cm 2 in multiwalled CNTs. This is three orders higher than the maximum current carrying capacity of copper. The above superior carrier transport and conduction characteristic makes it desirable for nanoscale electronic devices and interconnects. II. PHYSICS OF THE CARBON NANOTUBES There are two ways of making a transistor. A MOSFET-like device for which any charge demanded by the gate is supplied from the contacts. This mechanism is known as a charge modulation transistor. In the second type, there is a barrier at the contact and the transistor operates by modulating the width of the tunnel barrier. This is also known as a transmission modulation transistor. So, there are two types of carbon nanofets (CNFETS), the semiconducting and the metallic types. The graphene structure shown in Fig. 1 forms two adjacent sheets with M points representing the zero band gap (metallic CNT) and the Г points representing the band gap semiconducting CNT. The density of states for both types are shown in Fig. 2 [2, 6, 7]. Figure 2.a shows constant density of states near the Fermi-level (melallic CNT), while Fg. 2.b shows zero density of states near the Fermilevel (E=0 ev) representing the semiconducting CNT. The CNT structure can also be demonstrated by the rolled and unrolled struchers shown in Fig. 3. Typical diameters of carbon nanotubes are in the order of several nanometers. Figure 4 shows the device layout, where figure 4.a shows the structure of the metallic carbon ICCTA 2011, October 2011, Alexandria, Egypt 175

2 nanotube (MOSFET-like transistor) [2]. In this figure, the gate voltage pushes down the source to the channel barrier and allows any amount of charge demanded by the gate to enter the channel. Figure 4.b shows the structure of the semiconducting CNT (Schottky barrier transistor). In the Schottky barrier transistor, the gate voltage squeezes the barrier between the source and channel, which increases the tunneling current through the barrier. Schematic cross-section of the CNT is illustrated in Fig. 5 [2]. The device diameter is approximately 1.7 nm and the energy gap is about 0.5 ev. The insulator is formed by a hafnium dioxide having a dielectric constant of 16. The gate is a metal self aligned to the Pd drain and source contacts. The Pd provides a low Schottky barrier to the valance band. Fig. 3. Carbon nanotube: a- unrolled structure b- rolled structure [1]. (a) Fig. 1. E-k dispersion relation for graphene, calculated using a nearest-neighbour tight binding model. The three high-symmetry points are indicated by capital letters [2]. (b) Fig. 4. a- MOSFET-like transistor, b- Schottky barrier transistor [2]. (a) (b) Fig. 2. The density of states for metallic (a) and (b) semiconducting carbon nanotubes [2]. Fig. 5. Schematic cross section of the CNT[2]. ICCTA 2011, October 2011, Alexandria, Egypt 176

3 III. METRICS FOR PERFORMANCE EVALUATION AND COMPARISON OF NANOSCALE TRANSISTORS In digital circuit applications, the CMOS inverter is used to measure the performance of the MOSFETs. The performance measures are: the propagation delay related to the total load capacitance, the power dissipated, and the noise immunity. As CMOS dimensions scale deeply into the submicron (nano) range, many of the device nonideal behaviors arise. One of these nonidealities is the source drain series resistance contribution to the total resistance of the device. Another metric is the inverter effective drive current that appears to be useful in performance evaluation of nanoscale devices. This current is given by: I eff =1/2[C eff V DD ]/τpd (1) Where, Ceff is effective oxide capacitance, and τpd is the propagation delay between source and drain terminals. So, it is important to include the nonidealities in the simulation model used. It was shown in [3] that, the four point model of the inverter effective current is the model that is most correlated to the practical device operation. Throughout this paper, the analysis takes into consideration the nonideal behavior of the nanoscale devices, and the four point effective inverter current in addition to the resizing of the nmos and pmos aspect ratios to ensure the equality of the rise in fall times for both transistors. IV. MODEL DESCRIPTION The model used in this paper is shown in Fig. 6. It is known as the nine capacitance model [3]. In this model, we consider three current sources in the CNFET: a. The thermionic current contributed by the semiconducting sub-bands (I semi ) derived from the classical band theory. b- The current contributed by the metallic sub-bands (I metal ). c- The leakage current (I btbt ) caused by the band-to-band tunneling (btbt) mechanism through the semiconducting sub-bands. Fig. 6. Circuit model for the CNT [3]. Concerning I semi, for semiconducting subbands, we only consider the electron current for the nfet because the hole current is suppressed by the n-type heavily doped source/drain. The total current contributed by all substates is equal to the current flowing from the drain to the source (+k branch) minus the current flowing from the source to the drain ( k branch)[3] i.e., I semi (V ch,ds,v ch,gs ) LR J m,l (0,ΔΦ B ) +k - T RL J m,l (V ch,ds,δφ B ) -k ] (2) where V ch,ds and V ch,gs are the Fermi potential differences near the source side within the channel, ΔΦB is the channel surface-potential change with gate/drain bias, J m,l is the current contributed by the substate (m,l), T L,R and T R,L are the transmission probabilities, the factor of two is due to the double degeneracy of the subband, M and L are the numbers of subbands and substates, respectively. CNT= Q CAP =Q CNT (3) Concerning I metal, for metallic sub-bands of metallic nanotubes, the current includes both the electron and hole currents, i.e., (4) where T metal is the transmission probability, given by ICCTA 2011, October 2011, Alexandria, Egypt 177

4 ( ) (5) (10) where λ op is the optical phonon-scattering wavelength(~15 nm) and λ ap is the acoustic phonon-scattering wave length (~500 nm). It should be noted that in CNFET there exist three mechanisms for scattering [9]. These are the acoustic phonon scattering (near-elastic process), the optical phonon scattering (inelastic process), and the elastic scattering which is considered here to be independent of the carrier energy [3] (11) ] (12) With small gate bias (Em,0 >> ), the quantum capacitances due to carriers from source (+k branch) and drain (-k branch) are given by: Concerning I btbt and assuming a ballistic transport for the tunneling process, the BTBT current is approximated by the BTBT tunneling probability (T btbt ) times the maximum possible tunneling current integrated from the conduction band at the drain side up to the valance band at the source side, i.e., ] (13) ] (14) (15) (6) (16) (17) where T btbt is the transmission probability, given by ( ) ( ) where η m is a fitting parameter and F is given by: (7) (8) Is the electrical field triggering the tunneling process near the drain channel junction. The potential drop across the drainchannel junction is assumed to relax over the distance l relax. [ ] (18) (19) (20) (21) CMOS Model Equations: The long channel MOSFET small signal model including the inter electrode capacitances is shown in Fig.7 [4]. Transcapacitance Network The ac response of the CNFET device can be revealed using a controlled transfer capacitance array in between the source, drain, gate and body[3,6]. (9) Fig. 7. Small-signal MOS transistor equivalent circuit [5]. ICCTA 2011, October 2011, Alexandria, Egypt 178

5 The device transconductance is given by: (23) Due to device symmetry, (25) (24) (22) where V A is the Early voltage. Taking the body effect into consideration, the transconductance due to body effect is given by: ( ) (28) (27) (26) Where, is the Body effect coefficient, is the channel length modulation coefficient, v t is the threshold voltage, is the built-in potential, is the Fermi-potential,, C db0, are the source and drain capacitances when the source or drain are tied to the body [5]. also the same. The noise margin enhancement is about 11.5%. This nominates the CNFET to the operation at higher frequencies. Figs.13,14 show the behaviour of the CNFET through the inverter transfer characteristics, and the NAND gate input output characteristics. TABLE I COMPARISON BETWEEN DIGITAL CIRCUITS REALIZED BY CMOS AND CNFET Parameter/Device CMOS (180 nm) CNFET(32 nm) Noise Margin Low 375mV 418.7mV Noise Margin High 375mV 418.7mV Propagation Delay 10.15ps 0.2ps Power Delay 0.093pWs 0.093pWs Product Energy Delay 3.806*10-24 Js 75*10-27 Js Product Total Power Consumption 18.75mW 18.75mW A. CMOS 180nm Transistor simulation results: V. RESULTS AND DISCUSSION The described model was used to simulate three logic circuits, namely; the logic inverter, the NAND, and AND circuits for both CMOS (180 nm) and the CNFET (32 nm). The input output characteristics in both time domain and phase plane are displayed in Figs The simulation takes into account the various nonideal behaviors of the devices which include short channel and parasitic effects. In Fig.8 a severe distortion occures due to the application of nano-scale pulses to the long channel MOSFET. This distortion is much reduced when applying the same pulses to the CNFET as it is clear from Figure 12. TABLE I shows the comparison between the two transistor characteristics. As it is clear from the table, the most enhaced characteristics are the propagation delay in which the delay is reduced to more than 50 times and the energy delay product which is reduced by the same factor. This means that energy is almost the same. The total power consumption is Fig. 8. Input and output waveforms for Inverter using CMOS 180 nm Transistor. Fig. 9. VTC charactersitics for Inverter using CMOS 180 nm Transistor. ICCTA 2011, October 2011, Alexandria, Egypt 179

6 Fig. 13. VTC Characteristics for Inverter using Carbon Nano Transistor. Fig. 10. Input and output waveforms for a NAND gate using CMOS 180nm Transistor. Fig. 14. Input and output waveforms for a NAND gate using Carbon Nano Transistor. Fig. 11. Input and output waveforms for a NOR gate CMOS 180nm Transistor. B. Carbon Nano Transistor simulation results Fig. 15. Input and output waveforms for a NOR gate using Carbon Nano Transistor. Fig. 12. Input and output waveforms for Inverter using Carbon Nano Transistor. ICCTA 2011, October 2011, Alexandria, Egypt 180

7 C. Folded Cascode Amplifier D. Simulation results Fig 16. Folded Cascode Amplifier Circuit Fig 17. Transfer function (folded cascode CMOS 180nm) Another application for CMOS and CNFET is folded cascode amplifier. We summarize the simulation result in TABLE II as shown. TABLE II COMPARISON OF THE PERFORMANCE OF FOLDED CASCODE AMPLIFIER REALIZED BY CMOS AND CNFET Parameter CMOS 180nm CNFET 32nm Power µW 16.65µW dissipation Gain *10^6 Input 1.0*10^20Ω 5.0*10^11Ω Resistance Output 1.413*10^6Ω 3.681*10^10 Ω Resistance Output 28.56mV 0.37mV Noise Swing 3.62V 1.82V Fig 18. Transfer function (folded cascode CNFET 32nm) VI. CONCLUSION In this paper, we provided a quasi-analytical circuit compatible model for intrinsic ballistic CNFET. This model is seen to be very effective for various CNFET structures with a wide range of bias conditions and non ideal effects. This can be used in conventional circuit simulators. We also conclude that, the CNFET enhancement over the normal MOSFET manifests itself in the propagation delay and the noise margins, while the other characteristics are kept almost the ICCTA 2011, October 2011, Alexandria, Egypt 181

8 same. The propagation delay is reduced to more than 50 times and the energy delay product is reduced by the same factor. This means that energy is almost the same. The total power consumption is also the same. The noise margin enhancement is about 11.5%. This nominates the CNFET to the operation at higher frequencies. REFERENCES [1] EL-Muradi, M.M. Khalf-alla, K.-A.A. Shanab, W.T., Nanometer Ballistic MOSFET'S: Modeling, Simulation and Applications of Digital Circuits, XI th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), nanotube field-effect transistors, Appl. Phys. Lett., vol. 80, no. 17, pp , Apr [8] C. Dwyer, M. Cheung, and D. J. Sorin, Semi-empirical SPICE models for carbon nanotube FET logic, in Proc. 4th IEEE Conf. Nanotechnol., pp , [9] J. Guo and M. Lundstrom, Role of phonon scattering in carbon nanotube field-effect transistors, Appl. Phys. Lett., vol. 86, no. 19, p , May [2] Jie Deng, Device Modeling and Circuit Performance Evaluation for Nanoscale Devices: Silicon Technology beyond 45 nm Node and Carbon Nanotube Field Effect Transistors Doctor of Philosophy, Stanford University, June [3] Jie Deng, H.-S. Philip Wong, A Compact SPICE Model for Carbon-Nanotube Field- Effect Transistors Including Nonidealities and Its Application-Part I: Model of the Intrinsic Channel Region IEEE Transactions on Electron Devices, vol. 54, no. 12, Dec [4]Anisur Rahman, Jing Guo, Supriyo Datta, and Mark S. Lundstrom, Theory of Ballistic Nanotransistors IEEE Transactions on Electron Devices, vol. 50, no. 9, September [5] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, 4 th ed., John Wiley & Sons, University of California, Berkeley, [6] J. Deng and H.-S. P.Wong, A compact SPICE model for carbon nanotube field effect transistors including non-idealities and its application Part II: Full device model and circuit performance benchmarking, IEEE Trans. Electron Devices, vol. 54, no. 12, pp , Dec [7] J. Guo, M. Lundstrom, and S. Datta, Performance projections for ballistic carbon ICCTA 2011, October 2011, Alexandria, Egypt 182