Nevis ADC Tes+ng. Tim Andeen. Columbia University. LAr ADC Review. June 4, LAr ADC Review. Tim Andeen

Transcription

1 Nevis ADC Tes+ng Columbia University June 4, 214

2 Outline v This talk - tesbng and performance IntroducBon Nevis 1 o performance and irradiabon Nevis 12 o performance and irradiabon First look at Nevis 13 performance 2

3 ADC Architecture v Develop a hybrid ADC design: 4- bit pipeline ADC w/digital correcbon + 8- bit SAR ADC. Recall: 1.5b ADC Stage 1 (MSB) 1.5b ADC Stage 2 1.5b ADC Stage 3 1.5b ADC Stage 4 8b SAR ADC (LSB) Signal 4b pipeline ADC 8b SAR ADC v Each 1.5- bit stage in the pipeline outputs 3 possible digital codes and an analog residue (the input to following stage). v The next stage sees the same input voltage range, and may be 1- bit less accurate (i.e. first stage is 12- bit accurate, second stage is 11- bit accurate...). v For each 1.5- bit stage: v To determine calibrabon provide ±V ref /4 internally and force decision levels. 3

4 Digital Correc+on v V in = ±V ref /4, that is, near the decision levels of the ADC. We force the decision (+/nop/- ). v We do not need the input voltage to be accurate, just consistent. When a stage is being calibrated the upstream stages are disabled. v We correct the upstream stages using result of the previous stage, working from LSB to MSB. The correcbon should be most precise for the MSB

5 Test Chips v Nevis 1 test chip: 2 channel, 4- bit pipeline ADC with extended range (12- bits). Last 8- bits digibzed by commercial ADC. Verify the most significant bits, develop digital correcbon procedure. v Nevis 12 test chip: 2 channel, 12- bit ADC (4- bit pipeline ADC + 8- bit SAR). Verify 8- bit SAR. Digital correcbon on chip, correcbon constants stored on chip. Verify full 12- bit ADC performance. v Nevis 13 test chip: 4 channel, 12- bit ADC. Verify all aspects of ADC operabon, characterize chip- to- chip variability. 5

6 Nevis1 Chip 6

7 2 mm Nevis12 Chip 3 mm v Over 9% yield (~3 chips). v Power esbmate of 5 mw per ADC channel. 7

8 Nevis13 MDAC1 MDAC3 MDAC2 MDAC4 DDPU SAR 3.6 mm Vref Drivers Clock PLL I2C 3.6 mm 8

9 Characterizing an ADC v We digibze a pure sine wave and transform into frequency domain. v The dynamic performance is determined by comparing the harmonics and noise with the signal component of the input wave. v As input we apply 3 carrier frequencies, 2kHz, 1 MHz and 18 Mhz (~Nyquist), as close to the full amplitude as possible. The sine wave is sampled at 4 MHz. v Challenge of providing a very low noise signal and clock to chip. Test environment must be ~12- bit precision (.25%) throughout. v We use a socketed board for inibal tests, and a normal one for full precision tesbng (socket- induced parasibcs limit afainable precision). Test setup Test board (Nevis13) 9

10 ADC Performance Measures v DefiniBons of standard ADC characterisbcs: ENOB - EffecBve Number of Bits - Typically calculated by ~(SINAD- 1.76dB)/6.2. SFDR - Spurious Free Dynamic Range - Worst spurious value in the frequency spectrum w.r.t. the signal. For characterizabon the input signal is as close to the full range as possible. SINAD - SIgnal to Noise And DistorBon - The rabo of the signal amplitude to the root- sum- square of all spectral components, including harmonics. Generally, the SINAD gives the best indicabon of the ADC performance. SNR - Signal to Noise RaBo - The same as the SINAD except we remove (typically) the worst 5 harmonic components. INL/DNL - Integral/differenBal non- linearity - Difference between an actual step width and the ideal value (DNL) and the deviabon of the actual transfer funcbon from a straight line (INL). 1

11 Nevis 1 Performance Before Calibration After Calibration v FFT for f in = 1 MHz (lek) before calibrabon, (right) aker calibrabon. v COTS ADC on board also used to provide cross- check of performance. v Commercial ADC (digibzes last 8- bits) limits the maximum input signal to 85% of ADC prototypes full- scale, giving an effecbve resolubon of 11.7 bits. 11

12 Nevis 1 Irradia+on Tests Irradiated four Nevis 1 chips at Mass. General Hospital Proton Therapy Center. v Specialized, socketed board (right) for rad. tesbng. ADC chip powered and clocked, no other acbve elements. v Monitored current during irradiabng. v Results: All four chips funcboned before and aker the tests, with no unexpected changes in current during the test. v Chips with highest dose reafached to precision readout board and characterized: Internal structure of chip package visible on film used for alignment..142 Supply Current A Time s

13 Nevis 1 Post- irrada+on INL: +.8/-1.1 LSB DNL: +.3/-.2 LSB FFT, INL and DNL (with calibrabon) aker irradiabon show no degradabon across the full frequency range. 13

14 Nevis 12 SAR ADC ( fft / max ) [db] 1 2 log v First step was to validate 8 bit SAR. EnBrely new to this chip. At 1 MHz input at full scale: 1.8 ATLAS Upgrade ATLAS Upgrade Result of FFT.8.6 SFDR: SAR only.6 SAR only SAR only SINAD: ENOB: 7.68 Spur Freq. [MHz]: FFT: 7.7 Effective number of bits Freq. [MHz] ] 8 INL [LSB At 1 MHz input at full scale: Nevis12 Nevis12 Nevis INL: +.5/-.5 LSB Code ] 8 DNL [LSB At 1 MHz input at full scale: ATLAS Upgrade DNL: +.6/-.4 LSB v No frequency dependence observed (tested down to 2 khz). v It is cribcal that this works as designed: it is used to calibrate the pipeline stages. Code 14

15 Nevis 12 Precision Tests ( fft / max ) [db] 1 2 log v Apply calibrabon and perform socketed board precision tests. At 1 MHz input at full scale: At 1 MHz input at full scale: At 1 MHz input at full scale: ATLAS Upgrade 1 ATLAS Upgrade Nevis12 Nevis12 1 Nevis12 FFT: 11. Effective number of bits SFDR: SINAD: SNR: ENOB: 1.99 Spur Freq. [MHz]: Freq. [MHz] ] 12 INL [LSB INL: +.9/-1.2 LSB v No frequency dependence observed (tested down to 2 khz) v On socketed board with external V ref (fixed in Nevis 13) and digital correcbon applied we demonstrate 11 ENOB performance. Expect improvements in Nevis 13 with socketed board and internal V ref. Code ] 12 DNL [LSB ATLAS Upgrade DNL: +1.1/-.5 LSB Code 15

16 Nevis 12 Irradia+on Tests v v v v v Shielding Effective Number of Bits ATLAS Upgrade Max: 1.18 Min: 9.31 Mean: 9.79 RMS: Prepared a specialized board at Nevis for radiabon test. Nevis12 chip and signal input at right, FPGA, off board communicabons at lek separated by ~2cm. Due to the separabon we do not test the full precision of the chips (confirmed previously with Nevis 1 tests). RadiaBon board allowed chips to be read out constantly during test. Beam Tested integrated dose, single and triple redundant buffers, recalibrabon and SEE. ENOB stable through irradiation. ~1 ENOB expected on long boards for radiation tests. Readout and precision maintained to 2 MRad dose. Triple redundant buffers stable, single redundant buffers required refreshing (expected). Time [sec] ~1 ENOB expected 16

17 Nevis 12 SEE Tests v To reduce deadbme during SEE tests we implemented a Good Event filter in the FPGA. v When no signal is applied filter events +/- 4 ADC counts around the pedestal value. We only readout the (rare) codes outside this window. v TesBng at Nevis revealed non- radiabon related errors. These bad codes were masked offline during the irradiabon. The source of these codes is a clock duty cycle issue (fixed in Nevis 13, see Jaro's talk). 17

18 Nevis 12 SEE Tests v Three types of SEEs: Single- event- funcbon- interrupt (SEFI) - Constant ADC output is observed, an external reset returns the ADC to normal operabon (no latchup problems observed). Single- event- upset (SEU) - A transient, erroneous code. For analog signal path the errors are observed as small deviabons from the expected output value. For digital porbon of the chip (bit- flips) the errors are large deviabons from the pedestal value. Total SEE - sum of these errors. In determining the SEE cross- secbon we exclude the analog errors (primarily a resolubon effect). v Impact: With 25 devices, a safety factor of 2, and 1h fills (2 q - 1 each) expect 1.7 SEE events/fill. Less than 1 SEFI/fill requiring reset. 18

19 Nevis 13 v Nevis 13 chip was received May 16th and we have been able to begin tesbng on a socketed board. Completed inibal readout tests using internal reference voltage (w/o calibrabon) for all four channels. Completed socketed precision tests for one chip, one channel at 2 khz, 1 MHz, 18 MHz frequencies. Completed socketed precision tests for one chip, four channels at 1 MHz frequency. Completed socketed precision tests for ten chips, one channel at 1 MHz Verified calibrabon for ten chips, four channels. Completed 12hr+ test for bad codes in lab. 19

20 Nevis 13 First Tests v 1.6 ENOB on socketed board. v bad codes in the lab. v >9% yield. v Prelim. power measurement of 43 mw/ channel with everything included. ( fft / max ) [db] 1 2 log Nevis13, Ch.3 FFT: 1.6 Effective number of bits ATLAS Upgrade SFDR: SINAD: SNR: ENOB: 1.58 Spur Freq. [MHz]: Normal, non- socketed board in preparabon (socket induced parasibcs limit precision). Freq. [MHz] 2

21 Nevis 13 Variability v StarBng use of socketed board to invesbgate chip- to- chip variabon. <ENOB> = 1.36 ±.14 (expected) Determine spread in calibrabon constants v Preparing test setup to automate (as much as possible) measurements of parameters for all chips. v Non- socketed board in preparabon for precision tests ATLAS Internal Mean.63 RMS calibration constants, 12 1 Calibration Constant MDAC 1 [%] ATLAS Internal Mean 1.17 RMS.13 Variability of 1 chips Calibration Constant MDAC 3 [%] ATLAS Internal Mean.6 RMS Calibration Constant MDAC 2 [%] ATLAS Internal Mean 2.37 RMS Calibration Constant MDAC 4 [%] 21

22 Crosstalk and Satura+on v Crosstalk checked on Nevis 1 (shown), 12 and 13 chips. The input to one of the channels was grounded while a full- scale sine- wave was applied to the other channel. v RMS noise is.1 LSB RMS, no indicabon of crosstalk. Amplitude LSB Noise RMS =.1 LSB 12 Nevis 1 crosstalk Time µs v With Nevis 13 crosstalk with well saturated signals (>5% over max. scale) was checked on all four channels. fast, sine- wave signal, approx. every other sample over saturabon. slow (1 khz), sine- wave signal, with several hundred consecubve samples in saturabon. v No effect was observed. 22

23 Conclusions v Incremental program of development and tesbng has resulted in an ADC which successfully meets the specificabons. Nevis 13 reliability tesbng underway, irradiabon tesbng planned. v We now have at Nevis a chip with full funcbonality, which we believe will exceed 11 ENOB (on non- socketed board). Power consumpbon is ~43 mw/channel very radiabon tolerant 87.5 ns latency The technology is CMOS 8RF, easy interface to GBT for I2C. 23

24 Addi+onal Material 24

25 Analog SEE v Single- event- upset (SEU) - A transient, erroneous code. For analog signal path the errors are observed as small deviabons from the expected output value. v We measure a distribubon around expected value (central porbon of distribubon masked by filter). v With an analog SEUs cross- secbon of ~6 x 1-12 cm 2, expect ~2 analog SEE events/fill resulbng in a small decrease in the effecbve resolubon Masked Codes chip 1, 3 runs, codes 25

26 Nevis 1 Test Board Analog input Nevis 1 Chip Clock input Commercial 12 bit ADC USB output FPGA Direct path (green) for analog input to commercial ADC (AD9228) and separately through the Nevis1 chip, with the analog residue read by the AD9228 (white).

27 Nevis 12 Test Board v Nevis12 tesbng Over 9% yield for chips. Preliminary power estimate of 5 mw per ADC channel (including Vref drivers, band-gap, DDPU, serializer and SLVS drivers). Total ADC latency of 87.5 ns = (5 * 12.5 ns) (+ serializer) Simulation expects 61 ma total for the chip, we draw 56 ma. 27

28 Nevis 12 Block Diagram Channel 1 Serializer 2-Channel ADC Low-Voltage LVDS Foreground Digital Calibration and Bit Alignment V in1 V in2 Stage 1 1.5b MDAC Bandgap Generator Stage 1 1.5b MDAC Stage 2 1.5b MDAC Reference Buffers Stage 2 1.5b MDAC Stage 3 1.5b MDAC Bias Stage 3 1.5b MDAC Stage 4 1.5b MDAC Control Stage 4 1.5b MDAC Foreground Digital Calibration and Bit Alignment 8-bit SAR Clock Gen 8-bit SAR Digital Signal Processing (FPGA) and PC Channel 2 Serializer Low-Voltage LVDS 28

29 Nevis 13 Block Diagram 29