14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9640

Transcription

1 14-Bit, 8/15/125/15 MSPS, 1.8 V Dual Analog-to-Digital Converter AD964 FEATURES SNR = 71.8 dbc (72.8 dbfs) to MSPS SFDR = 85 dbc to MSPS Low power: MSPS SNR = 71.6 dbc (72.6 dbfs) to 7 15 MSPS SFDR = 84 dbc to 7 15 MSPS Low power: MSPS 1.8 V analog supply operation 1.8 V to 3.3V CMOS output supply or 1.8 V LVDS output supply Integer 1 to 8 input clock divider IF sampling frequencies to 45 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p Differential analog inputs with 65 MHz bandwidth ADC clock duty cycle stabilizer 95 db channel isolation/crosstalk Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes Integrated receive features Fast detect/threshold bits Composite signal monitor APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, WCDMA, LTE, CDMA2, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications VIN+A VIN A VREF SENSE CML RBIAS VIN B VIN+B FUNCTIONAL BLOCK DIAGRAM AVDD DVDD FD(:3)A FD BITS/THRESHOLD DETECT SHA REF SELECT SHA MULTICHIP SYNC ADC ADC AGND SYNC FD(:3)B SDIO/ SCLK/ DCS DFS PROGRAMMING DATA SIGNAL MONITOR DIVIDE 1TO 8 DUTY CYCLE STABILIZER FD BITS/THRESHOLD DETECT Figure 1. SPI CSB SIGNAL MONITOR DATA DRVDD DCO GENERATION SIGNAL MONITOR INTERFACE SMI SDFS SMI SCLK/ PDWN CMOS OUTPUT BUFFER CMOS OUTPUT BUFFER SMI SDO/ OEB DRGND D13A DA CLK+ CLK DCOA DCOB D13B PRODUCT HIGHLIGHTS 1. Integrated dual 14-bit, 8/15/125/15 MSPS ADC. 2. Fast overrange detect and signal monitor with serial output. 3. Signal monitor block with dedicated serial output mode. 4. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 45 MHz. 5. Operation from a single 1.8 V supply and a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. 6. A standard serial port interface that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and voltage reference mode. 7. Pin compatibility with the AD9627, AD , and the AD96 for a simple migration from 14 bits to 12 bits, 11 bits, or 1 bits. DB Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 916, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 AD964 TABLE OF CONTENTS Features... 1 Applications... 1 Functional Block Diagram... 1 Product Highlights... 1 Revision History... 3 General Description... 4 Specifications... 5 ADC DC Specifications AD964ABCPZ-8, AD964BCPZ-8, AD964ABCPZ-15, and AD964BCPZ ADC DC Specifications AD964ABCPZ-125, AD964BCPZ-125, AD964ABCPZ-15, and AD964BCPZ ADC AC Specifications AD964ABCPZ-8, AD964BCPZ-8, AD964ABCPZ-15, and AD964BCPZ ADC AC Specifications AD964ABCPZ-125, AD964BCPZ-125, AD964ABCPZ-15, and AD964BCPZ Digital Specifications... 9 Switching Specifications AD964ABCPZ-8, AD964BCPZ-8, AD964ABCPZ-15, and AD964BCPZ Switching Specifications AD964ABCPZ-125, AD964BCPZ-125, AD964ABCPZ-15, and AD964BCPZ Timing Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Equivalent Circuits Typical Performance Characteristics... 2 Theory of Operation ADC Architecture Analog Input Considerations Voltage Reference Clock Input Considerations Power Dissipation and Standby Mode... 3 Digital Outputs Timing ADC Overrange and Gain Control Fast Detect Overview ADC Fast Magnitude ADC Overrange (OR) Gain Switching Signal Monitor Peak Detector Mode RMS/MS Magnitude Mode Threshold Crossing Mode Additional Control Bits DC Correction Signal Monitor SPORT Output Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Channel/Chip Synchronization Serial Port Interface (SPI)... 4 Configuration Using the SPI... 4 Hardware Interface... 4 Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Table External Memory Map Memory Map Register Description Applications Information Design Guidelines Outline Dimensions... 5 Ordering Guide Rev. B Page 2 of 52

3 AD964 REVISION HISTORY 12/9 Rev. A to Rev. B Added CP-64-6 Package... Universal Changes to Ordering Guide /9 Rev. to Rev. A Changes to Applications Section and Product Highlights Section... 1 Changes to General Description Section... 3 Changes to Specifications Section... 4 Changes to Figure Changes to Figure Changes to Pin Configurations and Functional Descriptions Section Changes to Figure 11, Figure 12, Figure Change to Table Changes to ADC Overrange and Gain Control Section Changes to Signal Monitor Section Changes to Table Changes to Signal Monitor Period (Register x113 to Register x115) Section Added LVDS Operation Section Added Exposed Pad Notation to Outline Dimensions /7 Revision : Initial Version Rev. B Page 3 of 52

4 AD964 GENERAL DESCRIPTION The AD964 is a dual 14-bit, 8/15/125/15 MSPS analog-todigital converter (ADC). The AD964 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The AD964 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency. In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four MSBs, the user can quickly turn down the system gain to avoid an overrange condition. The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system. The ADC output data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface. The AD964 is available in a 64-lead LFCSP and is specified over the industrial temperature range of 4 C to +85 C. Rev. B Page 4 of 52

5 AD964 SPECIFICATIONS ADC DC SPECIFICATIONS AD964ABCPZ-8, AD964BCPZ-8, AD964ABCPZ-15, AND AD964BCPZ-15 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = 1. dbfs differential input, 1. V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 1. AD964ABCPZ- 8/AD964BCPZ-8 AD964ABCPZ- 15/AD964BCPZ-15 Parameter Temperature Min Typ Max Min Typ Max Unit RESOLUTION Full Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±.3 ±.6 ±.3 ±.6 % FSR Gain Error Full ±.2 ±3. ±.2 ±3. % FSR Differential Nonlinearity (DNL) 1 Full ±.9 ±.9 LSB 25 C ±.4 ±.4 LSB Integral Nonlinearity (INL) 1 Full ±5. ±5. LSB 25 C ±2. ±2. LSB MATCHING CHARACTERISTIC Offset Error Full ±.3 ±.6 ±.4 ±.7 % FSR Gain Error Full ±.1 ±.5 ±.1 ±.5 % FSR TEMPERATURE DRIFT Offset Error Full ±15 ±15 ppm/ C Gain Error Full ±95 ±95 ppm/ C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±2 ±15 ±2 ±15 mv Load 1. ma Full 7 7 mv INPUT REFERRED NOISE VREF = 1. V 25 C LSB rms ANALOG INPUT Input Span, VREF = 1. V Full 2 2 V p-p Input Capacitance 2 Full 8 8 pf VREF INPUT RESISTANCE Full 6 6 kω POWER SUPPLIES Supply Voltage AVDD, DVDD Full V DRVDD (CMOS Mode) Full V DRVDD (LVDS Mode) Full V Supply Current IAVDD 1, 3 Full ma IDVDD 1, 3 Full ma IDRVDD 1 (3.3 V CMOS) Full ma IDRVDD 1 (1.8 V CMOS) Full ma IDRVDD 1 (1.8 V LVDS) Full ma POWER CONSUMPTION DC Input Full mw Sine Wave Input 1 (DRVDD = 1.8 V) Full mw Sine Wave Input 1 (DRVDD = 3.3 V) Full mw Standby Power 4 Full mw Power-Down Power Full mw 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pf loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pins (CLK+, CLK ) inactive (set to AVDD or AGND). Rev. B Page 5 of 52

6 AD964 ADC DC SPECIFICATIONS AD964ABCPZ-125, AD964BCPZ-125, AD964ABCPZ-15, AND AD964BCPZ-15 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = 1. dbfs differential input, 1. V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 2. AD964ABCPZ-125/ AD964BCPZ-125 AD964ABCPZ-15/ AD964BCPZ-15 Parameter Temperature Min Typ Max Min Typ Max Unit RESOLUTION Full Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±.3 ±.6 ±.3 ±.6 % FSR Gain Error Full ±.2 ±3. ±.2 ±3. % FSR Differential Nonlinearity (DNL) 1 Full ±.9.95/+1.5 LSB 25 C ±.4.4/+.6 LSB Integral Nonlinearity (INL) 1 Full ±5. ±5. LSB 25 C ±2 ±2 LSB MATCHING CHARACTERISTIC Offset Error 25 C ±.4 ±.7 ±.4 ±.7 % FSR Gain Error 25 C ±.1 ±.6 ±.2 ±.6 % FSR TEMPERATURE DRIFT Offset Error Full ±15 ±15 ppm/ C Gain Error Full ±95 ±95 ppm/ C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±2 ±15 ±3 ±15 mv Load 1. ma Full 7 7 mv INPUT REFERRED NOISE VREF = 1. V 25 C LSB rms ANALOG INPUT Input Span, VREF = 1. V Full 2 2 V p-p Input Capacitance 2 Full 8 8 pf VREF INPUT RESISTANCE Full 6 6 kω POWER SUPPLIES Supply Voltage AVDD, DVDD Full V DRVDD (CMOS Mode) Full V DRVDD (LVDS Mode) Full V Supply Current IAVDD 1, 3 Full ma IDVDD 1, 3 Full 42 5 ma IDRVDD 1 (3.3 V CMOS) Full ma IDRVDD 1 (1.8 V CMOS) Full ma IDRVDD 1 (1.8 V LVDS) POWER CONSUMPTION DC Input Full mw Sine Wave Input 1 (DRVDD = 1.8 V) Full mw Sine Wave Input 1 (DRVDD = 3.3 V) Full 91 1 mw Standby Power 4 Full mw Power-Down Power Full mw 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pf loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pins (CLK+, CLK ) inactive (set to AVDD or AGND). Rev. B Page 6 of 52

7 AD964 ADC AC SPECIFICATIONS AD964ABCPZ-8, AD964BCPZ-8, AD964ABCPZ-15, AND AD964BCPZ-15 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = 1. dbfs differential input, 1. V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 3. AD964ABCPZ-8/ AD964BCPZ-8 AD964ABCPZ-15/ AD964BCPZ-15 Parameter 1 Temperature Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fin = 2.3 MHz 25 C db fin = 7 MHz 25 C db Full db fin = 14 MHz 25 C db fin = 2 MHz 25 C db SIGNAL-TO-NOISE AND DISTORTION (SINAD) fin = 2.3 MHz 25 C db fin = 7 MHz 25 C db Full db fin = 14 MHz 25 C db fin = 2 MHz 25 C db EFFECTIVE NUMBER OF BITS (ENOB) fin = 2.3 MHz 25 C Bits fin = 7 MHz 25 C Bits fin = 14 MHz 25 C Bits fin = 2 MHz 25 C Bits WORST SECOND OR THIRD HARMONIC fin = 2.3 MHz 25 C dbc fin = 7 MHz 25 C dbc Full dbc fin = 14 MHz 25 C dbc fin = 2 MHz 25 C dbc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fin = 2.3 MHz 25 C dbc fin = 7 MHz 25 C dbc Full dbc fin = 14 MHz 25 C dbc fin = 2 MHz 25 C dbc WORST OTHER HARMONIC OR SPUR fin = 2.3 MHz 25 C dbc fin = 7 MHz 25 C dbc Full dbc fin = 14 MHz 25 C dbc fin = 2 MHz 25 C dbc TWO TONE SFDR fin = 29.1 MHz, 32.1 MHz ( 7 dbfs) 25 C dbc fin = MHz, MHz ( 7 dbfs) 25 C dbc CROSSTALK 2 Full db ANALOG INPUT BANDWIDTH 25 C MHz 1 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 1 MHz with 1 dbfs on one channel and no input on the alternate channel. Rev. B Page 7 of 52

8 AD964 ADC AC SPECIFICATIONS AD964ABCPZ-125, AD964BCPZ-125, AD964ABCPZ-15, AND AD964BCPZ 15 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = 1. dbfs differential input, 1. V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 4. AD964ABCPZ-125 AD964BCPZ-125 AD964ABCPZ-15/ AD964BCPZ-15 Parameter 1 Temperature Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fin = 2.3 MHz 25 C db fin = 7 MHz 25 C db Full db fin = 14 MHz 25 C db fin = 2 MHz 25 C db SIGNAL-TO-NOISE AND DISTORTION (SINAD) fin = 2.3 MHz 25 C db fin = 7 MHz 25 C db Full db fin = 14 MHz 25 C db fin = 2 MHz 25 C db EFFECTIVE NUMBER OF BITS (ENOB) fin = 2.3 MHz 25 C Bits fin = 7 MHz 25 C Bits fin = 14 MHz 25 C Bits fin = 2 MHz 25 C Bits WORST SECOND OR THIRD HARMONIC fin = 2.3 MHz 25 C dbc fin = 7 MHz 25 C dbc Full dbc fin = 14 MHz 25 C dbc fin = 2 MHz 25 C dbc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fin = 2.3 MHz 25 C dbc fin = 7 MHz 25 C dbc Full dbc fin = 14 MHz 25 C dbc fin = 2 MHz 25 C dbc WORST OTHER HARMONIC OR SPUR fin = 2.3 MHz 25 C dbc fin = 7 MHz 25 C 89 9 dbc Full 8 8 dbc fin = 14 MHz 25 C 89 9 dbc fin = 2 MHz 25 C 89 9 dbc TWO TONE SFDR fin = 29.1 MHz, 32.1 MHz ( 7 dbfs) 25 C dbc fin = MHz, MHz ( 7 dbfs) 25 C dbc CROSSTALK 2 Full db ANALOG INPUT BANDWIDTH 25 C MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 1 MHz with 1 dbfs on one channel and no input on the alternate channel. Rev. B Page 8 of 52

9 DIGITAL SPECIFICATIONS Rev. B Page 9 of 52 AD964 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = 1. dbfs differential input, 1. V internal reference, and DCS enabled, unless otherwise noted. Table 5. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK ) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 V Differential Input Voltage Full.2 6 V p-p Input Voltage Range Full AGND.3 AVDD V Input Common-Mode Range Full 1.1 AVDD V High Level Input Voltage Full V Low Level Input Voltage Full.8 V High Level Input Current Full 1 +1 μa Low Level Input Current Full 1 +1 μa Input Capacitance Full 4 pf Input Resistance Full kω SYNC INPUT Logic Compliance CMOS Internal Bias Full 1.2 V Input Voltage Range Full AGND.3 AVDD V High Level Input Voltage Full V Low Level Input Voltage Full.8 V High Level Input Current Full 1 +1 μa Low Level Input Current Full 1 +1 μa Input Capacitance Full 4 pf Input Resistance Full kω LOGIC INPUT (CSB) 1 High Level Input Voltage Full V Low Level Input Voltage Full.6 V High Level Input Current Full 1 +1 μa Low Level Input Current Full μa Input Resistance Full 26 kω Input Capacitance Full 2 pf LOGIC INPUT (SCLK/DFS) 2 High Level Input Voltage Full V Low Level Input Voltage Full.6 V High Level Input Current (VIN = 3.3 V) Full μa Low Level Input Current Full 1 +1 μa Input Resistance Full 26 kω Input Capacitance Full 2 pf LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS) 1 High Level Input Voltage Full V Low Level Input Voltage Full.6 V High Level Input Current Full 1 +1 μa Low Level Input Current Full μa Input Resistance Full 26 kω Input Capacitance Full 5 pf LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN) 2 High Level Input Voltage Full V Low Level Input Voltage Full.6 V High Level Input Current (VIN = 3.3 V) Full μa Low Level Input Current Full 1 +1 μa Input Resistance Full 26 kω Input Capacitance Full 5 pf

10 AD964 Parameter Temperature Min Typ Max Unit DIGITAL OUTPUTS CMOS Mode DRVDD = 3.3 V High Level Output Voltage (IOH = 5 μa) Full 3.29 V High Level Output Voltage (IOH =.5 ma) Full 3.25 V Low Level Output Voltage (IOL = 1.6 ma) Full.2 V Low Level Output Voltage (IOL = 5 μa) Full.5 V CMOS Mode DRVDD = 1.8 V High Level Output Voltage (IOH = 5 μa) Full 1.79 V High Level Output Voltage (IOH =.5 ma) Full 1.75 V Low Level Output Voltage (IOL = 1.6 ma) Full.2 V Low Level Output Voltage (IOL = 5 μa) Full.5 V LVDS Mode DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Full mv Output Offset Voltage (VOS), ANSI Mode Full V Differential Output Voltage (VOD), Reduced Swing Mode Full mv Output Offset Voltage (VOS), Reduced Swing Mode Full V 1 Pull up. 2 Pull down. SWITCHING SPECIFICATIONS AD964ABCPZ-8, AD964BCPZ-8, AD964ABCPZ-15, AND AD964BCPZ-15 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = 1. dbfs differential input, 1. V internal reference, DCS enabled, unless otherwise noted. Table 6. AD964ABCPZ-8 AD964BCPZ-8 AD964ABCPZ-15/ AD964BCPZ-15 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full MHz Conversion Rate DCS Enabled 1 Full MSPS DCS Disabled 1 Full MSPS CLK Period Divide by 1 Mode (tclk) Full ns CLK Pulse Width High Divide by 1 Mode, DCS Enabled Full ns Divide by 1 Mode, DCS Disabled Full ns Divide by 2 Mode, DCS Enabled Full ns Divide by 3 Through 8, DCS Enabled Full.8.8 ns DATA OUTPUT PARAMETERS (DATA, FD) CMOS Mode DRVDD = 3.3 V Data Propagation Delay (tpd) 2 Full ns DCO Propagation Delay (tdco) Full ns Setup Time (ts) Full ns Hold Time (th) Full ns CMOS Mode DRVDD = 1.8 V Data Propagation Delay (tpd) 2 Full ns DCO Propagation Delay (tdco) Full ns LVDS Mode DRVDD = 1.8 V Data Propagation Delay (tpd) 2 Full ns DCO Propagation Delay (tdco) Full ns Rev. B Page 1 of 52

11 AD964 AD964ABCPZ-8 AD964BCPZ-8 AD964ABCPZ-15/ AD964BCPZ-15 Parameter Temp Min Typ Max Min Typ Max Unit CMOS Mode Pipeline Delay (Latency) Full Cycles LVDS Mode Pipeline Delay (Latency) 12/ /12.5 Cycles Channel A/Channel B Aperture Delay (ta) Full ns Aperture Uncertainty (Jitter, tj) Full.1.1 ps rms Wake-Up Time 3 Full μs OUT-OF-RANGE RECOVERY TIME Full 2 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Output propagation delay is measured from CLK 5% transition to DATA 5% transition, with 5 pf load. 3 Wake-up time is dependent on the value of the decoupling capacitors. SWITCHING SPECIFICATIONS AD964ABCPZ-125, AD964BCPZ-125, AD964ABCPZ-15, AND AD964BCPZ-15 AVDD = 1.8 V, DVDD = 1.8V, DRVDD = 3.3 V, maximum sample rate, VIN = 1. dbfs differential input, 1. V internal reference, DCS enabled, unless otherwise noted. Table 7. AD964ABCPZ-125/ AD964BCPZ-125 AD964ABCPZ-15/ AD964BCPZ-15 Parameter Temperature Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full MHz Conversion Rate DCS Enabled 1 Full MSPS DCS Disabled 1 Full MSPS CLK Period Divide by 1 Mode (tclk) Full ns CLK Pulse Width High Divide by 1 Mode, DCS Enabled Full ns Divide by 1 Mode, DCS Disabled Full ns Divide by 2 Mode, DCS Enabled Full ns Divide by 3 Through 8, DCS Enabled Full.8.8 ns DATA OUTPUT PARAMETERS (DATA, FD) CMOS Mode DRVDD = 3.3 V Data Propagation Delay (tpd) 2 Full ns DCO Propagation Delay (tdco) Full ns Setup Time (ts) Full ns Hold Time (th) Full ns CMOS Mode DRVDD = 1.8 V Data Propagation Delay (tpd) 2 Full ns DCO Propagation Delay (tdco) Full ns LVDS Mode DRVDD = 1.8 V Data Propagation Delay (tpd) 2 Full ns DCO Propagation Delay (tdco) Full ns CMOS Mode Pipeline Delay (Latency) Full Cycles LVDS Mode Pipeline Delay (Latency) 12/ /12.5 Cycles Channel A/Channel B Aperture Delay (ta) Full ns Aperture Uncertainty (Jitter, tj) Full.1.1 ps rms Wake-Up Time 3 Full μs OUT-OF-RANGE RECOVERY TIME Full 3 3 Cycles 1 Conversion rate is the clock rate after the divider. 2 Output propagation delay is measured from CLK 5% transition to DATA 5% transition, with 5 pf load. 3 Wake-up time is dependent on the value of the decoupling capacitors. Rev. B Page 11 of 52

12 AD964 TIMING SPECIFICATIONS Table 8. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS tssync SYNC to rising edge of CLK setup time.24 ns thsync SYNC to rising edge of CLK hold time.4 ns SPI TIMING REQUIREMENTS tds Setup time between the data and the rising edge of SCLK 2 ns tdh Hold time between the data and the rising edge of SCLK 2 ns tclk Period of the SCLK 4 ns ts Setup time between CSB and SCLK 2 ns th Hold time between CSB and SCLK 2 ns thigh SCLK pulse width high 1 ns tlow SCLK pulse width low 1 ns ten_sdio Time required for the SDIO pin to switch from an input to an 1 ns output relative to the SCLK falling edge tdis_sdio Time required for the SDIO pin to switch from an output to 1 ns an input relative to the SCLK rising edge SPORT TIMING REQUIREMENTS tcssclk Delay from rising edge of CLK+ to rising edge of SMI SCLK ns tssclksdo Delay from rising edge of SMI SCLK to SMI SDO ns tssclksdfs Delay from rising edge of SMI SCLK to SMI SDFS ns Timing Diagrams N N+ 1 N+2 N+ 3 t A N+ 4 N+ 5 N+ 6 N+ 7 N+ 8 CLK+ t CLK CLK CH A/B DATA N 13 t PD N 12 N 11 N 1 N 9 N 8 N 7 N 6 N 5 N 4 CH A/B FAST DETECT N 3 N 2 N 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 t S th t DCO t CLK DCOA/DCOB Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode ) Rev. B Page 12 of 52

13 AD964 N N + 1 N + 2 N + 3 t A N + 4 N + 5 N + 6 N + 7 N + 8 CLK+ t CLK CLK CH A/CH B DATA t PD A B A B A B A B A B A B A B A B A B A CH A/CH B FAST DETECT N 13 N 12 N 11 N 1 N 9 N 8 N 7 N 6 N 5 N 4 A B A B A B A B A B A B A B A B A B A N 7 N 6 N 5 N 4 N 3 N 2 N 1 N N + 1 N + 2 t DCO t CLK DCO+ DCO Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode 1 Through Fast Detect Mode 5) CLK+ t SSYNC t HSYNC SYNC Figure 4. SYNC Input Timing Requirements CLK+ CLK t CSSCLK SMI SCLK t SSCLKSDFS t SSCLKSDO SMI SDFS SMI SDO DATA Figure 5. Signal Monitor SPORT Output Timing (Divide by 2 Mode) DATA Rev. B Page 13 of 52

14 AD964 ABSOLUTE MAXIMUM RATINGS Table 9. Parameter ELECTRICAL AVDD, DVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD VIN+A/VIN+B, VIN A/VIN B to AGND CLK+, CLK to AGND SYNC to AGND VREF to AGND SENSE to AGND CML to AGND RBIAS to AGND CSB to AGND SCLK/DFS to DRGND SDIO/DCS to DRGND SMI SDO/OEB SMI SCLK/PDWN SMI SDFS DA/DB through D13A/D13B to DRGND FDA/FDB through FD3A/FD3B to DRGND DCOA/DCOB to DRGND ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating.3 V to +2. V.3 V to +3.9 V.3 V to +.3 V 3.9 V to +2. V.3 V to AVDD +.2 V.3 V to +3.9 V.3 V to +3.9 V.3 V to AVDD +.2 V.3 V to AVDD +.2 V.3 V to AVDD +.2 V.3 V to AVDD +.2 V.3 V to +3.9 V.3 V to +3.9 V.3 V to DRVDD +.3 V.3 V to DRVDD +.3 V.3 V to DRVDD +.3 V.3 V to DRVDD +.3 V.3 V to DRVDD +.3 V.3 V to DRVDD +.3 V.3 V to DRVDD +.3 V 4 C to +85 C 15 C 65 C to +15 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints and maximizes the thermal capability of the package. Table 1. Thermal Resistance Package Type 64-lead LFCSP 9 mm 9 mm Airflow Velocity (m/s) θja 1, 2 θjc 1, 3 θjb 1, 4 Unit C/W C/W C/W 1 JEDEC 51-7, plus JEDEC S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method Per JEDEC JESD51-8 (still air). Typical θja is specified for a 4-layer PCB with a solid ground plane. As shown, airflow improves heat dissipation, which reduces θja. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the θja. ESD CAUTION Rev. B Page 14 of 52

15 AD964 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DRGND D5B D4B D3B D2B D1B DB (LSB) DVDD FD3B FD2B FD1B FDB SYNC CSB CLK CLK+ DRVDD 1 D6B 2 D7B 3 D8B 4 D9B 5 D1B 6 D11B 7 D12B 8 D13B (MSB) 9 DCOB 1 DCOA 11 DA (LSB) 12 D1A 13 D2A 14 D3A 15 D4A 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN (BOTTOM OF PACKAGE) AD964 PARALLEL CMOS TOP VIEW (Not to Scale) 48 SCLK/DFS 47 SDIO/DCS 46 AVDD 45 AVDD 44 VIN+B 43 VIN B 42 RBIAS 41 CML 4 SENSE 39 VREF 38 VIN A 37 VIN+A 36 AVDD 35 SMI SDFS 34 SMI SCLK/PDWN 33 SMI SDO/OEB D5A D6A D7A DRGND DRVDD D8A D9A DVDD D1A D11A D12A D13A (MSB) FDA FD1A FD2A FD3A NOTES 1. NC = NO CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 6. Pin Configuration, LFCSP Parallel CMOS (Top View) Table 11. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 2, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). AGND, Exposed Pad Ground The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN A Input Differential Analog Input Pin ( ) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN B Input Differential Analog Input Pin ( ) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 4 SENSE Input Voltage Reference Mode Select. See Table 14 for details. 42 RBIAS Input/Output External Reference Bias Resistor. 41 CML Output Common Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input True. 5 CLK Input ADC Clock Input Complement. Rev. B Page 15 of 52

16 AD964 Pin No. Mnemonic Type Description ADC Fast Detect Outputs 29 FDA Output Channel A Fast Detect Indicator. See Table 18 for details. 3 FD1A Output Channel A Fast Detect Indicator. See Table 18 for details. 31 FD2A Output Channel A Fast Detect Indicator. See Table 18 for details. 32 FD3A Output Channel A Fast Detect Indicator. See Table 18 for details. 53 FDB Output Channel B Fast Detect Indicator. See Table 18 for details. 54 FD1B Output Channel B Fast Detect Indicator. See Table 18 for details. 55 FD2B Output Channel B Fast Detect Indicator. See Table 18 for details. 56 FD3B Output Channel B Fast Detect Indicator. See Table 18 for details. Digital Inputs 52 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 12 DA (LSB) Output Channel A CMOS Output Data. 13 D1A Output Channel A CMOS Output Data. 14 D2A Output Channel A CMOS Output Data. 15 D3A Output Channel A CMOS Output Data. 16 D4A Output Channel A CMOS Output Data. 17 D5A Output Channel A CMOS Output Data. 18 D6A Output Channel A CMOS Output Data. 19 D7A Output Channel A CMOS Output Data. 22 D8A Output Channel A CMOS Output Data. 23 D9A Output Channel A CMOS Output Data. 25 D1A Output Channel A CMOS Output Data. 26 D11A Output Channel A CMOS Output Data. 27 D12A Output Channel A CMOS Output Data. 28 D13A (MSB) Output Channel A CMOS Output Data. 58 DB (LSB) Output Channel B CMOS Output Data. 59 D1B Output Channel B CMOS Output Data. 6 D2B Output Channel B CMOS Output Data. 61 D3B Output Channel B CMOS Output Data. 62 D4B Output Channel B CMOS Output Data. 63 D5B Output Channel B CMOS Output Data. 2 D6B Output Channel B CMOS Output Data. 3 D7B Output Channel B CMOS Output Data. 4 D8B Output Channel B CMOS Output Data. 5 D9B Output Channel B CMOS Output Data. 6 D1B Output Channel B CMOS Output Data. 7 D11B Output Channel B CMOS Output Data. 8 D12B Output Channel B CMOS Output Data. 9 D13B (MSB) Output Channel B CMOS Output Data. 11 DCOA Output Channel A Data Clock Output. 1 DCOB Output Channel B Data Clock Output. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low). Serial Port 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode. Rev. B Page 16 of 52

17 AD964 PIN 1 INDICATOR DRGND D+ (LSB) D (LSB) FD3+ FD3 FD2+ FD2 DVDD FD1+ FD1 FD+ FD SYNC CSB CLK CLK+ DRVDD 1 D1 2 D1+ 3 D2 4 D2+ 5 D3 6 D3+ 7 D4 8 D4+ 9 DCO 1 DCO+ 11 D5 12 D5+ 13 D6 14 D6+ 15 D7 16 EXPOSED PADDLE, PIN (BOTTOM OF PACKAGE) AD964 PARALLEL LVDS TOP VIEW (Not to Scale) 48 SCLK/DFS 47 SDIO/DCS 46 AVDD 45 AVDD 44 VIN+B 43 VIN B 42 RBIAS 41 CML 4 SENSE 39 VREF 38 VIN A 37 VIN+A 36 AVDD 35 SMI SDFS 34 SMI SCLK/PDWN 33 SMI SDO/OEB D7+ D8 D8+ DRGND DRVDD D9 D9+ DVDD D1 D1+ D11 D11+ D12 D12+ (MSB) + (MSB) D13 D13 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 7. Pin Configuration, LFCSP LVDS (Top View) Table 12. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type Function ADC Power Supplies 2, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). AGND, Exposed Pad Ground The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN A Input Differential Analog Input Pin ( ) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN B Input Differential Analog Input Pin ( ) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 4 SENSE Input Voltage Reference Mode Select. See Table 14 for details. 42 RBIAS Input/Output External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input True. 5 CLK Input ADC Clock Input Complement. ADC Fast Detect Outputs 54 FD+ Output Channel A/Channel B LVDS Fast Detect Indicator True. See Table 18 for details. 53 FD Output Channel A/Channel B LVDS Fast Detect Indicator Complement. See Table 18 for details. 56 FD1+ Output Channel A/Channel B LVDS Fast Detect Indicator 1 True. See Table 18 for details. 55 FD1 Output Channel A/Channel B LVDS Fast Detect Indicator 1 Complement. See Table 18 for details. 59 FD2+ Output Channel A/Channel B LVDS Fast Detect Indicator 2 True. See Table 18 for details. 58 FD2 Output Channel A/Channel B LVDS Fast Detect Indicator 2 Complement. See Table 18 for details. 61 FD3+ Output Channel A/Channel B LVDS Fast Detect Indicator 3 True. See Table 18 for details. 6 FD3 Output Channel A/Channel B LVDS Fast Detect Indicator 3 Complement. See Table 18 for details. Rev. B Page 17 of 52

18 AD964 Pin No. Mnemonic Type Function Digital Inputs 52 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 63 D+ (LSB) Output Channel A/Channel B LVDS Output Data True. 62 D (LSB) Output Channel A/Channel B LVDS Output Data Complement. 3 D1+ Output Channel A/Channel B LVDS Output Data 1 True. 2 D1 Output Channel A/Channel B LVDS Output Data 1 Complement. 5 D2+ Output Channel A/Channel B LVDS Output Data 2 True. 4 D2 Output Channel A/Channel B LVDS Output Data 2 Complement. 7 D3+ Output Channel A/Channel B LVDS Output Data 3 True. 6 D3 Output Channel A/Channel B LVDS Output Data 3 Complement. 9 D4+ Output Channel A/Channel B LVDS Output Data 4 True. 8 D4 Output Channel A/Channel B LVDS Output Data 4 Complement. 13 D5+ Output Channel A/Channel B LVDS Output Data 5 True. 12 D5 Output Channel A/Channel B LVDS Output Data 5 Complement. 15 D6+ Output Channel A/Channel B LVDS Output Data 6 True. 14 D6 Output Channel A/Channel B LVDS Output Data 6 Complement. 17 D7+ Output Channel A/Channel B LVDS Output Data 7 True. 16 D7 Output Channel A/Channel B LVDS Output Data 7 Complement. 19 D8+ Output Channel A/Channel B LVDS Output Data 8 True. 18 D8 Output Channel A/Channel B LVDS Output Data 8 Complement. 23 D9+ Output Channel A/Channel B LVDS Output Data 9 True. 22 D9 Output Channel A/Channel B LVDS Output Data 9 Complement. 26 D1+ Output Channel A/Channel B LVDS Output Data 1 True. 25 D1 Output Channel A/Channel B LVDS Output Data 1 Complement. 28 D11+ Output Channel A/Channel B LVDS Output Data 11 True. 27 D11 Output Channel A/Channel B LVDS Output Data 11 Complement. 3 D12+ Output Channel A/Channel B LVDS Output Data 12 True. 29 D12 Output Channel A/Channel B LVDS Output Data 12 Complement. 32 D13+ (MSB) Output Channel A/Channel B LVDS Output Data 13 True. 31 D13 (MSB) Output Channel A/Channel B LVDS Output Data 13 Complement. 11 DCO+ Output Channel A/Channel B LVDS Data Clock Output True. 1 DCO Output Channel A/Channel B LVDS Data Clock Output Complement. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low). Signal Monitor Ports 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode. Rev. B Page 18 of 52

19 AD964 EQUIVALENT CIRCUITS DVDD VIN SCLK/DFS 26kΩ 1kΩ Figure 8. Equivalent Analog Input Circuit Figure 12. Equivalent SCLK/DFS Input Circuit AVDD CLK+ 1kΩ 1.2V 1kΩ CLK SENSE 1kΩ Figure 9. Equivalent Clock Input Circuit Figure 13. Equivalent SENSE Circuit DRVDD DVDD CSB 26kΩ 1kΩ DVDD DRGND Figure 1. Digital Output Figure 14. Equivalent CSB Input Circuit DRVDD DVDD AVDD SDIO/DCS 26kΩ 1kΩ DVDD VREF 6kΩ DRVDD Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit Figure 15. Equivalent VREF Circuit Rev. B Page 19 of 52

20 AD964 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V; DVDD = 1.8 V; DRVDD = 3.3 V; sample rate = 15 MSPS, DCS enabled, 1 V internal reference; 2 V p-p differential input; VIN = 1. dbfs; and 64k sample; TA = 25 C, unless otherwise noted. 2 15MSPS 1dBFS SNR = 71.9dBc (72.9dBFS) ENOB = 11.8 BITS SFDR = 86dBc 2 15MSPS 1dBFS SNR = 7.9dBc (71.9dBFS) ENOB = 11.6 BITS SFDR = 85.1dBc AMPLITUDE (dbfs) SECOND HARMONIC THIRD HARMONIC AMPLITUDE (dbfs) SECOND HARMONIC THIRD HARMONIC FREQUENCY (MHz) Figure 16. AD Single-Tone FFT with fin = 2.3 MHz FREQUENCY (MHz) Figure 19. AD Single-Tone FFT with fin = 14.3 MHz 2 15MSPS 1dBFS SNR = 71.7dBc (72.7dBFS) ENOB = 11.8 BITS SFDR = 89.9dBc 2 15MSPS 1dBFS SNR = 7dBc (71dBFS) ENOB = 11.5 BITS SFDR = 8dBc AMPLITUDE (dbfs) THIRD HARMONIC SECOND HARMONIC AMPLITUDE (dbfs) THIRD HARMONIC SECOND HARMONIC FREQUENCY (MHz) Figure 17. AD Single-Tone FFT with fin = 3.3 MHz FREQUENCY (MHz) Figure 2. AD Single-Tone FFT with fin = 2.3 MHz 2 15MSPS 1dBFS SNR = 71.5dBc (72.5dBFS) ENOB = 11.7 BITS SFDR = 84dBc 2 15MSPS 1dBFS SNR = 68dBc (69dBFS) ENOB = 11 BITS SFDR = 72.4dB AMPLITUDE (dbfs) SECOND HARMONIC THIRD HARMONIC AMPLITUDE (dbfs) THIRD HARMONIC SECOND HARMONIC FREQUENCY (MHz) Figure 18. AD Single-Tone FFT with fin = 7 MHz FREQUENCY (MHz) Figure 21. AD Single-Tone FFT with fin = 337 MHz Rev. B Page 2 of 52

21 AD MSPS 1dBFS SNR = 65dBc (66dBFS) ENOB = 1.4 BITS SFDR = 7.dB 2 125MSPS 1dBFS SNR = 71.8dBc (72.8dBFS) ENOB = 11.7 BITS SFDR = 85dBc AMPLITUDE (dbfs) SECOND HARMONIC THIRD HARMONIC AMPLITUDE (dbfs) SECOND HARMONIC THIRD HARMONIC FREQUENCY (MHz) FREQUENCY (MHz) Figure 22. AD Single-Tone FFT with fin = 44 MHz Figure 25. AD Single-Tone FFT with fin = 7 MHz MSPS 1dBFS SNR = 72.3dBc (73.3dBFS) ENOB = 11.8 BITS SFDR = 88.4dBc MSPS 1dBFS SNR = 71.4dBc (72.4dBFS) ENOB = 11.7 BITS SFDR = 87.1dBc AMPLITUDE (dbfs) SECOND HARMONIC THIRD HARMONIC AMPLITUDE (dbfs) SECOND HARMONIC THIRD HARMONIC FREQUENCY (MHz) FREQUENCY (MHz) Figure 23. AD Single-Tone FFT with fin = 2.3 MHz Figure 26. AD Single-Tone FFT with fin = 14 MHz MSPS 1dBFS SNR = 72.1dBc (73.1dBFS) ENOB = 11.8 BITS SFDR = 89.1dBc MSPS 1dBFS SNR = 7.8dBc (71.8dBFS) ENOB = 11.6 BITS SFDR = 8.5dBc AMPLITUDE (dbfs) THIRD HARMONIC SECOND HARMONIC AMPLITUDE (dbfs) THIRD HARMONIC SECOND HARMONIC FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. AD Single-Tone FFT with fin = 3.3 MHz Figure 27. AD Single-Tone FFT with fin = 2 MHz Rev. B Page 21 of 52

22 AD SFDR (dbfs) 9 SFDR = +25 C SNR/SFDR (dbc AND dbfs) SNR (dbfs) SFDR (dbc) SNR (dbc) SNR/SFDR (dbc) SNR = 4 C SFDR = +85 C SFDR = 4 C 2 85dB REFERENCE LINE SNR = +25 C SNR = +85 C INPUT AMPLITUDE (dbfs) INPUT FREQUENCY (MHz) Figure 28. AD Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fin = 2.3 MHz SNR/SFDR (dbc AND dbfs) SFDR (dbfs) SNR (dbfs) SFDR (dbc) INPUT AMPLITUDE (dbfs) SNR (dbc) 85dB REFERENCE LINE Figure 29. AD Single-Tone SFDR vs. Input Amplitude with fin = MHz GAIN/OFFSET ERROR (%FSR) Figure 31. AD Single-Tone SNR/SFDR vs. Input Frequency (fin) and Temperature with 1 V p-p Full Scale OFFSET GAIN TEMPERATURE ( C) Figure 32. AD964 Gain and Offset vs. Temperature SNR/SFDR (dbc) SNR = 4 C SFDR = +25 C SFDR = +85 C SNR = +25 C SNR = +85 C INPUT FREQUENCY (MHz) SFDR = 4 C Figure 3. AD Single-Tone SNR/SFDR vs. Input Frequency (fin) and Temperature with 2 V p-p Full Scale SNR/SFDR (dbc AND dbfs) SFDR (dbc) IMD3 (dbc) SFDR (dbfs) IMD3 (dbfs) INPUT AMPLITUDE (dbfs) Figure 33. AD Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fin1 = 29.1 MHz, fin2 = 32.1 MHz, fs = 15 MSPS Rev. B Page 22 of 52

23 AD964 SNR/SFDR (dbc AND dbfs) SFDR (dbc) IMD3 (dbc) IMD3 (dbfs) SFDR (dbfs) AMPLITUDE (dbfs) MSPS 7dBFS 7dBFS SFDR = 83.8dBc (9.8dBFS) INPUT AMPLITUDE (dbfs) Figure 34. AD Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fin1 = MHz, fin2 = MHz, fs = 15 MSPS FREQUENCY (MHz) Figure 37. AD Two-Tone FFT with fin1 = MHz and fin2 = MHz NPR = 64.7dBc 18.5MHz NOTCH WIDTH = 3MHz AMPLITUDE (dbfs) AMPLITUDE (dbfs) FREQUENCY (MHz) Figure 35. AD , Two 64 k WCDMA Carriers with fin = 17 MHz, fs = MSPS FREQUENCY (MHz) Figure 38. AD964 Noise Power Ratio (NPR) 2 15 MSPS 7dBFS 7dBFS SFDR = 86.1dBc (93dBFS) 1 95 SFDR SIDE A AMPLITUDE (dbfs) FREQUENCY (MHz) Figure 36. AD Two-Tone FFT with fin1 = 29.1 MHz and fin2 = 32.1 MHz SNR/SFDR (dbc) SFDR SIDE B SNR SIDE B SNR SIDE A CLOCK FREQUENCY (Msps) Figure 39. AD Single-Tone SNR/SFDR vs. Clock Frequency (fs) with fin = 2.3 MHz Rev. B Page 23 of 52

24 AD LSB rms 1 95 SFDR DCS ON NUMBER OF HITS (1M) SNR/SFDR (dbc) SFDR DCS OFF SNR DCS ON SNR DCS OFF N 4 N 3 N 2 N 1 N N + 1 N + 2 N + 3 N + 4 OUTPUT CODE Figure 4. AD964 Grounded Input Histogram DUTY CYCLE (%) Figure 43. AD964 SNR/SFDR vs. Duty Cycle with fin = 1.3 MHz 9 SFDR INL ERROR (LSB).5.5 SNR/SFDR (dbc) ,24 12,288 14,336 16,384 OUTPUT CODE Figure 41. AD964 INL with fin = 1.3 MHz SNR INPUT COMMON-MODE VOLTAGE (V) Figure 44. AD964 SNR/SFDR vs. Input Common Mode Voltage (VCM) with fin = 3 MHz DNL ERROR (LSB) ,24 12,288 14,336 16,384 OUTPUT CODE Figure 42. AD964 DNL with fin = 1.3 MHz Rev. B Page 24 of 52

25 AD964 THEORY OF OPERATION The AD964 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fs/2 frequency segment from dc to 2 MHz using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 45 MHz analog input is permitted but occurs at the expense of increased ADC distortion. In nondiversity applications, the AD964 can be used as a baseband receiver, where one ADC is used for I input data and the other is used for Q input data. Synchronizaton capability is provided to allow synchronized timing between multiple channels or multiple devices. Programming and control of the AD964 are accomplished using a 3-bit SPI-compatible serial interface. ADC ARCHITECTURE The AD964 architecture consists of a dual front-end sampleand-hold amplifier (SHA), followed by a pipelined, switched capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, and the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage of each channel contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, carries out error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. ANALOG INPUT CONSIDERATIONS The analog input to the AD964 is a differential switched capacitor SHA that has been designed for optimum performance while processing a differential input signal. The clock signal alternatively switches the SHA between sample mode and hold mode (see Figure 45). When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within ½ of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. In intermediate frequency (IF) undersampling applications, any shunt capacitors should be reduced. In combination with the driving source impedance, they limit the input bandwidth. See the AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, Transformer-Coupled Front-End for Wideband A/D Converters for more information on this subject. VIN+ C PIN, PAR VIN C PIN, PAR S S H C S C S S C H C H Figure 45. Switched-Capacitor SHA Input For best dynamic performance, the source impedances driving VIN+ and VIN should be matched. An internal differential reference buffer creates positive and negative reference voltages that define the input span of the ADC core. The span of the ADC core is set by the buffer to 2 VREF. Input Common Mode The analog inputs of the AD964 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM =.55 AVDD is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 44). An on-board common-mode voltage reference is included in the design and is available from the CML pin. Optimum performance is achieved when the common-mode voltage of the analog input is set by the CML pin voltage (typically.55 AVDD). The CML pin must be decoupled to ground by a.1 μf capacitor, as described in the Applications Information section. Differential Input Configurations Optimum performance is achieved while driving the AD964 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. S Rev. B Page 25 of 52

26 AD964 The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD964 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 1V p-p 49.9Ω.1µF 499Ω 523Ω 499Ω AD Ω R R C VIN+ AD964 VIN AVDD CML Figure 46. Differential Input Configuration Using the AD8138 For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 47. To bias the analog input, the CML voltage can be connected to the center tap of the transformer s secondary winding. 2V p-p 49.9Ω.1µF R R C VIN+ AD964 VIN CML Figure 47. Differential Transformer-Coupled Configuration The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion. At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD964. For applications where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 49 for an example) An alternative to using a transformer coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver. An example is shown in Figure 5. See the AD8352 data sheet for more information. In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 13 displays recommended values to set the RC network. However, these values are dependent on the input signal and should be used only as a starting guide. Table 13. Example RC Network R Series Frequency Range (MHz) (Ω Each) C Differential (pf) to to to >3 15 Open Single-Ended Input Configuration A single-ended input can provide adequate performance in cost sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 48 details a typical single-ended input configuration. 1V p-p 1µF 49.9Ω.1µF 1µF.1µF 1kΩ 1kΩ AVDD AVDD 1kΩ 1kΩ R R C VIN+ VIN Figure 48. Single-Ended Input Configuration AD V p-p.1µf.1µf 25Ω R VIN+ P A S S P.1µF 25Ω.1µF C R AD964 VIN CML Figure 49. Differential Double Balun Input Configuration V CC.1µF.1µF Ω 16 8, 13 ANALOG INPUT.1µF 1 11 R 2 2Ω C D R D R G AD8352 C 3.1µF 2Ω 4 1 R 5 ANALOG INPUT 14 Ω.1µF.1µF.1µF Figure 5. Differential Input Configuration Using the AD8352 VIN+ AD964 VIN CML Rev. B Page 26 of 52