10-Bit, 65/80/105 MSPS Dual A/D Converter AD9216

Transcription

1 -Bit, // MSPS Dual A/D Converter AD9 FEATURES Integrated dual -bit ADC Single V supply operation SNR = 7. c (to Nyquist, AD9-) SFDR = 7 c (to Nyquist, AD9-) Low power: mw/ch at MSPS Differential input with MHz bandwidth Exceptional crosstalk immunity < - Offset binary or twos complement data format Clock duty cycle stabilizer APPLICATIONS Ultrasound equipment IF sampling in communications receivers G, radio point-to-point, LMDS, MMDS Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes GENERAL DESCRIPTION The AD9 is a dual, V, -bit, MSPS analog-to-digital converter (ADC). It features dual high performance sampleand-hold amplifiers (SHAs) and an integrated voltage reference. The AD9 uses a multistage differential pipelined architecture with output error correction logic to provide -bit accuracy and guarantee no missing codes over the full operating temperature range at up to MSPS data rates. The wide bandwidth, differential SHA allows for a variety of user selectable input ranges and offsets, including single-ended applications. The AD9 is suitable for various applications, including multiplexed systems that switch full-scale voltage levels in successive channels and for sampling inputs at frequencies well beyond the Nyquist rate. Dual single-ended clock inputs are used to control all internal conversion cycles. A duty cycle stabilizer is available on the AD9 and can compensate for wide variations in the clock duty cycle, allowing the converters to maintain excellent performance. The digital output data is presented in either straight binary or twos complement format. VIN+_A VIN _A REFT_A REFB_A VREF SENSE AGND REFT_B REFB_B VIN+_B VIN _B FUNCTIONAL BLOCK DIAGRAM SHA.V SHA AD9 AD ADC ADC AGND DRD DRGND Figure. OUTPUT MUX/ BUFFERS CLOCK DUTY CYCLE STABILIZER MODE CONTROL OUTPUT MUX/ BUFFERS D9_A D_A OEB_A MUX_SELECT CLK_A CLK_B DCS SHARED_REF PWDN_A PWDN_B DFS D9_B D_B OEB_B Fabricated on an advanced CMOS process, the AD9 is available in a space saving, Pb-free, -lead LFCSP (9 mm 9 mm) and is specified over the industrial temperature range ( C to +8 C). PRODUCT HIGHLIGHTS. Pin compatible with AD98, dual -bit MSPS/ MSPS/ MSPS ADC and AD98, dual -bit MSPS/ MSPS/ MSPS ADC.. MSPS capability allows for demanding, high frequency applications.. Low power consumption: AD9 : MSPS = mw.. The patented SHA input maintains excellent performance for input frequencies up to MHz and can be configured for single-ended or differential operation.. Typical channel crosstalk of < at fin up to 7 MHz The clock duty cycle stabilizer maintains performance over a wide range of clock duty cycles. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Fax: 78.. Analog Devices, Inc. All rights reserved.

2 * PRODUCT PAGE QUICK LINKS Last Content Update: 9/7/7 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS AD9 Evaluation Board DOCUMENTATION Application Notes AN-: Techniques for High Speed ADC PCB Layout AN-8: Fundamentals of Sampled Data Systems AN-: Grounding for Low-and-High-Frequency Circuits AN-: Aperture Uncertainty and ADC System Performance AN-7: A First Approach to IBIS Models: What They Are and How They Are Generated AN-77: How ADIsimADC Models an ADC AN-7: Little Known Characteristics of Phase Noise AN-7: Sampled Systems and the Effects of Clock Phase Noise and Jitter AN-: Pin Compatible High Speed ADCs Simplify Design Tasks AN-87: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs AN-8: Understanding High Speed ADC Testing and Evaluation AN-9: Visual Analog Converter Evaluation Tool Version. User Manual AN-9: Designing an ADC Transformer-Coupled Front End Data Sheet AD9: -Bit, MSPS Dual A/D Converter Data Sheet TOOLS AND SIMULATIONS Visual Analog AD9 IBIS Models REFERENCE MATERIALS Technical Articles Matching An ADC To A Transformer MS-: Designing Power Supplies for High Speed ADC DESIGN RESOURCES AD9 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all AD9 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

3 TABLE OF CONTENTS DC Specifications... AC Specifications... Logic Specifications... Switching Specifications... Timing Diagram... 7 Absolute Maximum Ratings... 8 Explanation of Test Levels... 8 ESD Caution... 8 Pin Configuration and Function Descriptions... 9 Terminology... Typical Performance Characteristics... Equivalent Circuits... 9 Theory of Operation... Analog Input... Clock Input and Considerations... Power Dissipation and Standby Mode... Digital Outputs... Output Coding... Timing... Data Format... Voltage Reference... Dual ADC LFCSP PCB... Power Connector... Analog Inputs... Optional Operational Amplifier... Clock... Voltage Reference... Data Outputs... LFCSP Evaluation Board Bill of Materials (BOM)... 7 LFCSP PCB Schematics... 8 LFCSP PCB Layers... Thermal Considerations... 7 Outline Dimensions... 8 Ordering Guide... 8 REVISION HISTORY / Rev. to Rev. A Added and Speed Grades...Universal Changes to Table... Changes to Table... Changes to Table... Changes to Table... Changes to Table Added Figure 8... Added Figure, Figure, and Figure... Changes to Figure... 8 Changes to Table... 7 Changes to Figure... 8 Changes to Figure... 9 Changes to Figure... Changes to Figure... Changes to Figure... Changes to Figure... Changes to Figure 7... Changes to Figure 8... Changes to Figure 9... Changes to Ordering Guide... 8 / Revision : Initial Version Rev. A Page of

4 SPECIFICATIONS DC SPECIFICATIONS AD9 AD =. V, DRD =. V, maximum sample rate, CLK_A = CLK_B; AIN =. FS differential input,. V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table. Temp Test AD9BCPZ- AD9BCPZ- AD9BCPZ- Parameter Level Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full VI Bits ACCURACY No Missing Codes Full VI Guaranteed Guaranteed Guaranteed Offset Error Full VI -.9 ± ± ±. +. % FSR Gain Error C VI -. ± ±. +.. ±. +. % FSR Differential Nonlinearity (DNL) Full IV -. ± ±. +.. ±. +. LSB C I -.9 ± ± ±. +. LSB Integral Nonlinearity (INL) Full IV -. ± ±. +.. ±. +. LSB C I -. ± ±. +.. ±. +. LSB TEMPERATURE DRIFT Offset Error Full V ± ± ± µv/ C Gain Error Full V ±7 ±7 ±7 ppm/ C Reference Voltage Full V ± ± ± ppm/ C INTERNAL VOLTAGE REFERENCE Output Voltage Error Full VI ± ± ± ± ± ± mv Load ma C V... mv INPUT REFERRED NOISE Input Span =. V C V... LSB rms ANALOG INPUT Input Span, VREF =. V Full IV V p-p Input Capacitance C V pf REFERENCE INPUT RESISTANCE C V kω POWER SUPPLIES Supply Voltages AD Full IV V DRD Full IV V Supply Current IAD Full VI ma IDRD Full VI 8 ma PSRR C V ±. ±. ±. % FSR POWER CONSUMPTION PAD C I mw PDRD C V 8 mw Standby Power C V... mw MATCHING CHARACTERISTICS Offset Matching Error C I -. ± ±. +.. ±. +. % FSR Gain Matching Error (Shared Reference C I -. ± ±. +.. ±. +. % FSR Mode) Gain Matching Error (Nonshared Reference Mode) C I -. ± ±. +.. ±. +. % FSR Gain error and gain temperature coefficient are based on the ADC only (with a fixed. V external reference). Measured with low frequency ramp at maximum clock rate. Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 7 for the equivalent analog input structure. Measured with low frequency analog input at maximum clock rate with approximately pf loading on each output bit. Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AD or AGND). Both shared reference mode and nonshared reference mode. Rev. A Page of

5 AC SPECIFICATIONS AD =. V, DRD =. V, maximum sample rate, CLK_A = CLK_B; AIN =. FS differential input,. V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table. Parameter Temp Test Level SIGNAL-TO-NOISE RATIO (SNR) AD9BCPZ- AD9BCPZ- AD9BCPZ- Min Typ Max Min Typ Max Min Typ Max Unit finput =. MHz C V finput = Nyquist Full IV C I finput = 9 MHz C V finput = MHz C V SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) finput =. MHz C V finput = Nyquist Full IV C I finput = 9 MHz C V finput = MHz C V EFFECTIVE NUMBER OF BITS (ENOB) finput =. MHz C V Bits finput = Nyquist Full IV Bits C I Bits finput = 9 MHz C V Bits finput = MHz C V Bits WORST HARMONIC (SECOND OR THIRD) finput =. MHz Full IV c finput = Nyquist Full IV c C I c finput = 9 MHz C V c finput = MHz C V c WORST OTHER (EXCLUDING SECOND OR THIRD) finput =. MHz Full IV c finput = Nyquist Full IV c C I c finput = 9 MHz C V c finput = MHz C V c SPURIOUS-FREE DYNAMIC RANGE (SFDR) finput =. MHz Full IV c finput = Nyquist Full IV c C I c finput = 9 MHz C V c finput = MHz C V c TWO-TONE SFDR (AIN = 7 FS) fin = 9. MHz, fin = 7. MHz C V c fin =. MHz, fin =. MHz C V c ANALOG BANDWIDTH C V MHz CROSSTALK C V... Nyquist = approximately MHz, MHz, MHz for the,, and grades respectively Rev. A Page of

6 LOGIC SPECIFICATIONS AD =. V, DRD =. V, maximum sample rate, CLK_A = CLK_B; AIN =. FS differential input,. V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table. AD9BCPZ- AD9BCPZ- AD9BCPZ- Parameter Temp Test Min Typ Max Min Typ Max Min Typ Max Unit Level LOGIC INPUTS High Level Input Full IV... V Voltage Low Level Input Full IV V Voltage High Level Input Full IV µa Current Low Level Input Full IV µa Current Input Capacitance Full IV pf LOGIC OUTPUTS DRD =. V High Level Output Full IV... V Voltage Low Level Output Voltage Full IV... V Output voltage levels measured with pf load on each output. Rev. A Page of

7 SWITCHING SPECIFICATIONS AD =. V, DRD =. V, maximum sample rate, CLK_A = CLK_B; AIN =. FS differential input,. V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table. AD9BCPZ- AD9BCPZ- AD9BCPZ- Parameter Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit SWITCHING PERFORMANCE Maximum Conversion Rate Full VI MSPS Minimum Conversion Rate Full IV MSPS CLK Period Full VI.. 9. ns CLK Pulse Width High Full VI...8 ns CLK Pulse Width Low Full VI...8 ns OUTPUT PARAMETERS Output Propagation Delay (tpd) C I ns Valid Time (tv) C I... Output Rise Time (% to 9%) C V... ns Output Fall Time (% to 9%) C V... ns Output Enable Time Full IV Cycle Output Disable Time Full IV Cycle Pipeline Delay (Latency) Full IV Cycle APERTURE Aperture Delay (ta) C V... ns Aperture Uncertainty (tj) C V... ps rms Wake-Up Time C V ms OUT-OF-RANGE RECOVERY TIME C V Cycle CLOAD equals pf maximum for all output switching parameters. Output delay is measured from clock % transition to data % transition. Valid time is approximately equal to the minimum output propagation delay. Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective channel outputs going into high impedance. Wake-up time is dependent on value of decoupling capacitors; typical values shown for. µf and µf capacitors on REFT and REFB. Rev. A Page of

8 TIMING DIAGRAM N N+ N+ N+8 N t A N+ ANALOG INPUT N+ N+ N+ N+7 CLK DATA OUT N 8 N 7 N N N N N N N N+ t PD 77- Figure. Rev. A Page 7 of

9 ABSOLUTE MAXIMUM RATINGS Table. Parameter To Rating ELECTRICAL AD AGND. V to +.9 V DRD DRGND. V to +.9 V AGND DRGND. V to +. V AD DRD. V to +.9 V Digital Outputs DRGND. V to DRD + CLK_A, CLK_B, DCS, DFS, MUX_SELECT, OEB_A, OEB_B, SHARED_REF, PDWN_A, PDWN_B AGND. V. V to AD +. V VIN _A, VIN+_A, VIN _B, VIN+_B AGND. V to AD +. V REFT_A, REFB_A,VREF, REFT_B, REFB_B, SENSE AGND. V to AD +. V ENVIRONMENTAL Operating Temperature C to +8 C Junction Temperature C Lead Temperature ( sec) C Storage Temperature C to + C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EXPLANATION OF TEST LEVELS Table. Test Level Description I % production tested. II % production tested at C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI % production tested at C; guaranteed by design and characterization testing for industrial temperature range; % production tested at temperature extremes for military devices. Typical thermal impedances (-lead LFCSP); θja =. C/W. These measurements were taken on a -layer board (with thermal via array) in still air, in accordance with EIA/JESD-7. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A Page 8 of

10 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN INDICATOR AD CLK_A SHARED_REF MUX_SELECT PDWN_A OEB_A DNC D9_A (MSB) D8_A D7_A D_A DRGND DRD D_A D_A D_A AGND VIN+_A VIN _A AGND AD REFT_A REFB_A 7 VREF 8 SENSE 9 REFB_B REFT_B AD AGND VIN _B VIN+_B AGND AD9 TOP VIEW (Not to Scale) 8 D_A 7 D_A D_A (LSB) DNC DNC DNC DNC DRD DRGND 9 DNC 8 D9_B (MSB) 7 D8_B D7_B D_B D_B D_B DNC = DO NOT CONNECT AD CLK_B DCS DFS PDWN_B OEB_B DNC DNC DNC DNC D_B (LSB) DRGND DRD D_B D_B D_B 77- Figure. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description,,, AGND Analog Ground. VIN+_A Analog Input Pin (+) for Channel A. VIN _A Analog Input Pin ( ) for Channel A.,, 7, AD Analog Power Supply. REFT_A Differential Reference (+) for Channel A. 7 REFB_A Differential Reference ( ) for Channel A. 8 VREF Voltage Reference Input/Output. 9 SENSE Reference Mode Selection. REFB_B Differential Reference ( ) for Channel B. REFT_B Differential Reference (+) for Channel B. VIN _B Analog Input Pin ( ) for Channel B. VIN+_B Analog Input Pin (+) for Channel B. 8 CLK_B Clock Input Pin for Channel B. 9 DCS Duty Cycle Stabilizer (DCS) Mode Pin (Active High). DFS Data Output Format Select Pin. Low for offset binary; high for twos complement. PDWN_B Power-Down Function Selection for Channel B. Logic enables Channel B. Logic powers down Channel B. (Outputs static, not High-Z.) OEB_B Output Enable for Channel B. Logic enables Data Bus B. Logic sets outputs to High-Z. to, 9, DNC Do Not Connect Pins. Should be left floating. to, 8 7, to 8 D_B (LSB) to Channel B Data Output Bits. D9_B (MSB) 8,, DRGND Digital Output Ground. 9,, DRD Digital Output Driver Supply. Must be decoupled to DRGND with a minimum. µf capacitor. Recommended decoupling is. µf capacitor in parallel with µf. Rev. A Page 9 of

11 Pin No. Mnemonic Description to, D_A (LSB) to Channel A Data Output Bits. to 7 D9_A (MSB) 9 OEB_A Output Enable for Channel A. Logic enables Data Bus A. Logic sets outputs to High-Z. PDWN_A Power-Down Function Selection for Channel A. Logic enables Channel A. Logic powers down Channel A. (Outputs static, not High-Z.) MUX_SELECT Data Multiplexed Mode. (See Data Format section for how to enable.) SHARED_REF Shared Reference Control Bit. Low for independent reference mode; high for shared reference mode. CLK_A Clock Input Pin for Channel A. It is recommended that all ground pins (AGND and DRGND) be tied to a common ground plane. Rev. A Page of

12 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by. Aperture Delay The delay between the % point of the rising edge of the encode command and the instant the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle Pulse-width high is the minimum amount of time that the clock pulse should be left in a Logic state to achieve rated performance; pulse-width low is the minimum time clock pulse should be left in a low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Crosstalk Coupling onto one channel being driven by a low level ( FS) signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is out of phase. Peak-to-peak differential is computed by rotating the inputs phase and by taking the peak measurement again. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal LSB step. Effective Number of Bits (ENOB) The ENOB is calculated from the measured SINAD based on the equation (assuming full-scale input) ENOB = SINAD MEASURED..7 Full-Scale Input Power Expressed in m and computed using the following equation. Power FULL SCALE V = log FULL SCALE Z INPUT. rms Gain Error The difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in c. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in c. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of LSB using a best straight line determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a % crossing of the CLK rising edge and the time when all output data bits are within valid logic levels. Rev. A Page of

13 Noise (for Any Range within the ADC) This value includes both thermal and quantization noise. where: V noise = FS Z. Z is the input impedance. m SNRc Signal FS FS is the full scale of the device for the frequency in question. SNR is the value for the particular input level. Signal is the signal level within the ADC reported in below full scale. Power Supply Rejection Ratio The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, in c. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It also may be reported in c (that is, degrades as signal level is lowered) or in FS (that is, always relates back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic), reported in c. Transient Response Time The time it takes for the ADC to reacquire the analog input after a transient from % above negative full scale to % below positive full scale. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transient from % above positive full scale to % above negative full scale, or from % below negative full scale to % below positive full scale. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at below full scale) to the rms value of the sum of all other spectral components, excluding the first seven harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in c (that is, degrades as signal level is lowered) or FS (that is, always related back to converter full scale). Rev. A Page of

14 TYPICAL PERFORMANCE CHARACTERISTICS AD =. V, DRD =. V, T = C, AIN differential drive, internal reference, DCS on, unless otherwise noted. AMPLITUDE (FS) SNR = 7.8 SINAD = 7.8 H = 9.7c H =.c SFDR = 78.c AMPLITUDE (FS) 7 7MHz ON CHANNEL A ACTIVE 7MHz CROSSTALK FROM CHANNEL B FREQUENCY (MHz) (7) (7) FREQUENCY (MHz) 77- Figure. FFT: fs = MSPS, AIN =. MHz at. FS ( Grade) Figure 7. FFT: fs = MSPS, AIN =7 MHz, 7 MHz ( Grade) (A Port FFT while Both A and B Ports Are Driven at. FS) SNR =.9 SINAD =.8 H = 78.c H = c SFDR = 78.c 7MHz ON CHANNEL A ACTIVE SNR = 7. SINAD = 7. H = 8.c H = 77.c SFDR = 7c AMPLITUDE (FS) AMPLITUDE (FS) 7MHz CROSSTALK FROM CHANNEL B FREQUENCY (MHz) 77-9 FREQUENCY (MHz) 77-8 Figure. FFT: fs = MSPS, AIN = 7 MHz at. FS ( Grade) Figure 8. FFT: fs = MSPS, AIN =7 MHz, 7 MHz ( Grade) (A Port FFT while Both A and B Ports Are Driven at. FS) AMPLITUDE (FS) SNR =.8 SINAD =.7 H = 7c H = 8.c SFDR = 7c AMPLITUDE (FS) 7MHz ON CHANNEL A ACTIVE 7MHz CROSSTALK FROM CHANNEL B SNR = 7. SINAD = 7. H = 8.9c H = 7.c SFDR = 7.c FREQUENCY (MHz) Figure. FFT: fs = MSPS, AIN = MHz at. FS ( Grade) 77- FREQUENCY (MHz) Figure 9. FFT: fs = MSPS, AIN =7 MHz, 7 MHz ( Grade) (A Port FFT while Both A and B Ports Are Driven at. FS) 77-9 Rev. A Page of

15 H 9 H H 9 H 7 SNR SFDR 7 SFDR SNR SINAD CLOCK FREQUENCY (MHz) 77- SINAD ANALOG INPUT FREQUENCY (MHz) 77- Figure. SNR, SINAD, H, H, SFDR vs. Sample Clock Frequency AIN = 7 MHz at. FS ( Grade) Figure. Analog Input Frequency Sweep, AIN =. FS, fs = MSPS ( Grade) 9 H H 9 H H 7 7 SFDR SNR SFDR SNR SINAD 7 9 CLOCK FREQUENCY (MHz) Figure. SNR, SINAD, H, H, SFDR vs. Sample Clock Frequency, AIN = 7 MHz at. FS ( / Grade) 77- SINAD ANALOG INPUT FREQUENCY (MHz) Figure. Analog Input Frequency Sweep, AIN =. FS, fs = MSPS ( Grade) H 7 SFDR FS 7 H SFDR c REF. LINE SFDR SNR SINAD 77- SNR 77- ANALOG INPUT FREQUENCY (MHz) INPUT LEVEL (FS) Figure. Analog Input Frequency Sweep, AIN =. FS, fs = MSPS ( Grade) Figure. SFDR vs. Analog Input Level, AIN = 7 MHz, fs = MSPS ( Grade) Rev. A Page of

16 9 9 7 SFDR c REF. LINE SFDR FS 7 TWO-TONE SFDR FS TWO-TONE SFDR c 7 REF LINE SNR INPUT LEVEL (FS) Figure. SFDR vs. Analog Input Level, AIN = 7 MHz, fs = MSPS ( Grade) 77- TWO-TONE ANALOG INPUT LEVEL (FS) Figure 9. Two-Tone IMD Performance vs. Input Drive Level (9. MHz and 7. MHz; fs = MSPS ( Grade); F, F Levels Equal) SFDR FS SFDR c 9 7 SFDR FS SFDR c 7 REF. LINE SNR REF. LINE INPUT LEVEL (FS) Figure 7. SFDR vs. Analog Input Level, AIN = 7 MHz, fs = MSPS ( Grade ) 77-7 TWO-TONE ANALOG INPUT LEVEL (FS) Figure. Two-Tone IMD Performance vs. Input Drive Level (9. MHz and 7. MHz; fs = MSPS ( Grade); F, F Levels Equal) 77-9 AMPLITUDE (FS) 7 IMD = 9.9c 7 SFDR FS SFDR c 7 REF. LINE 9 INPUT FREQUENCY (MHz) Figure 8. Two-Tone IMD Performance F, F = 9. MHz, 7. MHz at 7 FS, MSPS ( Grade) 77-7 TWO-TONE ANALOG INPUT LEVEL (FS) Figure. Two-Tone IMD Performance vs. Input Drive Level (9. MHz and 7. MHz; fs = MSPS ( Grade); F, F Levels Equal) 77- Rev. A Page of

17 9 7 TWO-TONE SFDR FS TWO-TONE SFDR c 7 7 SFDR SNR 7 REF LINE TWO-TONE ANALOG INPUT LEVEL (FS) VREF (V) Figure. Two-Tone IMD Performance vs. Input Drive Level (. MHz and. MHz; fs = MSPS ( Grade); F, F Levels Equal) Figure. SNR, SFDR vs. External VREF (Full Scale = VREF) AIN = 7. MHz at. FS, MSPS ( Grade) 9 AD CURRENT ( GRADE) CURRENT (ma) AD CURRENT ( / GRADE) DRD CURRENT (ALL GRADES) GAIN ERROR (% Full Scale).. EXTERNAL REFERENCE MODE... INTERNAL REFERENCE MODE SAMPLE CLOCK RATE (MSPS) TEMPERATURE ( C) Figure. IAD, IDRD vs. Sample Clock Frequency, CLOAD = pf, AIN = 7 FS Figure. Typical Gain Error Variation vs. Temperature, ( Grade) AIN = 7 MHz at. FS, MSPS (Normalized to C) 7 SNR DCS ON SFDR DCS ON SFDR DCS OFF 7 7 SFDR SNR DCS OFF 7 7 POSITIVE DUTY CYCLE (%) Figure. SNR, SFDR vs. Positive Duty Cycle DCS Enabled, Disabled; AIN = 7 MHz at. FS, MSPS ( Grade) 77-9 SNR SINAD TEMPERATURE ( C) Figure 7. SNR, SINAD, SFDR vs. Temperature, ( Grade) AIN = 7 MHz at. FS, MSPS, Internal Reference Mode 77- Rev. A Page of

18 7 SFDR 7 7 SFDR 7 SNR SINAD TEMPERATURE ( C) SNR SINAD AD (V) 77-9 Figure 8. SNR, SINAD, SFDR vs. Temperature, ( Grade) AIN = 7 MHz at. FS, MSPS, External Reference Mode Figure. SNR, SINAD, SFDR vs. AD, AIN = 7 MHz at. FS, MSPS ( Grade) 7 SFDR 7 SFDR 7 7 SNR SNR SINAD SINAD TEMPERATURE ( C) AD (V) Figure 9. SNR, SINAD, SFDR vs. Temperature, (- Grade) AIN = 7 MHz at. FS, MSPS, Internal Reference Mode Figure. SNR, SINAD, SFDR vs. AD, AIN = 7 MHz at. FS, MSPS ( Grade) 8 8 SFDR SFDR TEMPERATURE ( C) SINAD SNR Figure. SNR, SINAD, SFDR vs. Temperature, (- Grade) AIN = 7 MHz at. FS, MSPS,, Internal Reference Mode SINAD SNR AD (V) Figure. SNR, SINAD, SFDR vs. AD, AIN = 7 MHz at. FS, MSPS ( Grade) 77- Rev. A Page 7 of

19 LSB.... CODE Figure. Typical DNL Plot, AIN =. MHz at. FS, MSPS ( Grade) 77- T PD (ns).... TEMPERATURE ( C) Figure. Typical Propagation Delay vs. Temperature ( All Speed Grades) LSB.... CODE Figure. Typical INL Plot, AIN =. MHz at. FS, MSPS ( Grade) 77- Rev. A Page 8 of

20 EQUIVALENT CIRCUITS AD AD VIN+_A, VIN _A, VIN+_B, VIN _B PDWN kω Figure 7. Equivalent Analog Input Figure 9. Power-Down Input AD DRD CLK_A, CLK_B DCS, DFS, MUX_SELECT, SHARED_REF Figure 8. Equivalent Clock, Digital Inputs Circuit 77- Figure. Digital Outputs 77-7 Rev. A Page 9 of

21 THEORY OF OPERATION The AD9 consists of two high performance ADCs that are based on the AD9 converter core. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each of the ADC paths consists of a proprietary front end SHA followed by a pipelined, switched-capacitor ADC. The pipelined ADC is divided into three sections, consisting of a sample-and-hold amplifier, followed by seven.-bit stages, and a final -bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined through the digital correction logic block into a final -bit result. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the respective clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC and a residual multiplier to drive the next stage of the pipeline. The residual multiplier uses the flash ADC output to control a switched capacitor digital-to-analog converter (DAC) of the same resolution. The DAC output is subtracted from the stage s input signal and the residual is amplified (multiplied) to drive the next pipeline stage. The residual multiplier stage is also called a multiplying DAC (MDAC). One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be configured as ac- or dc-coupled in differential or single-ended modes. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. ANALOG INPUT The analog input to the AD9 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input accepts inputs over a wide common-mode range. An input common-mode voltage of midsupply is recommended to maintain optimal performance. The SHA input is a differential switched-capacitor circuit. In Figure, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC s input; therefore, the precise values are dependant on the application. In IF under-sampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they would limit the input bandwidth. For best dynamic performance, the source impedances driving VIN+ and VIN should be matched, so the common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. VIN+ VIN C PAR C PAR T T.pF.pF Figure. Switched-Capacitor Input An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common-mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as: REFT = / (AD + VREF) REFB = / (AD VREF) Span = (REFT REFB) = VREF It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as VCMMIN = VREF/ VCMMAX = (AD + VREF)/ The minimum common-mode input level allows the AD9 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a single-ended source may be driven into VIN+ or VIN. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. T T H H 77-8 Rev. A Page of

22 For example, a V p-p signal may be applied to VIN+, while a V reference is applied to VIN. The AD9 then accepts an input signal varying between V and V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies. 8 For dc-coupled applications, the AD88, AD89, or AD8 can serve as a convenient ADC driver, depending on requirements. Figure shows an example with the AD88. The AD9 PCB has an optional AD89 on board, as shown in Figure. Note the AD8 typically yields better performance for frequencies greater than MHz to MHz. 7 V p-p SFDR 9.9Ω 99Ω 99Ω Ω AD VIN+ 7 V p-p SNR AD88 pf AD9 Ω Ω VIN AGND 99Ω Figure. Driving the ADC with the AD ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure. Input Common-Mode Voltage Sensitivity Differential Input Configurations As previously detailed, optimum performance is achieved while driving the AD9 in a differential input configuration. For baseband applications, the AD88 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD88 is easily set to AD/, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9. This is especially true in IF under-sampling applications where frequencies in the 7 MHz to MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure. V p-p 9.9Ω Ω pf Ω pf VIN_A AD9 VIN_B AD AGND 77-9 FULL SCALE/ SENSE = GROUND VIN+ AD/ VIN DIGITAL OUT = ALL ONES DIGITAL OUT = ALL ZEROES Figure. Analog Input Full Scale (Full Scale = V) Single-Ended Input Configuration AD/ A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance Figure. Differential Transformer Coupling The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion. Rev. A Page of

23 CLOCK INPUT AND CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a % tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9 provides separate clock inputs for each channel. The optimum performance is achieved with the clocks operated at the same frequency and phase. Clocking the channels asynchronously may degrade performance significantly. In some applications, it is desirable to skew the clock timing of adjacent channels. The AD9 s separate clock inputs allow for clock timing skew (typically ± ns) between the channels without significant performance degradation. The AD9 contains two clock duty cycle stabilizers, one for each converter, that retime the nonsampling edge, providing an internal clock with a nominal % duty cycle. Faster input clock rates, where it becomes difficult to maintain % duty cycles, can benefit from using DCS, as a wide range of input clock duty cycles can be accommodated. Maintaining a % duty cycle clock is particularly important in high speed applications, when proper track-and-hold times for the converter are required to maintain high performance. The DCS can be enabled by tying the DCS pin high. The duty cycle stabilizer uses a delay-locked loop to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately µs to µs to allow the DLL to acquire and settle to the new rate. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (finput) due only to aperture jitter (tj) can be calculated by SNR degradation = log [/ p finput tj] In the equation, the rms aperture jitter, tj, represents the rootsum square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. For optimal performance, especially in cases where aperture jitter may affect the dynamic range of the AD9, it is important to minimize input clock jitter. The clock input circuitry should use stable references; for example, use analog power and ground planes to generate the valid high and low digital levels for the AD9 clock input. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. POWER DISSIPATION AND STANDBY MODE The power dissipated by the AD9 is proportional to its sampling rates. The digital (DRD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The digital drive current can be calculated by IDRD = RD CLOAD fclock N where N is the number of bits changing, and CLOAD is the average load on the digital pins that changed. The analog circuitry is optimally biased, so each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases with clock frequency. Either channel of the AD9 can be placed into standby mode independently by asserting the PWDN_A or PDWN_B pins. Time to go into or come out of standby mode is cycles maximum when only one channel is being powered down. When both channels are powered down, VREF goes to ground, resulting in a wake-up time of ~7 ms dependent on decoupling capacitor values. It is recommended that the input clock(s) and analog input(s) remain static during either independent or total standby, which results in a typical power consumption of mw for the ADC. If the clock inputs remain active while in total standby mode, typical power dissipation of mw results. The minimum standby power is achieved when both channels are placed into full power-down mode (PDWN_A = PDWN_B = HI). Under this condition, the internal references are powered down. When either or both of the channel paths are enabled after a power-down, the wake-up time is directly related to the recharging of the REFT and REFB decoupling capacitors and to the duration of the power-down. A single channel can be powered down for moderate power savings. The powered-down channel shuts down internal circuits, but both the reference buffers and shared reference remain powered on. Because the buffer and voltage reference remain powered on, the wake-up time is reduced to several clock cycles. DIGITAL OUTPUTS The AD9 output drivers can interface directly with V logic families. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches because large drive currents tend to cause current glitches on the supplies that may affect converter performance. The data format can be selected for either offset binary or twos complement. This is discussed in the Data Format section. Rev. A Page of

24 OUTPUT CODING Table 8. Code (VIN+) (VIN ) Offset Binary Twos Complement > V V +.99 V +. V +. V. V.998 V. V <. V TIMING The AD9 provides latched data outputs with a pipeline delay of six clock cycles. Data outputs are available one propagation delay (tpd) after the rising edge of the clock signal. Refer to Figure for a detailed timing diagram. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9. These transients can detract from the converter s dynamic performance. The lowest conversion rate of the AD9 is MSPS. At clock rates below MSPS, dynamic performance may degrade. DATA FORMAT The AD9 data output format can be configured for either twos complement or offset binary. This is controlled by the data format select pin (DFS). Connecting DFS to AGND produces offset binary output data. Conversely, connecting DFS to AD formats the output data as twos complement. The output data from the dual ADCs can be multiplexed onto a single, -bit output bus. The multiplexing is accomplished by toggling the MUX_SELECT bit, which directs channel data to the same or opposite channel data port. When MUX_SELECT is logic high, the Channel A data is directed to the Channel A output bus, and the Channel B data is directed to the Channel B output bus. When MUX_SELECT is logic low, the channel data is reversed; that is, the Channel A data is directed to the Channel B output bus, and the Channel B data is directed to the Channel A output bus. By toggling the MUX_SELECT bit, multiplexed data is available on either of the output data ports. If the ADCs are run with synchronized timing, this same clock can be applied to the MUX_SELECT pin. Any skew between CLK_A, CLK_B, and MUX_SELECT can degrade ac performance. It is recommended to keep the clock skew < phs. After the MUX_SELECT rising edge, either data port has the data for its respective channel; after the falling edge, the alternate channel s data is placed on the bus. Typically, the other unused bus is disabled by setting the appropriate OEB high to reduce power consumption and noise. Figure shows an example of multiplex mode. When multiplexing data, the data rate is two times the sample rate. Note that both channels must remain active in this mode and that each channel s powerdown pin must remain low. A A A A A A A A A 7 A 8 ANALOG INPUT ADC A B B B B B B B B B 7 B 8 ANALOG INPUT ADC B CLK_A = CLK_B = MUX_SELECT B 7 A B A B A B A B A B A B A B A B D_A D_A 77- Figure. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT Rev. A Page of

25 VOLTAGE REFERENCE A stable and accurate. V voltage reference is built into the AD9. The input range can be adjusted by varying the reference voltage applied to the AD9, using either the internal reference with different external resistor configurations or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. Internal Reference Connection A comparator within the AD9 detects the potential at the SENSE pin and configures the reference into three possible states, which are summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 7), setting VREF to V. If a resistor divider is connected, as shown in Figure 8, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as VREF =. ( + R/R) Note: The optimum performance is obtained with VREF =. V; performance degrades as VREF (and full scale) reduces (see Figure ). In all reference configurations, REFT and REFB drive the ADC core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. µf VIN+ VIN VREF ADC CORE SELECT LOGIC.V SENSE REFT REFB µf AD9 77- Figure 7. Internal Reference Configuration (One Channel Shown) Table 9. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference AD N/A External Reference Programmable Reference. V to VREF. ( + R/R) VREF (see Figure 8) Internal Fixed Reference AGND to. V.. Rev. A Page of

26 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve the thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset temperature drift. Figure 9 shows the typical drift characteristics of the internal reference. VREF ERROR (%)..... VREF =.V When the SENSE pin is tied to AD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 kω load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of V. If the internal reference of the AD9 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure depicts how the internal reference voltage is affected by loading. µf µf SENSE VIN+ VIN V REF R R SELECT LOGIC ADC CORE.V AD9 REFT REFB Figure 8. Programmable Reference Configuration (one channel shown) µf 77- VREF ERROR (%). TEMPERATURE ( C)..... Figure 9. Typical VREF Drift VREF =.V I LOAD (ma) Figure. VREF Accuracy vs. Load Shared Reference Mode The shared reference mode allows the user to connect the references from the dual ADCs together externally for superior gain and offset matching performance. If the ADCs are to function independently, the reference decoupling can be treated independently and can provide superior isolation between the dual channels. To enable shared reference mode, the SHARED_REF pin must be tied high, and the external differential references must be externally shorted. (REFT_A must be externally shorted to REFT_B, and REFB_A must be shorted to REFB_B.) Rev. A Page of

27 DUAL ADC LFCSP PCB The PCB requires a low jitter clock source, analog sources, and power supplies. The PCB interfaces directly with ADI s standard dual-channel data capture board (HSC-ADC-EVAL- DC), which together with ADI s ADC Analyzer software allows for quick ADC evaluation. POWER CONNECTOR Power is supplied to the board via three detachable -lead power strips. Table. Power Connector Terminal Comments VCC. V Analog supply for ADC D. V Output supply for ADC L. V Buffer supply VCLK. V Supply for XOR Gates + V Optional op amp supply V Optional op amp supply VCC, D, and L are the minimum required power connections. ANALOG INPUTS The evaluation board accepts a V p-p analog input signal centered at ground at two SMB connectors, Input A and Input B. These signals are terminated at their respective primary side transformer. T and T are wideband RF transformers that provide the single-ended-to-differential conversion, allowing the ADC to be driven differentially, minimizing even-order harmonics. The analog signals can be low-pass filtered at the secondary transformer to reduce high frequency aliasing. OPTIONAL OPERATIONAL AMPLIFIER The PCB has been designed to accommodate an optional AD89 op amp that can serve as a convenient solution for dc-coupled applications. To use the AD89 op amp, remove C, R, R, C, R7, and R, and place R, R, R, and R. CLOCK The single-clock input is at J; the input clock is buffered and drives both channel input clocks from Pin at U8 through R79, R, and R8. Jumper E to E9 allows for inverting the input clock. U8 also provides CLKA and CLKB outputs, which are buffered by U and U, which drive the DRA and DRB signals (these are the data-ready clocks going off card). DRA and DRB can also be inverted at their respective jumpers. Table. Jumpers Terminal OEB A PWDN A MUX SHARED REF DRA LATA ENC A OEB B PWDN B DFS SHARED REF DRB LATB ENC B Comments Output Enable for A Side Power-Down A Mux Input Shared Reference Input Invert DRA Invert A Latch Clock Invert Encode A Output Enable for B Side Power-Down B Data Format Select Shared Reference Input Invert DRB Invert B Latch Clock Invert Encode B VOLTAGE REFERENCE The ADC SENSE pin is brought out to E, and the internal reference mode is selected by placing a jumper from E to ground (E7). External reference mode is selected by placing a jumper from E to E and E to E. R and R allow for programmable reference mode selection. DATA OUTPUTS The ADC outputs are buffered on the PCB at U, U. The ADC outputs have the recommended series resistors in line to limit switching transient effects on ADC performance. Rev. A Page of

28 LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM) Table. Dual CSP PCB Rev. B No. Quan. Reference Designator Device Package Value C, C Capacitors pf 7 C, C, C7, C9, C, C, C Capacitors µf C, C, C8, C to C, C, C, C to C7, C9 to Capacitors. µf, (C9, C NP ) C, C9 to C 7 C to C9, C7, C8,C7 Capacitors TAJD µf C, C8 Capacitors. µf E to E7, E9 to E, E to E7, E9 to E, E to Jumpers E8, E to E, E9, E 7 J to J SMA 8 P, P, P Power Connector Posts Z... Wieland 9 P, P, P Detachable Connectors... Wieland P, P8 (implemented as one pin connector) Connector TSW--8- Samtec L-D-RA R, R, R, R Resistors Ω (All NP ) R, R7, R, R, R, R Resistors Ω, (R, R NP ) R, R8, R, R Resistors Ω, (All NP ) R, R, R, R7 Resistors Ω R9, R, R, R, R, R, R, R, R8, R8 Resistors Zero Ω (R9, R, R, R, R, R8 NP ) R, R, R8, R, R9, R Resistors 99 Ω (R, R9 NP ) 7 R7, R Resistors Ω 8 R9, R, R7, R8, R9, R, R, R to R9, R, R, R, R7 to R, R to R7, R7, R77, R78, R8 to R8 Resistors kω (R, R78, R8, R8, R8 NP ) 9 R to R, R Resistors Ω (R, R, R, R NP ) R, R Resistors kω (R, R NP ) 7 R, R, R8, R7, R7, R79, R Resistor Ω 8 RZ, RZ, RZ, RZ, RZ, RZ, RZ9, RZ Resistor Pack CTS 7C7J 7 Ω T, T Transformers T-WT Minicircuits U AD9/AD98/AD98 LFCSP- U, U Transparent Latch/Buffer TSSOP-8 SN7LVCH7ADGGR 7 U, U7 Inverter SC-7 SN7LVCGDCKT (U, U7 NP ) 8 U, U, U8 XOR SO- SN7VCX8 9 U, U Amp SO-8/EP AD89 P, P to P7, P9, P, P to P8, P Solder Bridge Not Populated. Rev. A Page 7 of