12-Bit, 20/40/65 MSPS 3 V A/D Converter AD9235

Transcription

1 Data Sheet -Bit, 0/40/65 MSPS V A/D Converter FEATURES Single V supply operation (.7 V to.6 V) SNR = 70 dbc to Nyquist at 65 MSPS SFDR = 85 dbc to Nyquist at 65 MSPS Low power: 00 mw at 65 MSPS Differential input with 500 MHz bandwidth On-chip reference and SHA DNL = ±0.4 LSB Flexible analog input: V p-p to V p-p range Offset binary or twos complement data format Clock duty cycle stabilizer VIN+ VIN REFT REFB SHA FUNCTIONAL BLOCK DIAGRAM DRVDD 8-STAGE MDAC /-BIT PIPELINE 4 6 A/D CORRECTION LOGIC OUTPUT BUFFERS A/D OTR D APPLICATIONS Ultrasound equipment IF sampling in communications receivers IS-95, CDMA-One, IMT-000 Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes VREF SENSE REF SELECT A CLOCK DUTY CYCLE STABILIZER 0.5V MODE SELECT CLK PDWN MODE Figure. D D GENERAL DESCRIPTION The is a family of monolithic, single V supply, -bit, 0/40/65 MSPS analog-to-digital converters (ADCs). This family features a high performance sample-and-hold amplifier (SHA) and voltage reference. The uses a multistage differential pipelined architecture with output error correction logic to provide -bit accuracy at 0/40/65 MSPS data rates and guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the is suitable for applications in communications, imaging, and medical ultrasound. A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the is available in a 8-lead TSSOP and a -lead LFCSP and is specified over the industrial temperature range ( 40 C to +85 C). PRODUCT HIGHLIGHTS. The operates from a single V power supply and features a separate digital output driver supply to accommodate.5 V and. V logic families.. Operating at 65 MSPS, the consumes a low 00 mw.. The patented SHA input maintains excellent performance for input frequencies up to 00 MHz and can be configured for single-ended or differential operation. 4. The pinout is similar to the AD94-65, a 0-bit, 65 MSPS ADC. This allows a simplified upgrade path from 0 bits to bits for 65 MSPS systems. 5. The clock DCS maintains overall ADC performance over a wide range of clock pulse widths. 6. The OTR output bit indicates when the signal is beyond the selected input range. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 906, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Specifications... DC Specifications... Digital Specifications... 4 Switching Specifications... 4 AC Specifications... 5 Absolute Maximum Ratings... 7 Explanation of Test Levels... 7 ESD Caution... 7 Pin Configurations and Function Descriptions... 8 Definitions of Specifications... 9 Equivalent Circuits... 0 Typical Performance Characteristics... Data Sheet Applying the... 5 Theory of Operation... 5 Analog Input... 5 Clock Input Considerations... 6 Power Dissipation and Standby Mode... 7 Digital Outputs... 8 Voltage Reference... 8 Operational Mode Selection... 9 TSSOP Evaluation Board... 9 LFCSP Evaluation Board... 0 Outline Dimensions... 6 Ordering Guide... 7 REVISION HISTORY 0/ Rev. C to Rev. D Changes to Figure 4 and Table Updated Outline Dimensions (Changed CP-- to CP--7)... 6 Changes to Ordering Guide /04 Data Sheet changed from Rev. B to Rev. C Changes to Format... Universal Changes to Specifications... Changes to the Ordering Guide /0 Data Sheet changed from Rev. A to Rev. B Added CP- Package (LFCSP)... Universal Changes to Several Pin Names... Universal Changes to Features... Changes to Product Description... Changes to Product Highlights... Changes to Specifications... Replaced Figure... Changes to Absolute Maximum Ratings... 5 Changes to Ordering Guide... 5 Changes to Pin Function Descriptions... 6 New Definitions of Specifications Section... 7 Changes to TPCs to... 9 Changes to Theory of Operation Section... Changes to Analog Input Section... Changes to Single-ended Input Configuration Section... 4 Replaced Figure Changes to Clock Input Considerations Section... 4 Changes to Table I... 5 Changes to Power Dissipation and Standby Mode Section... 5 Changes to Digital Outputs Section... 5 Changes to Timing Section... 5 Changes to Figure... 6 Changes to Figures 6 to Added LFCSP Evaluation Board Section... 7 Inserted Figures 7 to Added Table III... 0 Updated Outline Dimensions... 8/0 Data Sheet changed from Rev. 0 to Rev. A Updated RU-8 Package... 4 Rev. D Page of 40

3 Data Sheet SPECIFICATIONS DC SPECIFICATIONS = V, DRVDD =.5 V, maximum sample rate, V p-p differential input,.0 V internal reference, TMIN to TMAX, unless otherwise noted. Table. Test BRU/BCP-0 BRU/BCP-40 BRU/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full VI Bits ACCURACY No Missing Codes Guaranteed Full VI Bits Offset Error Full VI ±0.0 ±.0 ±0.50 ±.0 ±0.50 ±.0 % FSR Gain Error Full VI ±0.0 ±.40 ±0.50 ±.50 ±0.50 ±.60 % FSR Differential Nonlinearity (DNL) Full IV ±0.5 ±0.65 ±0.5 ±0.75 ±0.40 ±0.80 LSB 5 C I ±0.5 ±0.5 ±0.5 LSB Integral Nonlinearity (INL) Full IV ±0.45 ±0.80 ±0.50 ±0.90 ±0.70 ±.0 LSB 5 C I ±0.40 ±0.40 ±0.45 LSB TEMPERATURE DRIFT Offset Error Full V ± ± ± ppm/ C Gain Error Full V ± ± ± ppm/ C INTERNAL VOLTAGE REFERENCE Output Voltage Error ( V Mode) Full VI ±5 ±5 ±5 ±5 ±5 ±5 mv Load ma Full V mv Output Voltage Error (0.5 V Mode) Full V ±.5 ±.5 ±.5 mv Load 0.5 ma Full V mv INPUT REFERRED NOISE VREF = 0.5 V 5 C V LSB rms VREF =.0 V 5 C V LSB rms ANALOG INPUT Input Span, VREF = 0.5 V Full IV V p-p Input Span, VREF =.0 V Full IV V p-p Input Capacitance Full V pf REFERENCE INPUT RESISTANCE Full V kω POWER SUPPLIES Supply Voltages Full IV V DRVDD Full IV V Supply Current I Full V ma IDRVDD Full V 5 7 ma PSRR Full V ±0.0 ±0.0 ±0.0 % FSR POWER CONSUMPTION DC Input 4 Full V mw Sine Wave Input Full VI mw Standby Power 5 Full V mw Gain error and gain temperature coefficient are based on the ADC only (with a fixed.0 V external reference). Measured at maximum clock rate, fin =.4 MHz, full-scale sine wave, with approximately 5 pf loading on each output bit. Input capacitance refers to the effective capacitance between one differential input pin and A. Refer to Figure 5 for the equivalent analog input structure. 4 Measured with dc input at maximum clock rate. 5 Standby power is measured with a dc input, the CLK pin inactive (i.e., set to or A). Rev. D Page of 40

4 Data Sheet DIGITAL SPECIFICATIONS Table. Test BRU/BCP-0 BRU/BCP-40 BRU/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit LOGIC INPUTS High Level Input Voltage Full IV V Low Level Input Voltage Full IV V High Level Input Current Full IV µa Low Level Input Current Full IV µa Input Capacitance Full V pf LOGIC OUTPUTS DRVDD =. V High-Level Output Voltage Full IV V (IOH = 50 µa) High-Level Output Voltage Full IV V (IOH = 0.5 ma) Low-Level Output Voltage Full IV V (IOL =.6 ma) Low-Level Output Voltage Full IV V (IOL = 50 µa) DRVDD =.5 V High-Level Output Voltage Full IV V (IOH = 50 µa) High-Level Output Voltage Full IV V (IOH = 0.5 ma) Low-Level Output Voltage Full IV V (IOL =.6 ma) Low-Level Output Voltage Full IV V (IOL = 50 µa) Output voltage levels measured with 5 pf load on each output. SWITCHING SPECIFICATIONS Table. Test BRU/BCP-0 BRU/BCP-40 BRU/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Maximum Conversion Rate Full VI MSPS Minimum Conversion Rate Full V MSPS CLK Period Full V ns CLK Pulse-Width High Full V ns CLK Pulse-Width Low Full V ns DATA OUTPUT PARAMETERS Output Delay (tpd) Full V ns Pipeline Delay (Latency) Full V Cycles Aperture Delay (ta) Full V ns Aperture Uncertainty Jitter (tj) Full V ps rms Wake-Up Time Full V ms OUT-OF-RANGE RECOVERY TIME Full V Cycles For the -65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -0 and -40 models. Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pf load on each output. Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0. µf and 0 µf capacitors on REFT and REFB. Rev. D Page 4 of 40

5 Data Sheet ANALOG INPUT N N N+ t A N+ N+ N+4 N+5 N+6 N+7 N+8 CLK DATA OUT N 9 N 8 N 7 N 6 N 5 N 4 N N N N t PD = 6.0ns MAX.0ns MIN AC SPECIFICATIONS Figure. Timing Diagram = V, DRVDD =.5 V, maximum sample rate, V p-p differential input, AIN = 0.5 dbfs,.0 V internal reference, TMIN to TMAX, unless otherwise noted. Table 4. BRU/BCP-0 BRU/BCP-40 BRU/BCP-65 Parameter Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO finput =.4 MHz 5 C V dbc finput = 9.7 MHz Full IV dbc 5 C I 70.6 dbc finput = 9.6 MHz Full IV dbc 5 C I 70.4 dbc finput =.5 MHz Full IV dbc 5 C I 70. dbc finput = 00 MHz 5 C V dbc SIGNAL-TO-NOISE RATIO AND DISTORTION finput =.4 MHz 5 C V dbc finput = 9.7 MHz Full IV dbc 5 C I 70.5 dbc finput = 9.6 MHz Full IV dbc 5 C I 70. dbc finput =.5 MHz Full IV dbc 5 C I 69.9 dbc finput = 00 MHz 5 C V dbc TOTAL HARMONIC DISTORTION finput =.4 MHz 5 C V dbc finput = 9.7 MHz Full IV dbc 5 C I 87.4 dbc finput = 9.6 MHz Full IV dbc 5 C I 86.0 dbc finput =.5 MHz Full IV dbc 5 C I 8.0 dbc finput = 00 MHz 5 C V dbc WORST HARMONIC (SECOND OR THIRD) finput = 9.7 MHz Full IV dbc finput = 9.6 MHz Full IV dbc finput =.5 MHz Full IV dbc Rev. D Page 5 of 40

6 Data Sheet BRU/BCP-0 BRU/BCP-40 BRU/BCP-65 Parameter Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE finput =.4 MHz 5 C V dbc finput = 9.7 MHz Full IV dbc 5 C I 9.0 dbc finput = 9.6 MHz Full IV dbc 5 C I 90.0 dbc finput =.5 MHz Full IV dbc 5 C I 85.0 dbc finput = 00 MHz 5 C V dbc Rev. D Page 6 of 40

7 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Pin Name With Respect to Min Max Unit ELECTRICAL A V DRVDD D V A D V DRVDD V Digital D 0. DRVDD + 0. V Outputs CLK, MODE A V VIN+, VIN A V VREF A V SENSE A V REFB, REFT A V PDWN A V ENVIRONMENTAL Operating Temperature C Junction Temperature 50 C Lead Temperature (0 sec) 00 C Storage Temperature C Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. EXPLANATION OF TEST LEVELS Test Levels I II III IV V VI Description 00% production tested. 00% production tested at 5 C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 00% production tested at 5 C; guaranteed by design and characterization testing for industrial temperature range; 00% production tested at temperature extremes for military devices. Typical thermal impedances (8-lead TSSOP), θja = 67.7 C/W; (-lead LFCSP), θja =.5 C/W, θjc =.7 C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD5-. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D Page 7 of 40

8 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OTR MODE SENSE VREF 4 REFB 5 REFT 6 7 A 8 VIN+ 9 VIN 0 TOP VIEW (Not to Scale) D (MSB) D0 D9 D8 DRVDD D D7 D6 D5 D4 DNC CLK DNC PDWN 4 DNC 5 DNC 6 D0 (LSB) 7 D 8 A VIN VIN+ A REFT REFB TOP VIEW (Not to Scale) 4 VREF SENSE MODE OTR 0 D (MSB) 9 D0 8 D9 7 D8 A CLK PDWN D D D D0 (LSB) D D D4 D5 D6 D7 D DRVDD NOTES. DNC = DO NOT CONNECT.. IT IS RECOMMENDED THAT THE EXPOSED PADDLE BE SOLDERED TO THE GROUND PLANE Figure. 8-Lead TSSOP Pin Configuration Figure 4. -Lead LFCSP Pin Configuration Table 6. Pin Function Descriptions Pin No. 8-Lead TSSOP Pin No. -Lead LFCSP Mnemonic Description OTR Out-of-Range Indicator. MODE Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection. SENSE Reference Mode Selection. 4 4 VREF Voltage Reference Input/Output. 5 5 REFB Differential Reference ( ). 6 6 REFT Differential Reference (+). 7, 7, Analog Power Supply. 8, 8, A Analog Ground. 9 9 VIN+ Analog Input Pin (+). 0 0 VIN Analog Input Pin ( ). CLK Clock Input Pin. 4 4 PDWN Power-Down Function Selection (Active High). 5 to, 5 to 8 7 to 4, 7 to 0 D0 (LSB) to D (MSB) Data Output Bits. 5 D Digital Output Ground. 4 6 DRVDD Digital Output Driver Supply. Must be decoupled to D with a minimum. 0. µf capacitor. Recommended decoupling is 0. µf in parallel with 0 µf.,, 5, 6 DNC Do Not Connect. EP EPAD Exposed Pad. It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of the package is achieved with exposed paddle soldered to the customer board. Rev. D Page 8 of 40

9 Data Sheet DEFINITIONS OF SPECIFICATIONS Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by db. Aperture Delay (ta) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Jitter (tj) The sample-to-sample variation in aperture delay. Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level ½ LSBs beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to -bit resolution indicates that all 4096 codes must be present over all operating ranges. Offset Error The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN. Offset error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition should occur at an analog value ½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (5 C) value to the value at TMIN or TMAX. Power Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Total Harmonic Distortion (THD) The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 0.5 db below full scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Effective Number of Bits (ENOB) The ENOB for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD using the following formula N = (SINAD.76)/6.0 Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set at 0.5 db below full scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious-Free Dynamic Range (SFDR) The difference in db between the rms amplitude of the input signal and the peak spurious signal. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Clock Pulse Width and Duty Cycle Pulse-width high is the minimum amount of time that the clock pulse should be left in the Logic state to achieve rated performance. Pulse-width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than db below the guaranteed limit. Maximum Conversion Rate The clock rate at which parametric testing is performed. Output Propagation Delay (tpd) The delay between the clock logic threshold and the time when all bits are within valid logic levels. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 0% above positive full scale to 0% above negative full scale, or from 0% below negative full scale to 0% below positive full scale. AC specifications may be reported in dbc (degrades as signal levels are lowered) or in dbfs (always related back to converter full scale). Rev. D Page 9 of 40

10 Data Sheet EQUIVALENT CIRCUITS DRVDD VIN+, VIN D D0, OTR Figure 5. Equivalent Analog Input Circuit Figure 7. Equivalent Digital Output Circuit MODE 0kΩ CLK, PDWN Figure 6. Equivalent MODE Input Circuit Figure 8. Equivalent Digital Input Circuit Rev. D Page 0 of 40

11 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS =.0 V, DRVDD =.5 V, fsample = 65 MSPS with DCS disabled, TA = 5 C, V differential input, AIN = 0.5 dbfs, VREF =.0 V, unless otherwise noted. MAGNITUDE (dbfs) SNR = 70.dBc SINAD = 70.dBc ENOB =.4 BITS THD = 86.dBc SFDR = 89.9dBc SNR/SFDR (dbc) SFDR (V DIFF) SNR (V DIFF) SNR (V SE) SFDR (V SE) FREQUENCY (MHz) SAMPLE RATE (MSPS) Figure 9. Single Tone 8K FFT with fin = 0 MHz Figure. -65: Single Tone SNR/SFDR vs. fclk with fin = Nyquist (.5 MHz) MAGNITUDE (dbfs) SNR = 69.4dBc SINAD = 69.dBc ENOB =. BITS THD = 8.0dBc SFDR = 8.8dBc SNR/SFDR (dbc) SFDR (V DIFF) SNR (V SE) SFDR (V SE) SNR (V DIFF) FREQUENCY (MHz) SAMPLE RATE (MSPS) Figure 0. Single Tone 8K FFT with fin = 70 MHz Figure. -40: Single Tone SNR/SFDR vs. fclk with fin = Nyquist (0 MHz) MAGNITUDE (dbfs) SNR = 68.5dBc SINAD = 66.5dBc ENOB = 0.8 BITS THD = 7.0dBc SFDR = 7.dBc SNR/SFDR (dbc) SFDR (V DIFF) SFDR (V SE) SNR (V SE) SNR (V DIFF) FREQUENCY (MHz) SAMPLE RATE (MSPS) Figure. Single Tone 8K FFT with fin = 00 MHz Figure 4. -0: Single Tone SNR/SFDR vs. fclk with fin = Nyquist (0 MHz) Rev. D Page of 40

12 Data Sheet 00 SFDR SINGLE-ENDED (dbfs) SFDR DIFFERENTIAL (dbfs) 95 SNR/SFDR (dbfs and dbc) SFDR DIFFERENTIAL (dbc) SNR DIFFERENTIAL (dbfs) SFDR SINGLE-ENDED (dbc) SNR SINGLE-ENDED (dbfs) SNR SINGLE-ENDED (dbc) 50 SNR DIFFERENTIAL (dbc) A IN (dbfs) SNR/SFDR (dbc) 90 SFDR SNR INPUT FREQUENCY (MHz) Figure : Single Tone SNR/SFDR vs. AIN with fin = Nyquist (.5 MHz) Figure : SNR/SFDR vs. fin 00 SFDR DIFFERENTIAL (dbfs) 95 SNR/SFDR (dbfs and dbc) SNR DIFFERENTIAL (dbfs) SFDR DIFFERENTIAL (dbc) SNR DIFFERENTIAL (dbc) SNR SINGLE-ENDED (dbfs) SNR SINGLE-ENDED (dbc) A IN (dbfs) SFDR SINGLE-ENDED (dbfs) SFDR SINGLE-ENDED (dbc) SNR/SFDR (dbc) 90 SFDR SNR INPUT FREQUENCY (MHz) Figure : Single Tone SNR/SFDR vs. AIN with fin = Nyquist (0 MHz) Figure : SNR/SFDR vs. fin 00 SFDR DIFFERENTIAL (dbfs) 95 SNR/SFDR (dbfs and dbc) SFDR SINGLE-ENDED (dbfs) SNR DIFFERENTIAL (dbfs) SNR DIFFERENTIAL(dBc) SFDR DIFFERENTIAL (dbc) SNR SINGLE-ENDED (dbfs) SFDR SINGLE-ENDED(dBc) SNR/SFDR (dbc) SFDR SNR SNR SINGLE-ENDED (dbc) A IN (dbfs) INPUT FREQUENCY (MHz) Figure 7. -0: Single Tone SNR/SFDR vs. AIN with fin = Nyquist (0 MHz) Figure 0. -0: SNR/SFDR vs. fin Rev. D Page of 40

13 Data Sheet 0 0 SNR = 64.6dBFS SFDR = 8.6dBFS V SFDR MAGNITUDE (dbfs) SNR/SFDR (dbfs) V SFDR V SNR V SNR FREQUENCY (MHz) A IN (dbfs) Figure. Dual Tone 8K FFT with fin = 45 MHz and fin = 46 MHz Figure 4. Dual Tone SNR/SFDR vs. AIN with fin = 45 MHz and fin = 46 MHz 0 0 SNR = 64.dBFS SFDR = 8.dBFS V SFDR V SFDR MAGNITUDE (dbfs) SNR/SFDR (dbfs) V SNR V SNR FREQUENCY (MHz) A IN (dbfs) Figure. Dual Tone 8K FFT with fin = 69 MHz and fin = 70 MHz Figure 5. Dual Tone SNR/SFDR vs. AIN with fin = 69 MHz and fin = 70 MHz 0 0 SNR = 6.5dBFS SFDR = 75.6dBFS V SFDR MAGNITUDE (dbfs) SNR/SFDR (dbfs) V SFDR V SNR V SNR FREQUENCY (MHz) A IN (dbfs) Figure. Dual Tone 8K FFT with fin = 44 MHz and fin = 45 MHz Figure 6. Dual Tone SNR/SFDR vs. AIN with fin = 44 MHz and fin = 45 MHz Rev. D Page of 40

14 Data Sheet : V SINAD -40: V SINAD -65: V SINAD SINAD (dbc) : V SINAD -65: V SINAD -40: V SINAD ENOB (Bits) GAIN DRAFT (ppm/ C) SAMPLE RATE (MSPS) TEMPERATURE ( C) Figure 7. SINAD vs. fclk with fin = Nyquist Figure 0. A/D Gain vs. Temperature Using an External Reference SFDR: DCS ON SFDR: DCS OFF SINAD/SFDR (dbc) SINAD: DCS ON SINAD: DCS OFF INL (LSB) DUTY CYCLE (%) CODE Figure 8. SINAD/SFDR vs. Clock Duty Cycle Figure. Typical INL SFDR V DIFF 0.8 SINAD/SFDR (dbc) SFDR V DIFF SINAD V DIFF SINAD V DIFF DNL (LSB) SAMPLE RATE (MSPS) CODE Figure 9. SINAD/SFDR vs. Temperature with fin =.5 MHz Figure. Typical DNL Rev. D Page 4 of 40

15 Data Sheet APPLYING THE THEORY OF OPERATION The architecture consists of a front end SHA followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4-bit first stage followed by eight.5-bit stages and a final -bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final -bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The outputstaging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. ANALOG INPUT The analog input to the is a differential switched capacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input can support a wide common-mode range and maintain excellent performance, as shown in Figure 4. An input common-mode voltage of midsupply minimizes signaldependent errors and provides optimum performance. Referring to Figure, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC s input; therefore, the precise values are dependent upon the application. In IF undersampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they would limit the input bandwidth. For best dynamic performance, the source impedances driving VIN+ and VIN should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. VIN+ VIN C PAR C PAR T T 5pF 5pF Figure. Switched-Capacitor SHA Input An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as: REFT = ½( + VREF) REFB = ½( VREF) Span = (REFT REFB) = VREF It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. SNR (dbc) THD 5MHz V DIFF SNR.5MHz V DIFF SNR 5MHz V DIFF COMMON-MODE LEVEL (V) T T H H THD.5MHz V DIFF Figure : SNR, THD vs. Common-Mode Level THD (dbc) Rev. D Page 5 of 40

16 The internal voltage reference can be pin-strapped to fixed values of 0.5 V or.0 V, or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the set to the largest input span of V p-p. The relative SNR degradation is db when changing from V p-p mode to V p-p mode. The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as: VCMMIN = VREF/ VCMMAX = ( + VREF)/ The minimum common-mode input level allows the to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a single-ended source may be driven into VIN+ or VIN. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a V p-p signal may be applied to VIN+ while a V reference is applied to VIN. The then accepts an input signal varying between V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies and in the lower speed grade models (-40 and -0). Differential Input Configurations As previously detailed, optimum performance is achieved while driving the in a differential input configuration. For baseband applications, the AD88 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD88 is easily set to /, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. Vp-p 49.9Ω kω kω 499Ω 5Ω 499Ω Ω 5pF AD88 Ω 499Ω 5pF VIN+ VIN A Figure 5. Differential Input Configuration Using the AD88 At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 00 MHz range are being sampled. For these applications, Data Sheet differential transformer coupling is the recommended input configuration, as shown in Figure 6. Vp-p 49.9Ω Ω 5pF Ω kω 5pF kω VIN+ VIN A Figure 6. Differential Transformer-Coupled Configuration The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion. Single-Ended Input Configuration A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is degradation in SFDR and in distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance. Figure 7 details a typical singleended input configuration. Vp-p 0µF 49.9Ω 0.µF kω kω kω kω Ω 5pF Ω 5pF VIN+ VIN A Figure 7. Single-Ended Input Configuration CLOCK INPUT CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result, may be sensitive to clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the. As shown in Figure 0, noise and distortion performance are nearly flat over a 0% range of duty cycle. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 00 clock cycles to allow the DLL to acquire and lock to the new rate Rev. D Page 6 of 40

17 Data Sheet High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (finput) due only to aperture jitter (tj) can be calculated by SNR Degradation = 0 log0[π finput tj] In the equation, the rms aperture jitter, tj, represents the rootsum square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. TOTAL POWER (mw) -40 The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. POWER DISSIPATION AND STANDBY MODE As shown in Figure 8, the power dissipated by the is proportional to its sample rate. The digital power dissipation does not vary substantially between the three speed grades because it is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current can be calculated as IDRVDD = VDRVDD CLOAD fclk N where N is the number of output bits, in the case of the. This maximum current occurs when every output bit switches on every clock cycle, i.e., a full-scale square wave at the Nyquist frequency, fclk/. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the encode rate and the characteristics of the analog input signal SAMPLE RATE (MSPS) Figure 8. Total Power vs. Sample Rate with fin = 0 MHz For the -0 speed grade, the digital power consumption can represent as much as 0% of the total dissipation. Digital power consumption can be minimized by reducing the capacitive load presented to the output drivers. The data in Figure 8 was taken with a 5 pf load on each output driver. The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases linearly with the clock frequency. By asserting the PDWN pin high, the is placed in standby mode. In this state, the ADC typically dissipates mw if the CLK and analog inputs are static. During standby, the output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the into its normal operational mode. Low power dissipation in standby mode is achieved by shutting down the reference, reference buffer, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering standby mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake-up times. With the recommended 0. µf and 0 µf decoupling capacitors on REFT and REFB, it takes approximately sec to fully discharge the reference buffer decoupling capacitors and ms to restore full operation Rev. D Page 7 of 40

18 Data Sheet Table 7. Reference Configuration Summary Selected Mode SENSE Voltage Internal Switch Position Resulting VREF (V) Resulting Differential Span (V p-p) External Reference N/A N/A External Reference Internal Fixed Reference VREF SENSE Programmable Reference 0. V to VREF SENSE 0.5 ( + R/R) VREF (See Figure 40) Internal Fixed Reference A to 0. V Internal Divider.0.0 DIGITAL OUTPUTS The output drivers can be configured to interface with.5 V or. V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fan-outs may require external buffers or latches. As detailed in Table 8, the data format can be selected for either offset binary or twos complement. Timing The provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tpd) after the rising edge of the clock signal. Refer to Figure for a detailed timing diagram. The length of the output data lines and loads placed on them should be minimized to reduce transients within the ; these transients can detract from the converter s dynamic performance. The lowest typical conversion rate of the is MSPS. At clock rates below MSPS, dynamic performance may degrade. VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the. The input range can be adjusted by varying the reference voltage applied to the, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage). Internal Reference Connection A comparator within the detects the potential at the SENSE pin and configures the reference into one of four possible states, which are summarized in Table 7. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 9), setting VREF to V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected as shown in Figure 40, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as VREF = 0.5 ( + R/R) VIN+ VIN VREF + 0µF SENSE SELECT LOGIC ADC CORE 0.5V REFT REFB + 0µF Figure 9. Internal Reference Configuration In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. VIN+ VIN VREF + 0µF R SENSE R SELECT LOGIC ADC CORE 0.5V REFT REFB + 0µF Figure 40. Programmable Reference Configuration Rev. D Page 8 of 40

19 Data Sheet External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset temperature drift. Figure 4 shows the typical drift characteristics of the internal reference in both V and 0.5 V modes. VREF ERROR (%) VREF =.0V VREF = 0.5V TEMPERATURE ( C) Figure 4. Typical VREF Drift When the SENSE pin is tied to, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 kω load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of V. If the internal reference of the is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 4 depicts how the internal reference voltage is affected by loading. ERROR (%) V ERROR (%) 0.5V ERROR (%) OPERATIONAL MODE SELECTION As discussed earlier, the can output data in either offset binary or twos complement format. There is also a provision for enabling or disabling the clock DCS. The MODE pin is a multilevel input that controls the data format and DCS state. The input threshold values and corresponding mode selections are outlined in Table 8. Table 8. Mode Selection MODE Voltage Data Format Duty Cycle Stabilizer Twos Complement Disabled / Twos Complement Enabled / Offset Binary Enabled A (Default) Offset Binary Disabled The MODE pin is internally pulled down to A by a 0 kω resistor. TSSOP EVALUATION BOARD The evaluation board provides the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially, through an AD88 driver or a transformer, or single-ended. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). Figure 4 shows the typical bench characterization setup used to evaluate the ac performance of the. It is critical that signal sources with very low phase noise (< ps rms jitter) be used to realize the ultimate performance of the converter. Proper filtering of the input signal, to remove harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance. The AUXCLK input should be selected in applications requiring the lowest jitter and SNR performance, i.e., IF undersampling characterization. It allows the user to apply a clock input signal that is 4 the target sample rate of the. A low-jitter, differential divide-by-4 counter, the MC00LVELD, provides a clock output that is subsequently returned back to the CLK input via JP9. For example, a 60 MHz signal (sinusoid) is divided down to a 65 MHz signal for clocking the ADC. Note that R must be removed with the AUXCLK interface. Lower jitter is often achieved with this interface since many RF signal generators display improved phase noise at higher output frequencies and the slew rate of the sinusoidal output signal is 4 that of a signal of equal amplitude. Complete schematics and layout plots follow and demonstrate the proper routing and grounding techniques that should be applied at the system level LOAD (ma) Figure 4. VREF Accuracy vs. Load Rev. D Page 9 of 40

20 + LFCSP EVALUATION BOARD The typical bench setup used to evaluate the ac performance of the is similar to the TSSOP Evaluation Board connections (refer to the schematics for connection details). The can be driven single-ended or differentially through a transformer. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). Data Sheet An alternative differential analog input path using an AD85 op amp is included in the layout but is not populated in production. Designers interested in evaluating the op amp with the ADC should remove C5, R, and R and populate the op amp circuit. The passive network between the AD85 outputs and the allows the user to optimize the frequency response of the op amp for the application. V + V V + V + REFIN 0MHz REFOUT HP8644, V p-p SIGNAL SYNTHESIZER HP8644, V p-p CLOCK SYNTHESIZER BAND-PASS FILTER CLOCK DIVIDER DUT S4 XFMR INPUT S CLOCK DUT DRVDD TSSOP EVALUATION BOARD DVDD J DATA CAPTURE AND PROCESSING Figure 4. TSSOP Evaluation Board Connections Rev. D Page 0 of 40

21 Data Sheet RP Ω D0O D0 RP Ω DO D RP Ω DO D RP Ω DO D RP5 Ω D8O D8 RP5 Ω D9O D9 RP5 Ω D0O D0 RP5 Ω DO D RP4 Ω D4O D4 RP4 Ω D5O D5 RP4 Ω D6O D6 RP4 Ω D7O D DUTIN TB A TB IN TB DRVDDIN TB 5 A TB 4 5 C58 µf 5V + C47 µf 5V + C48 µf 5V + FBEAD L C59 FBEAD L C5 FBEAD L C5 RP6 Ω 8 RP6 Ω 7 RP6 Ω 6 RP6 Ω OTRO OTR 4 5 TP RED TP RED TP RED JP JP DUT JP DUTDRVDD R 0kΩ R4 0kΩ R7 5kΩ C 0µF 0V C4 C0 0µF 0V R0 kω R7 kω R4 kω ΩHT TP5 C5 JP7 JP DUT JP C57 C JP5 0µF 0V + + C C JP6 JP JP JP4 C 0µF 0V SHEET C50 C8 + DUT C6 C9 0.00µF ΩHT TP7 C4 0.00µF VIN+ VIN C 0µF 0V + + A SENSE VREF PDΩN REFB REFT MODE VIN+ VIN A D DRVDD U C7 OTR D D0 D9 D8 D7 D6 D5 D4 D D D D0 CLK OTRO D0O DO DO DO D4O D5O D6O D7O D8O D9O D0O DO DUTCLK ΩHT TP6 DUTDRVDD C µF DVDDIN TB 6 C6 µf 5V + FBEAD L4 C4 TP4 TP9 RED BLK DVDD TP BLK TP BLK TP0 BLK TP BLK TP5 BLK TP4 BLK TP6 BLK Figure 44. TSSOP Evaluation Board Schematic, DUT Rev. D Page of 40

22 Data Sheet C DVDD AUXCLK S5 5 R 49.9W 4 T R W R4 90W CLOCK S C7 JP9 R9 500W CW C R 49.9W MC00LVELD VCC U NC OUT INA REF INB VEE INCOM R 0W 6 R W R5 90W T T 4 C4 N57 U8 DECOUPLING C6 R5 0kW D D R6 0kW C8 0µF 0V N57 D0 D D D D4 D5 D6 D7 D8 R8 D9 500W ; 4 D0 ; 7 D WHT R7 U8 U8 TP7 W DUTCLK OTR VHC04 74VHC04 JP4 U8 JP 4 74VHC04 U8 74VHC04 U8 0 + R9 W C4 0µF 0V + 9 G G 0 VCC 0 A 8 Y A 7 Y 4 6 A U6 Y 5 74VHC54 5 A4 Y4 6 A5 4 Y5 7 A6 Y6 A7 Y7 9 A8 Y8 8 C C5 0µF 0V + 9 G G 0 VCC 0 A 8 Y A 7 Y 4 6 A U7 Y 5 74VHC54 5 A4 Y4 6 A5 4 Y5 7 A6 Y6 A7 Y7 9 A8 Y8 8 C0 U9 DECOUPLING C8 0µF 0V RP W 6 RP W 5 RP W 4 RP W 4 RP W 5 RP W 6 RP W 7 0 RP W 8 9 RP W 6 RP W 5 RP W 4 RP W 4 RP W 5 RP W 6 RP W 7 0 RP W 8 9 DD0 DD DD DD DD4 DD5 DD6 DD7 DD8 DD9 DD0 DD DOTR DACLK HEADER RIGHT ANGLE MALE NO EJECTORS HDR40RAM J U VHC Figure 45. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering Rev. D Page of 40

23 Data Sheet AMP INPUT S C8 R4 5Ω R5 499Ω R 49.9Ω IN 8 +IN C9 0µF + 0V ALT VEE TP8 RED A B JP8 AD88 U 6 C5 0µF 0V C69 C VAL R7 499Ω VCC 4 5 VEE R6 499Ω C7 VAL VO+ VO SINGLE INPUT S R5 49.9Ω VOC R kω R kω C8 R6 40Ω R0 40Ω XFMR INPUT S4 C4 VAL C45 VAL R4 49.9Ω JP5 C9 0.µF 6 R kω R4 kω T T 5 4 T C7 R6 kω R8 kω C5 0.µF JP4 JP40 JP45 JP46 JP4 JP4 C6 R Ω R Ω C44 5pF VIN+ C44B C4 5pF VIN Figure 46. TSSOP Evaluation Board Schematic, Analog Inputs DACLK DD0 DD DD DD DD4 DD5 DD6 DD7 DD8 DD9 DD0 DD AD976 U4 MSB-DB CLOCK DB0 DB9 DB8 DB7 DB6 DB5 DB4 DB DVDD 7 DCOM 6 NC 5 4 COMP IOUTA IOUTB ACOM 0 0 DB COMP 9 DB FSADJ 8 DB0 REFIO 7 NC REFLO 6 4 NC SLEEP 5 C0 C49 C 0.0µF C56 R0 kω C5 DVDD C9 C46 0.0µF ΩHT TP8 R9 49.9Ω C55 pf R8 49.9Ω C54 pf S Figure 47. TSSOP Evaluation Board Schematic, Optional DAC Rev. D Page of 40

24 Data Sheet Figure 48. TSSOP Evaluation Board Layout, Primary Side Rev. D Page 4 of 40

25 Data Sheet Figure 49. TSSOP Evaluation Board Layout, Secondary Side Rev. D Page 5 of 40

26 Data Sheet Figure 50. TSSOP Evaluation Board Layout, Ground Plane Rev. D Page 6 of 40

27 Data Sheet _ Figure 5. TSSOP Evaluation Board Power Plane Rev. D Page 7 of 40

28 Data Sheet Figure 5. TSSOP Evaluation Board Layout, Primary Silkscreen Rev. D Page 8 of 40

29 Data Sheet Figure 5. TSSOP Evaluation Board Layout, Secondary Silkscreen Rev. D Page 9 of 40

30 Data Sheet EXTREF V MAX E R9 0kΩ R 0kΩ C P7 A P9 B C E P0 P8 D C9 0.0µF P C7 C9 0µF + C 0.0µF C C 0µF P6 R5 kω MODE P P5 R7 kω P R6 kω 4 P4 C DRVDD VDL VAMP.0V.5V.5V 5.0V OVERRANGE BIT (MSB) P H MTHOLE6 H MTHOLE6 H MTHOLE6 H4 MTHOLE6 C6 AMPIN X OUT R4 0Ω R 0Ω T C5 ADT ΩT R0 J XFRIN 6Ω C6 6 0pF L 5 E 45 CT 0nH NC 4 AMP C6 PRI SEC C5 OPTIONAL XFR R R T 6Ω 0Ω FT C X OUT B X FRIN 5 X OUT AMPINB CT 4 X OUT B C8 PRI SEC R6 kω R4 kω R XX C9 5pF R5 Ω R8 R SINGLE ENDED R, R7, R8 5Ω ONLY ONE SHOULD BE ON BOARD AT A TIME R6 kω C 0pF OR L FOR FILTER C 0pF R kω VIN+ VIN R5 kω VREF SENSE 5 REFB REFT 8 A 9 VIN+ 0 VIN A DNC CLK CLK P4 MODE DNC OTR U4 PDΩN P D DNC D0 R8 kω D9 D8 DRVDD 6 DRVDD D 5 D7 4 DNC D0 D D6 D5 D4 D 0 D 9 (LSB) SENSE PIN SOLDERABLE JUMPER E TO A E TO B E TO C E TO D RP 0Ω EXTERNAL VOLTAGE DIVIDER INTERNAL V REFERENCE (DEFAULT) EXTERNAL REFERENCE INTERNAL 0.5V REFERENCE MODE PIN SOLDERABLE JUMPER RP 0Ω 5 TO TΩOS COMPLEMENT/DCS OFF 5 TO TΩOS COMPLEMENT/DCS OFF 5 TO OFFSET BINARY/DCS ON 5 TO 4 OFFSET BINARY/DCS OFF DRX DX DX DX D0X D9X D8X D7X D6X D5X D4X DX DX DX D0X Figure 54. LFCSP Evaluation Board Schematic, Analog Inputs and DUT Rev. D Page 0 of 40

31 Data Sheet Rev. D Page of 40 DRX DX DX DX D0X DX DX DRVDD D0X D9X D8X D7X D5X D6X D4X DX DRVDD CLK DB D7 D6 D5 V CC D D CLK D4 D D D D7 D6 D5 D8 V CC D4 D QB Q7 Q6 Q5 V CC Q Q OE Q4 Q Q Q Q8 Q7 Q6 Q5 V CC Q4 Q IN OUT CLKAT/DAC 74LVTH674 U CLKLAT/DAC DRY MSB LSB DR MSB HEADER 40 DRY DRVDD DRVDD AMPIN AMPINB VAMP C7 C8 C5 0.0µF C7 R6 0Ω R4 5Ω R40 0kΩ PΩDN RGP INHI INLO RPG R4 0kΩ R5 5Ω R4.kΩ AMP IN AMP AD85 U POΩER DOΩN USE R40 OR R4 C44 COMM OPLO OPH VPOS VOCM R 5Ω R4 0kΩ R9 50Ω VAMP VAMP R8 kω R9 kω C4 0µF C45 R7 0Ω OE + Figure 55. LFCSP Evaluation Board Schematic, Digital Path

32 A A A 4A 4B Data Sheet VDL DRVDD DRVDD + C0 µf + C4 0µF + C 0µF C5 0µF C 0.00µF C C4 0.00µF C4 ANALOG BYPASSING DUT BYPASSING CLOCK TIMING ADJUSTMENTS FOR A BUFFERED ENCODE USE R8 FOR A DIRECT ENCODE USE R7 ENCX ENC R8 0Ω R7 0Ω CLK ENC E50 E5 R kω VDL E5 E5 ENCODE J R9 50Ω C4 VDL R kω R0 kω R0 kω VDL E E5 R kω VDL E4 E44 R4 kω VDL C µf C0 0.00µF C DIGITAL BYPASSING B 4 5 B 9 0 B C4 C6 74VCX86 Y Y Y 4Y PΩR C8 0.00µF C9 0.00µF ENCX VDL VDL C C47 C µF C µF + C0 0µF LATCH BYPASSING VAMP SCHEMATIC SHOΩS TΩO GATE DELAY SETUP FOR ONE DELAY REMOVE R AND R7 AND ATTACH Rx (Rx = 0Ω) R 0Ω CLKAT/DAC R7 5Ω Rx DNP DR R 0Ω C7 + C46 0µF C µF Figure 56. LFCSP Evaluation Board Schematic, Clock Input Rev. D Page of 40

33 Data Sheet Figure 57. LFCSP Evaluation Board Layout, Primary Side Figure 59. LFCSP Evaluation Board Layout, Ground Plane Figure 58. LFCSP Evaluation Board Layout, Secondary Side Figure 60. LFCSP Evaluation Board Layout, Power Plane Rev. D Page of 40

34 Data Sheet Figure 6. LFCSP Evaluation Board Layout, Primary Silkscreen Figure 6. LFCSP Evaluation Board Layout, Secondary Silkscreen Rev. D Page 4 of 40