8-Bit, 40/80/100 MSPS Dual A/D Converter AD9288

Transcription

1 FEATURES Dual -bit, 0 MSPS, 0 MSPS, and 00 MSPS ADC Low power: 90 mw at 00 MSPS per channel On-chip reference and track-and-hold MHz analog bandwidth each channel SNR = MHz V p-p analog input range each channel Single.0 V supply operation (. V to. V) Standby mode for single-channel operation Twos complement or offset binary output mode Output data alignment mode Pin-compatible 0-bit upgrade available APPLICATIONS Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes I and Q communications ENC A A IN A A IN A REF IN A REF OUT REF IN B A IN B A IN B ENC B -Bit, 0/0/00 MSPS Dual A/D Converter AD9 FUNCTIONAL BLOCK DIAGRAM TIMING TIMING T/H T/H AD9 ADC REF ADC V D V DD Figure. OUTPUT REGISTER OUTPUT REGISTER V DD D A D0 A SELECT SELECT DATA FORMAT SELECT D B D0 B GENERAL DESCRIPTION The AD9 is a dual -bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits. It is optimized for low cost, low power, small size, and ease of use. The product operates at a 00 MSPS conversion rate with outstanding dynamic performance over its full operating range. Each channel can be operated independently. The ADC requires only a single.0 V (. V to. V) power supply and an Encode clock for full-performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS-compatible, and a separate output power supply pin supports interfacing with. V or. V logic. The Encode input is TTL/CMOS-compatible, and the -bit digital outputs can be operated from.0 V (. V to. V) supplies. User-selectable options offer a combination of standby modes, digital data formats, and digital data timing schemes. In standby mode, the digital outputs are driven to a high impedance state. Fabricated on an advanced CMOS process, the AD9 is available in a -lead surface-mount plastic package ( mm mm,. mm LQFP) specified over the industrial temperature range ( 0 C to + C). The AD9 is pin-compatible with the 0-bit AD9, facilitating future system migrations. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 90, Norwood, MA 00-90, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 * PRODUCT PAGE QUICK LINKS Last Content Update: 0//0 COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Application Notes AN-0: Exploit Digital Advantages in an SSB Receiver AN-: Understanding High Speed ADC Testing and Evaluation Data Sheet AD9: -Bit, 0/0/00 MSPS Dual A/D Converter Data Sheet TOOLS AND SIMULATIONS AD9 IBIS Models REFERENCE MATERIALS Technical Articles Correlating High-Speed ADC Performance to Multicarrier G Requirements DNL and Some of its Effects on Converter Performance Single Chip Realizes Direct-Conversion Rx DESIGN RESOURCES AD9 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all AD9 EngineerZone Discussions. AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

3 TABLE OF CONTENTS Specifications... Explanation of Test Levels... Timing Diagrams... Absolute Maximum Ratings... ESD Caution... Pin Configuration and Function Descriptions... Typical Performance Characteristics... 9 Test Circuits... Terminology... Theory of Operation... Using the AD9... Encode Input... Digital Outputs... Analog Input... Voltage Reference... Timing... User-Selectable Options... AD9/AD9 Customer PCB BOM... Evaluation Board... Power Connector... Analog Inputs... Voltage Reference... Clocking... Data Outputs... Data Format/Gain... Timing... Troubleshooting... 0 Outline Dimensions... Ordering Guide... REVISION HISTORY /0 Rev. B to Rev. C Change to Absolute Maximum Ratings... Replaced Evaluation Board Section... Updated Outline Dimensions... Changes to Ordering Guide... /0 Rev. A to Rev. B Edits to ABSOLUTE MAXIMUM RATINGS... /0 Rev. 0 to Rev. A /99 Revision 0: Initial Version Rev. C Page of

4 SPECIFICATIONS VDD =.0 V; VD =.0 V, differential input; external reference, unless otherwise noted. Table. AD9 Test AD9BST-00 AD9BST-0 AD9BST-0 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Bits DC ACCURACY Differential Nonlinearity C I ± ± ± LSB Full VI LSB Integral Nonlinearity C I ± ± ± LSB Full VI LSB No Missing Codes Full VI Guaranteed Guaranteed Guaranteed Gain Error C I ±. + ±. + ±. + % FS Full VI % FS Gain Tempco Full VI ppm/ C Gain Matching C V ±. ±. ±. % FS Voltage Matching C V ± ± ± mv ANALOG INPUT Input Voltage Range (with Full V ± ± ± mv p-p Respect to AIN) Common-Mode Voltage Full V VD VD VD 0. V VD VD VD VD VD VD Input Offset Voltage C I ±0 + ± 0 + ± 0 + mv Full VI mv Reference Voltage Full VI V Reference Tempco Full VI ± 0 ± 0 ± 0 ppm/ C Input Resistance C I kω Full VI Input Capacitance C V pf Analog Bandwidth, Full C V MHz Power SWITCHING PERFORMANCE Maximum Conversion Rate Full VI MSPS Minimum Conversion Rate C IV MSPS Encode Pulse Width High (teh) C IV ns Encode Pulse Width Low (tel) C IV ns Aperture Delay (ta) C V ps Aperture Uncertainty (Jitter) C V ps rms Output Valid Time (tv) Full VI ns Output Propagation Delay Full VI ns (tpd) DIGITAL INPUTS Logic Voltage Full VI V Logic 0 Voltage Full VI V Logic Current Full VI ± ± ± µa Logic 0 Current Full VI ± ± ± µa Input Capacitance C V pf DIGITAL OUTPUTS Logic Voltage Full VI... V Logic 0 Voltage Full VI V POWER SUPPLY Power Dissipation Full VI mw Standby Dissipation, Full VI mw Power Supply Rejection Ratio (PSRR) C I mv/v Rev. C Page of

5 Test AD9BST-00 AD9BST-0 AD9BST-0 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Transient Response C V ns Overvoltage Recovery Time C V ns Signal-to-Noise Ratio (SNR) (without Harmonics) fin = 0. MHz C I... db fin = MHz C I. db fin = MHz C I.0 db Signal-to-Noise Ratio (SINAD) (with Harmonics) fin = 0. MHz C I db fin = MHz C I db fin = MHz C I db Effective Number of Bits fin = 0. MHz C I...0. Bits fin = MHz C I..0. Bits fin = MHz C I.0.. Bits Second Harmonic Distortion fin = 0. MHz C I dbc fin = MHz C I 0 0 dbc fin = MHz C I 0 0 dbc Third Harmonic Distortion fin = 0. MHz C I dbc fin = MHz C I 0 0 dbc fin = MHz C I 0 0 dbc Two-Tone Intermod Distortion (IMD) fin = 0. MHz C V dbc Gain error and gain temperature coefficient are based on the ADC only (with a fixed. V external reference). tv and tpd are measured from the. V level of the Encode input to the 0%/90% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 0 pf or a dc current of ±0 µa. Digital supply current based on VDD =.0 V output drive with < 0 pf loading under dynamic test conditions. Power dissipation measured under the following conditions: fs = 00 MSPS, analog input is 0. dbfs, both channels in operation. Standby dissipation calculated with Encode clock in operation. SNR/harmonics based on an analog input voltage of 0. dbfs referenced to a.0 V full-scale input range. EXPLANATION OF TEST LEVELS Level Description I 00% production tested. II 00% production tested at C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 00% production tested at C; guaranteed by design and characterization testing for industrial temperature range; 00% production tested at temperature extremes for military devices. Rev. C Page of

6 TIMING DIAGRAMS N N + N + A IN A, A IN B t A N + N + N + t EH t EL /fs ENCODE A, B t PD t V D A D0 A DATA N DATA N DATA N DATA N DATA N DATA N + D B D0 B DATA N DATA N DATA N DATA N DATA N DATA N + Figure. Normal Operation, Same Clock (S =, S = 0) Channel Timing N N + N + N + N + A IN A, A IN B t A t EH t EL /fs ENCODE A t PD t V ENCODE B D A D0 A DATA N DATA N DATA N DATA N DATA N DATA N + D B D0 B DATA N DATA N DATA N DATA N DATA N + DATA N + Figure. Normal Operation with Two Clock Sources (S =, S = 0) Channel Timing Rev. C Page of

7 N N + N + N + N + A IN A, A IN B t A t EH t EL /fs ENCODE A t PD t V ENCODE B D A D0 A DATA N DATA N DATA N DATA N DATA N DATA N + D B D0 B DATA N 9 DATA N DATA N DATA N DATA N DATA N + Figure. Data Align with Two Clock Sources (S =, S = ) Channel Timing Rev. C Page of

8 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating VD, VDD V Analog Inputs 0. V to VD + 0. V Digital Inputs 0. V to VDD + 0. V VREF IN 0. V to VD + 0. V Digital Output Current 0 ma Operating Temperature C to + C Storage Temperature C to +0 C Maximum Junction Temperature 0 C Maximum Case Temperature 0 C Thermal Impedance θja C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C Page of

9 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V D ENC A V DD D A (MSB) D A D A D A D A D A D A D0 A 0 9 A IN A A IN A DFS REF IN A REF OUT REF IN B S S 9 A IN B 0 A IN B PIN IDENTIFIER AD9 TOP VIEW (Not to Scale) 9 0 NC NC V DD V D 0 V D 9 V DD NC NC V D NC = NO CONNECT ENC B V DD (MSB) D B D B D B D B D B D B D B D0 B Figure. Pin Configuration Table. Pin No. Name Description,,,, 9, Ground,, AINA Analog Input for Channel A. AINA Analog Input for Channel A (Complementary). DFS Data Format Select. Offset binary output available if set low. Twos complement output available if set high. REFINA Reference Voltage Input for Channel A. REFOUT Internal Reference Voltage. REFINB Reference Voltage Input for Channel B. S User Select. Refer to Table. Tied with respect to VD. 9 S User Select. Refer to Table. Tied with respect to VD. 0 AINB Analog Input for Channel B (Complementary). AINB Analog Input for Channel B., 0,, VD Analog Supply ( V). ENCB Clock Input for Channel B.,,, VDD Digital Supply ( V). DB D0 B Digital Output for Channel B.,,, NC Do Not Connect. D0A D A Digital Output for Channel A. ENC A Clock Input for Channel A Rev. C Page of

10 TYPICAL PERFORMANCE CHARACTERISTICS db ENCODE = 00MSPS A IN = 0.MHz SNR =.db SINAD =.0dB SECOND HARMONIC =.dbc THIRD HARMONIC =.dbc db 0 RD ND ENCODE RATE = 00MSPS MHz Figure. Spectrum: fs = 00 MSPS, fin = 0 MHz, Single-Ended Input Figure 9. Harmonic Distortion vs. AIN Frequency ENCODE = 00MSPS A IN = MHz SNR =.db SINAD =.db SECOND HARMONIC =.0dBc THIRD HARMONIC =.dbc ENCODE = 00MSPS A IN = 9.MHz A IN = 0.MHz IMD = 0.0dBc 0 0 db 0 db Figure. Spectrum: fs = 00 MSPS, fin = MHz, Single-Ended Input Figure 0. Two-Tone Intermodulation Distortion ENCODE = 00MSPS A IN = MHz SNR =.db SINAD =.db SECOND HARMONIC =.dbc THIRD HARMONIC =.dbc 0 SINAD ENCODE RATE = 00MSPS SNR 0 db 0 db MHz 00-0 Figure. Spectrum: fs = 00 MSPS, fin = MHz, Single-Ended Input Figure. SINAD/SNR vs. AIN Frequency Rev. C Page 9 of

11 9 A IN = 0.MHz SNR 90 A IN = 0.MHz SINAD 0 db POWER (mw) MSPS MSPS 00-0 Figure. SINAD/SNR vs. Encode Rate Figure. Analog Power Dissipation vs. Encode Rate 0 SNR A IN = 0.MHz.0. ENCODE RATE = 00MSPS A IN = 0.MHz SINAD.0 SNR..0 SINAD db db ENCODE HIGH PULSE WIDTH (ns) TEMPERATURE ( C) 00-0 Figure. SINAD/SNR vs. Encode Pulse Width High Figure. SINAD/SNR vs. Temperature ENCODE RATE = 00MSPS ENCODE RATE = 00MSPS A IN = 0.MHz.0 0. db db % GAIN BANDWIDTH (MHz) TEMPERATURE ( C) 00-0 Figure. ADC Frequency Response: fs = 00 MSPS Figure. ADC Gain vs. Temperature (with External. V Reference) Rev. C Page 0 of

12 .0... ENCODE = 00MSPS V D =.0V T A = C.0 LSB V REFOUT (V) CODE LOAD (ma) Figure. Integral Nonlinearity Figure 0. Voltage Reference Out vs. Current Load LSB CODE Figure 9. Differential Nonlinearity Rev. C Page of

13 TEST CIRCUITS V D V DD kω A IN kω kω A IN kω 00-0 OUT 00-0 Figure. Equivalent Analog Input Circuit Figure. Equivalent Digital Output Circuit V D V D V BIAS REF IN 00-0 OUT Figure. Equivalent Reference Input Circuit V D Figure. Equivalent Reference Output Circuit ENCODE Figure. Equivalent Encode Input Circuit Rev. C Page of

14 TERMINOLOGY Analog Bandwidth (Small Signal) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by db. Aperture Delay The delay between a 0% crossing of Encode and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal LSB step. Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the Encode pulse should be left in Logic state to achieve rated performance; pulse width low is the minimum time Encode pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of LSB using a best straight line determined by a least square curve fit. Minimum Conversion Rate The Encode rate at which the SNR of the lowest analog signal frequency drops by no more than db below the guaranteed limit. Maximum Conversion Rate The Encode rate at which parametric testing is performed. Output Propagation Delay The delay between a 0% crossing of Encode and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at db below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set at db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dbc (i.e., degrades as signal level is lowered), or in dbfs (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dbc (i.e., degrades as signal level is lowered), or in dbfs (always related back to converter full scale). Worst Harmonic The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dbc. Rev. C Page of

15 THEORY OF OPERATION The AD9 ADC architecture is a bit-per-stage pipeline-type converter utilizing switch capacitor techniques. These stages determine the MSBs and drive a -bit flash. Each stage provides sufficient overlap and error correction, allowing optimization of comparator accuracy. The input buffers are differential, and both sets of inputs are internally biased. This allows the most flexible use of ac or dc and differential or single-ended input modes. The output staging block aligns the data, carries out the error correction, and feeds the data to output buffers. The set of output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. There is no discernible difference in performance between the two channels. USING THE AD9 Good high speed design practices must be followed when using the AD9. To obtain maximum benefit, decoupling capacitors should be physically as close as possible to the chip, minimizing trace and via inductance between chip pins and capacitor (00 surface-mount capacitors are used on the AD9/PCB evaluation board). It is recommended to place a 0. µf capacitor at each power-ground pin pair for high frequency decoupling, and to include one 0 µf capacitor for local low frequency decoupling. The VREF IN pin should also be decoupled by a 0. µf capacitor. It is also recommended to use a split power plane and a contiguous ground plane (see the Evaluation Board section). Data output traces should be short (< inch), minimizing on-chip noise at switching. ENCODE INPUT Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track-andhold circuit is essentially a mixer. Any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the Encode (Clock) input of the AD9, and the user is advised to give commensurate thought to the clock source. The Encode input is fully TTL/CMOS-compatible. DIGITAL OUTPUTS The digital outputs are TTL/CMOS-compatible for lower power consumption. During standby, the output buffers transition to a high impedance state. A data format selection option supports either twos complement (set high) or offset binary output (set low) formats. ANALOG INPUT The analog input to the AD9 is a differential buffer. For best dynamic performance, impedance at AIN and AIN should match. Special care was taken in the design of the analog input stage of the AD9 to prevent damage and corruption of data when the input is overdriven. The nominal input range is.0 V p-p centered at VD 0.. VOLTAGE REFERENCE A stable and accurate. V voltage reference is built into the AD9 (REFOUT). In normal operation, the internal reference is used by strapping Pins (REFINA) and (REFINB) to Pin (REFOUT). The input range can be adjusted by varying the reference voltage applied to the AD9. No appreciable degradation in performance occurs when the reference is adjusted ±%. The full-scale range of the ADC tracks reference voltage, which changes linearly. TIMING The AD9 provides latched data outputs, with four pipeline delays. Data outputs are available one propagation delay (tpd) after the rising edge of the Encode command (see Figure, Figure, and Figure ). The length of the output data lines and loads placed on them must be minimized to reduce transients within the AD9. These transients can detract from the converter s dynamic performance. The minimum guaranteed conversion rate of the AD9 is MSPS. At clock rates below MSPS, dynamic performance degrades. Typical power-up recovery time after standby mode is clock cycles. USER-SELECTABLE OPTIONS Two pins are available for a combination of operational modes. These options allow the user to place both channels, excluding the reference, into standby mode, or just the B channel. Both modes place the output buffers and clock inputs into high impedance states. The other option allows the user to skew the B channel output data by / of a clock cycle. In other words, if two clocks are fed to the AD9 and are 0 out of phase, enabling the data align allows Channel B output data to be available at the rising edge of Clock A. If the same Encode clock is provided to both channels and the data align pin is enabled, then output data from Channel B is 0 out of phase with respect to Channel A. If the same Encode clock is provided to both channels and the data align pin is disabled, both outputs are delivered on the same rising edge of the clock. Table. User-Selectable Options S S Option 0 0 Standby Both Channels A and B. 0 Standby Channel B Only. 0 Normal Operation (Data Align Disabled). Data Align Enabled (data from both channels available on rising edge of Clock A. Channel B data is delayed a / clock cycle). Rev. C Page of

16 AD9/AD9 CUSTOMER PCB BOM Table. Bill of Materials No. Qty. Reference Designator Device Package Value Comments AD9 9 C, C-C, C0, C, C, Capacitor µf C, C, C0 C, C9 C C, C Capacitor 00 pf out C C9, C, C, C Capacitor TAJD 0 µf E, E, E, E, E E0, W-HOLE W-HOLE E E H, H, H, H MTHOLE MTHOLE J, J, J, J, J SMA SMA J, J, not placed P, P, P -pin power connector Post Z...0 Wieland P, P, P -pin power connector Detachable.0..0 Wieland Connector 9 P, P 0-pin rt. angle male TSW-0-0- Samtec L-D-RA 0 R, R, R, R Resistor 00 Ω R, R, R, R, not placed 9 R, R, R, R, R, R, R, R0, R R, R, R, R9, R0, R, R, R0, R, R, R, R, R0, R, R, R0, R Resistor 00 0 Ω R, R, R, R, R0, R not placed Resistor 00 Zero Ω R, R0 not placed R, R Resistor 00 Ω R, R not placed R, R, R, R, R9, R Resistor Ω R, R9 not placed R, R Resistor 00 Ω R9, R Resistor 00 kω R, R, R9, R, R, Resistor 00 kω R R9, R, R, R T, T Transformer ADT-WT Minicircuits 9 U AD9 LQFP 0 U, U LCX U, U SNVCX U, U, U9, U0 Resistor array CTS Ω 00G U, U AD op amp P, P are implemented as one physical 0-pin connector SAMTEC TSW-0-0-L-D-RA. AD9/PCB populated with AD9-00. To use optional amp: place R, R, R0, R, R, R9, remove R, R. Rev. C Page of

17 EVALUATION BOARD The AD9/AD9 customer evaluation board offers an easy way to test the AD9 or the AD9. The compatible pinout of the two parts facilitates the use of one PCB for testing either part. The PCB requires power supplies, a clock source, and a filtered analog source for most ADC testing required. POWER CONNECTOR Power is supplied to the board via a detachable -lead power strip. The minimum V supplies required to run the board are VDD, VDL, and VDD. To allow the use of the optional amplifier path, ± V supplies are required. ANALOG INPUTS Each channel has an independent analog path that uses a wideband transformer to drive the ADC differentially from a single-ended sine source at the input SMAs. The transformer paths can be bypassed to allow the use of a dc-coupled path by using two AD op amps with a simple board modification. The analog input should be band-pass filtered to remove any harmonics in the input signal and to minimize aliasing. VOLTAGE REFERENCE The AD9 has an internal. V voltage reference; an external reference for each channel can be used instead by connecting two external voltage references at the power connector and setting jumpers at E and E9. The evaluation board is shipped configured for internal reference mode. CLOCKING Each channel can be clocked by a common clock input at SMA input ENCODE A/B. The channels can also be clocked independently by a simple board modification. The clock input should be a low jitter sine source for maximum performance. DATA OUTPUTS The data outputs are latched on-board by two 0-bit latches and drive an -pin connector which is compatible with the dualchannel FIFO board available from Analog Devices. This board, together with ADC analyzer software, can greatly simplify ADC testing. DATA FORMAT/GAIN The DFS/Gain pin can be biased for desired operation at the DFS jumper located at the S, S jumpers. TIMING Timing on each channel can be controlled if needed on the PCB. Clock signals at the latches or the data ready signals that go to the output 0-pin connector can be inverted if required. Jumpers also allow for biasing of Pins S and S for powerdown and timing alignment control. Rev. C Page of

18 C 0µF V +V V D V DD V DL V REF A V REF B + C 0µF P 00-0 ENCA D9A (MSB) DA DA DA DA DA DA DA VD VDD V DL V DD V D V REF B V REF A P P C C D A D0 A D0 B D B C C V DD V DD C V D VDD VD ENCB (MSB) D9B DB DB DB DB DB DB DB C R AMPOUTA J R 0Ω C R Ω R AIN A AMPINA C T R Ω AMPOUTAB R AMPINB R Ω J C R Ω R AIN B R 0Ω AMPOUTB C R C0 R Ω R Ω REFOUT VD E E E C9 VD E E E E0 VREFA E0 VD E9 E E E E E E9 9 0 A IN A A IN A DFS/GAIN REF IN A REF OUT REF IN B S S A IN B A IN B VD ENCA VDD D9A DA DA DA DA DA DA DA 0 9 AD9/AD9 U VD ENCB VDD D9B DB DB DB DB DB DB DB **DUT CLOCK SELECTABLE** **TO BE DIRECT OR BUFFERED** ENCODE A J TIEA C0 VDL ENCXA ENCA R9 kω R R R 0Ω R kω VDL E E R kω ENCXA R SINGLE-ENDED R SINGLE-ENDED AMPOUTBB C T R A B Y A B U LCX VCC B A Y B Y A 9 Y 0 C R0 R9 DRA VDL CLKLATA R kω R kω E E E E VDL VDL ENCODE B J R0 Ω TIEB C VDL ENCXB ENCB R R kω R kω VDL R0 ENCXB E VDL E R9 kω C 9 0 Y A B Y A U LCX Y B A Y B B VCC A R **DUT CLOCK SELECTABLE** **TO BE DIRECT OR BUFFERED** R CLKLATB DRB R kω R kω E E E E VDL VDL C0 D A D0 A V DD V D V D V DD D0 B D B TO TIE CLOCKS TOGETHER C9 C C ENC A ENC B R J R 0Ω R0 R0 TIEA TIEB P V +V P P C 0µF C 0µF V D V DD V DL C 0µF C9 0µF C 0µF C REF IN A C REF IN B H MTHOLE H MTHOLE H MTHOLE H MTHOLE Figure. PCB Schematic Rev. C Page of

19 00-0 R R OPAMP INPUT OFF PIN ONE OF TRANSFORMER AMPINA R R Ω AD +V V C +IN NC V OUT IN VOCM V+ +OUT U +V C R9 kω R kω R 0Ω C pf R 0Ω AMPOUTAB AMPOUTA AMPINB R9 R Ω AD +V V C +IN NC V OUT IN VOCM V+ +OUT U +V C R kω R kω R 0Ω C pf R0 0Ω AMPOUTB AMPOUTBB R R D9A DA DA DA DA DA DA DA 9 DA 9 D0A 0 0 D0B DB DB DB DB DB DB DB 9 DB 9 D9B 0 0 U CTS0 VALUE = 0 U CTS0 VALUE = D9M DM DM DM DM DM DM DM DM D0M D0N DN DN DN DN DN DN DN DN D9N D9M DM DM DM DM DM DM DM 9 DM 0 D0M D0N DN DN DN DN DN DN DN 9 DN 0 D9N U LCX OE VCC X0 Y0 X Y X Y X Y X Y X Y X Y X Y X Y X9 Y9 CLK U LCX OE VCC X0 Y0 X Y X Y X Y X Y X Y X Y X Y X Y X9 Y9 CLK C VDL D9X D9X DX DX DX DX DX DX DX DX DX DX DX DX DX DX DX 9 DX D0X 0 D0X CLKLATA C0 VDL D0Y D0Y DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY 9 DY D9Y 0 D9Y CLKLATB U9 CTS0 VALUE = 0 U0 CTS0 VALUE = D9P DP DP DP DP DP DP DP DP D0P D0Q DQ DQ DQ DQ DQ DQ DQ DQ D9Q P HEADER0 P HEADER DRA D9P DP DP DP DP DP DP DP DP D0P DRB D9Q DQ DQ DQ DQ DQ DQ DQ DQ D0Q Figure. PCB Schematic (Continued) Rev. C Page of

20 00-0 Figure. Top Silkscreen Figure. Split Power Plane 00-0 Figure 9. Top Routing Figure. Bottom Routing Figure 0. Ground Plane Figure. Bottom Silkscreen 00-0 Rev. C Page 9 of

21 TROUBLESHOOTING If the board does not seem to be working correctly, try the following: Verify power at the IC pins. Check that all jumpers are in the correct position for the desired mode of operation. Verify that VREF is at. V. Try running Encode clock and analog inputs at low speeds (0 MSPS/ MHz) and monitor LCX outputs, DAC outputs, and ADC outputs for toggling. The AD9/AD9 evaluation board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose. Rev. C Page 0 of

22 OUTLINE DIMENSIONS MAX 9.00 BSC SQ SEATING PLANE VIEW A ROTATED 90 CCW SEATING PLANE MAX COPLANARITY VIEW A 0.0 BSC COMPLIANT TO JEDEC STANDARDS MS-0BBC PIN TOP VIEW (PINS DOWN) BSC SQ Figure. -Lead Low Profile Quad Flat Package [LQFP] (ST-) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Options AD9BST-0 0 C to + C -Lead Low Profile Quad Flat Package ST- AD9BSTZ-0 0 C to + C -Lead Low Profile Quad Flat Package ST- AD9BSTZRL-0 0 C to + C -Lead Low Profile Quad Flat Package ST- AD9BST-0 0 C to + C -Lead Low Profile Quad Flat Package ST- AD9BSTZ-0 0 C to + C -Lead Low Profile Quad Flat Package ST- AD9BST-00 0 C to + C -Lead Low Profile Quad Flat Package ST- AD9BSTZ-00 0 C to + C -Lead Low Profile Quad Flat Package ST- AD9/PCB Evaluation Board Z = Pb-free part. Rev. C Page of

23 NOTES Rev. C Page of

24 NOTES Rev. C Page of

25 NOTES 00 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00 0 /0(C) Rev. C Page of