10-Bit, 40/65/80/105 MSPS 3 V Dual Analog-to-Digital Converter AD9218

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1 -Bit, //8/ MSPS V Dual Analog-to-Digital Converter AD98 FEATURES Dual -bit, MSPS, MSPS, 8 MSPS, and MSPS ADC Low power: 7 mw at MSPS per channel On-chip reference and track-and-hold MHz analog bandwidth each channel SNR = 7 MHz, Encode = 8 MSPS V p-p or V p-p analog input range each channel. V single-supply operation (.7 V to. V) Power-down mode for single-channel operation Twos complement or offset binary output mode Output data alignment mode Pin compatible with the 8-bit AD988 7 dbc crosstalk between channels APPLICATIONS Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes I and Q communications Ultrasound equipment ENCODE A A IN A A IN A REF IN A REF OUT REF IN B A IN B A IN B ENCODE B FUNCTIONAL BLOCK DIAGRAM TIMING T/H T/H TIMING ADC REF ADC / / Figure. AD98 OUTPUT REGISTER OUTPUT REGISTER / / V D V DD D9 A TO D A USER SELECT NO. USER SELECT NO. DATA FORMAT/ GAIN D9 B TO D B - GENERAL DESCRIPTION The AD98 is a dual -bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits. The product is low cost, low power, and is small and easy to use. The AD98 operates at a MSPS conversion rate with outstanding dynamic performance over its full operating range. Each channel can be operated independently. The ADC requires only a single. V (.7 V to. V) power supply and a clock for full operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with. V or. V logic. The clock input is TTL/CMOS compatible and the -bit digital outputs can be operated from. V (. V to. V) supplies. User-selectable options offer a combination of power-down modes, digital data formats, and digital data timing schemes. In power-down mode, the digital outputs are driven to a high impedance state. PRODUCT HIGHLIGHTS. Low Power. Only 7 mw power dissipation per channel at MSPS. Other speed grades proportionally scaled down while maintaining high ac performance.. Pin Compatibility Upgrade. Allows easy migration from 8-bit to -bit devices. Pin compatible with the 8-bit AD988 dual ADC.. Easy to Use. On-chip reference and user controls provide flexibility in system design.. High Performance. Maintains db SNR at MSPS with a Nyquist input.. Channel Crosstalk. Very low at 7 dbc.. Fabricated on an Advanced CMOS Process. Available in a 8-lead low profile quad flat package (7 mm 7 mm LQFP) specified over the industrial temperature range ( C to +8 C). Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Fax: 78.. Analog Devices, Inc. All rights reserved.

2 AD98 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Product Highlights... Revision History... Specifications... DC Specifications... Digital Specifications... AC Specifications... Switching Specifications... Timing Diagrams... Absolute Maximum Ratings... 8 Explanation of Test Levels... 8 ESD Caution... 8 Pin Configuration and Function Descriptions... 9 Terminology... Equivalent Circuits... Typical Performance Characteristics... Theory of Operation... 8 Using the AD98 ENCODE Input... 8 Digital Outputs... 8 Analog Input... 8 Voltage Reference... 9 Timing... 9 User Select Options... 9 Application Information... 9 AD98/AD988 Customer PCB BOM... Evaluation Board... Power Connector... Analog Inputs... Voltage Reference... Clocking... Data Outputs... Data Format/Gain... Timing... Troubleshooting... Outline Dimensions... Ordering Guide... REVISION HISTORY / Rev. B to Rev. C Updated Format...Universal Changes to DC Specifications... / Rev. A. to Rev. B Updated format...universal Changes to General Description... Changes to DC Specifications... Changes to Switching Specifications... Added AD98/AD988 Customer PCB BOM section... Added Evaluation Board section... 7/ Rev. to Rev. A Updated Ordering Guide... Changes to Terminology section....8 Changes to Figure 7b... 9 Updated Outline Dimensions... Rev. C Page of 8

3 AD98 SPECIFICATIONS DC SPECIFICATIONS VDD =. V, VD =. V; external reference, unless otherwise noted. Table. Test AD98BST-/- AD98BST-8/- Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION Bits ACCURACY No Missing Codes Full VI Guaranteed, not tested Guaranteed, not tested Offset Error C I LSB Gain Error C I 8. 8 % FS Differential Nonlinearity C I ±./±. /. ±./±.8./.7 LSB (DNL) Full VI ±.8 ±./±.9 LSB Integral Nonlinearity C I /. ±./± /../.7 ±.7/± +./.7 LSB (INL) Full VI ± ±/±. LSB TEMPERATURE DRIFT Offset Error Full V ppm/ C Gain Error Full V 8 ppm/ C Reference Full V ppm/ C REFERENCE Internal Reference Voltage C I V (REFOUT) Input Resistance (REFINA, Full VI 9 9 kω REFINB) ANALOG INPUTS Differential Input Voltage Full V or V Range (AIN, AIN) Common-Mode Voltage Full V VD/ VD/ V Input Resistance Full VI 8 8 kω Input Capacitance C V pf POWER SUPPLY VD Full IV V VDD Full IV V Supply Currents IVD (VD =. V) Full VI 8/7 / 7/8 7/88 ma IVDD (VDD =. V) C V 7/ /7 ma Power Dissipation DC Full VI / /9 / / mw IVD Power-Down Current Full VI ma Power Supply Rejection Ratio C I ± ± mv/v No missing codes across industrial temperature range guaranteed for MSPS, MSPS, and 8 MSPS grades. No missing codes at room temperature guaranteed for MSPS grade. Gain error and gain temperature coefficients are based on the ADC only (with a fixed. V external reference) grade in V p-p range,, 8, grades in V p-p range. (AIN AIN) = ±. V in V range (full scale), (AIN AIN) = ± V in V range (full scale). The analog inputs self-bias to VD/. This common-mode voltage can be overdriven externally by a low impedance source by ± mv (differential drive, gain = ) or ± mv (differential drive, gain = ). AC power dissipation measured with rated encode and a. MHz analog dbfs, CLOAD = pf. DC power dissipation measured with rated encode and a dc analog input (outputs static, IVDD = ). In power-down state, IVDD = ± μa typical (all grades). Rev. C Page of 8

4 AD98 DIGITAL SPECIFICATIONS VDD =. V, VD =. V; external reference, unless otherwise noted. Table. Test AD98BST-/- AD98BST-8/- Parameter Temp Level Min Typ Max Min Typ Max Unit DIGITAL INPUTS Encode Input Common Mode Full V VD/ VD/ V Encode Voltage Full VI V Encode Voltage Full VI.8.8 V Encode Input Resistance Full VI kω Logic Voltage S, S, Full VI V DFS Logic Voltage S, S, Full VI.8.8 V DFS Logic Current S Full VI ± ± μa Logic Current S Full VI μa Logic Current S Full VI μa Logic Current S Full VI ± ± μa Logic Current DFS Full VI μa Logic Current DFS Full VI μa Input Capacitance S, C V pf S, Encode Inputs Input Capacitance DFS C V.. pf DIGITAL OUTPUTS Logic Voltage Full VI.. V Logic Voltage Full VI.. V Output Coding Twos complement or offset binary Twos complement or offset binary Rev. C Page of 8

5 AD98 AC SPECIFICATIONS VDD =. V, VD =. V; external reference, unless otherwise noted. Table. Test AD98BST-/- AD98BST-8/- Parameter Temp Level Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) (Without Harmonics) fin =. MHz C I 8/ 9/7 7/ 8/ db fin = Nyquist C I / 9/ / 7/ db Signal-to-Noise and Distortion (SINAD) (With Harmonics) fin =. MHz C I 8/ 9/ / 8/ db fin = Nyquist C I / 9/ / 7/ db Effective Number of Bits fin =. MHz C I 9./8.8 9./9. 9./8. 9./8. Bits fin = Nyquist C I /8. 9./8.9 9/8. 9./8. Bits Second Harmonic Distortion fin =. MHz C I 7/ 89/ 77 9/ 77/ 8 dbc fin = Nyquist C I / 89/ 7 / 7 7/ dbc Third Harmonic Distortion fin =. MHz C I 8/ 79/ 8 / 7 7/ dbc fin = Nyquist C I / 78/ / 7 7/ 9 dbc Spurious Free Dynamic Range (SFDR) fin =. MHz C I 8/ 79/ 7 / 7 9/ dbc fin = Nyquist C I / 78/ / 7 7/ dbc Two-Tone Intermodulation Distortion (IMD) fin = MHz, fin = MHz at 7 dbfs C V 7/ 7 dbc fin = MHz, fin = MHz at 7 dbfs C V 7/ 7 77/ 7 dbc Analog Bandwidth, Full Power C V MHz Crosstalk C V 7 7 dbc AC specifications based on an analog input voltage of. dbfs at. MHz, unless otherwise noted. AC specifications for, 8, grades are tested in V p-p range and driven differentially. AC specifications for grade are tested in V p-p range and driven differentially. The, 8, and grades are tested close to Nyquist for that grade: MHz, 9 MHz, and MHz for the, 8, and grades, respectively. Rev. C Page of 8

6 AD98 SWITCHING SPECIFICATIONS VDD =. V, V D =. V; external reference, unless otherwise noted. Table. Test AD98BST-/- AD98BST-8/- Parameter Temp Level Min Typ Max Min Typ Max Unit ENCODE INPUT PARAMETERS Maximum Encode Rate Full VI / 8/ MSPS Minimum Encode Rate Full IV / / MSPS Encode Pulse Width High (teh) Full IV 7/ /.8 ns Encode Pulse Width Low (tel) Full IV 7/ /.8 ns Aperture Delay (ta) C V ns Aperture Uncertainty (Jitter) C V ps rms DIGITAL OUTPUT PARAMETERS Output Valid Time (tv) Full VI.. ns Output Propagation Delay (tpd) Full VI. 7. ns Output Rise Time (tr) C V. ns Output Fall Time (tf) C V.. ns Out-of-Range Recovery Time C V ns Transient Response Time C V ns Recovery Time from Power-Down C V Cycles Pipeline Delay Full IV Cycles t V and tpd are measured from the. level of the ENCODE input to the %/% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of pf or a dc current of ± μa. Rise and fall times are measured from % to 9%. TIMING DIAGRAMS N N + N + N + A IN A A IN B t A teh t EL /f S N + N + N + ENCODE A ENCODE B t PD t V D9 A TO D A DATA N DATA N DATA N DATA N DATA N DATA N D9 B TO D B DATA N DATA N DATA N DATA N DATA N DATA N - Figure. Normal Operation, Same Clock (S =, S = ) Channel Timing Rev. C Page of 8

7 AD98 N N + N + N + 7 N + 8 A IN A A IN B t A teh t EL N + N + N + N + /f S ENCODE A t PD t V ENCODE B D9 A TO D A DATA N DATA N 8 DATA N DATA N DATA N DATA N DATA N + D9 B TO D B DATA N 9 DATA N 7 DATA N DATA N DATA N DATA N + - Figure. Normal Operation with Two Clock Sources (S =, S = ) Channel Timing N N + N + N + 7 N + 8 A IN A A IN B t A teh t EL N + N + N + N + /f S ENCODE A t PD t V ENCODE B D9 A TO D A DATA N DATA N 8 DATA N DATA N DATA N DATA N DATA N + D9 B TO D B DATA N DATA N 9 DATA N 7 DATA N DATA N DATA N DATA N + - Figure. Data Align with Two Clock Sources (S =, S = ) Channel Timing Rev. C Page 7 of 8

8 AD98 ABSOLUTE MAXIMUM RATINGS Table. EXPLANATION OF TEST LEVELS Parameter Rating I. % production tested. VD, VDD V II. % production tested at C and sample tested at Analog Inputs. V to VD +. V specified temperatures. Digital Inputs. V to V DD +. V REFIN Inputs. V to VD +. V III. Sample tested only. Digital Output Current ma Operating Temperature C to + C IV. Parameter is guaranteed by design and characterization Storage Temperature C to + C testing. Maximum Junction Temperature C Maximum Case Temperature C V. Parameter is a typical value only. θa (measured on a -layer board with 7 C/W VI. % production tested at C; guaranteed by design solid ground plane) and characterization testing for industrial temperature range. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. % production tested at temperature extremes for military devices. Table. User Select Modes S S Power-Down and Data Alignment Settings Power down both Channel A and Channel B. Power down Channel B only. Normal operation (data align disabled). Data align enabled (data from both channels available on rising edge of Clock A. Channel B data is delayed by a ½ clock cycle.) ESD CAUTION Rev. C Page 8 of 8

9 AD98 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V D ENC A V DD D9 A (MSB) D8 A D7 A D A D A D A D A D A A IN A A IN A DFS/GAIN REF IN A REF OUT REF IN B 7 S 8 S 9 A IN B A IN B D A D A V DD V D V D 9 8 V DD 7 D B D B AD98 TOP VIEW (Not to Scale) V D ENC B V DD (MSB) D9 B D8 B D7 B D B D B D B D B D B Figure. Pin Configuration - Table 7. Pin Function Descriptions Pin Number Mnemonic Description,,, 7, 9,,, AINA Ground. Analog Input for Channel A. A IN A Analog Input for Channel A (Complementary). DFS/GAIN Data Format Select and Analog Input Gain Mode. Low = offset binary output available, V p-p supported; high = twos complement output available, V p-p supported; floating = offset binary output available, V p-p supported; set to V REF = twos complement output available, V p-p supported. REFINA Reference Voltage Input for Channel A. REFOUT Internal Reference Voltage. 7 REFINB Reference Voltage Input for Channel B. 8 S User Select No.. See Table. 9 S User Select No.. See Table. A IN B Analog Input for Channel B (Complementary). AINB Analog Input for Channel B.,,, 8 VD Analog Supply ( V). ENC B Clock Input for Channel B., 8,, V DD Digital Supply (. V to. V). 7 to D9 B to D B Digital Output for Channel B (D9 B = MSB). to DA to D9A Digital Output for Channel A (D9A = MSB). 7 ENCA Clock Input for Channel A. Rev. C Page 9 of 8

10 AD98 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by db. Aperture Delay The delay between the % point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Crosstalk Coupling onto one channel being driven by a low level signal ( dbfs) when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 8 degrees out of phase. Peak-to-peak differential is computed by rotating the input phase 8 degrees and again taking the peak measurement. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal LSB step. Effective Number of Bits (ENOB) The effective number of bits is calculated from the measured SNR based on the equation ENOB = SNR MEASURED.7 db. ENCODE Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in Logic state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing tench in text. At a given clock rate, these specifications define an acceptable ENCODE duty cycle. Full-Scale Input Power Expressed in dbm. Computed using the following equation: Power Full Scale V = log Full Scale Z INPUT. rms Gain Error Gain error is the difference between the measured and the ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of LSB using a best straight line determined by a least-square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than db below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between the % level crossing of ENCODE A or ENCODE B and the % level crossing of the respective channel s output data bit. Noise (for Any Range Within the ADC) V NOISE = FS Z. dbm SNR dbc Signal dbfs where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value for the particular input level, and Signal is the signal level within the ADC reported in db below full scale. This value includes both thermal and quantization noise. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Rev. C Page of 8

11 AD98 Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set db below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. Reported in dbc (that is, degrades as signal level is lowered) or dbfs (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dbc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Reported in dbc (that is, degrades as signal level is lowered) or in dbfs (always related back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics) reported in dbc. Transient Response Time Transient response is defined as the time it takes for the ADC to reacquire the analog input after a transient from % above negative full scale to % below positive full scale. Out-of-Range Recovery Time Out-of-range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from % above positive full scale to % above negative full scale or from % below negative full scale to % below positive full scale. Rev. C Page of 8

12 AD98 EQUIVALENT CIRCUITS V D V D kω kω A IN kω kω A IN REF kω kω kω -B- - Figure. Analog Input Stage Figure. Reference Inputs V D V D.kΩ ENCODE kω S.kΩ -7 kω - Figure 7. Encode Inputs Figure. S Input V D V D kω OUT S -8 - Figure 8. Reference Output Stage Figure. S Input V DD V D kω kω DX DFS/GAIN kω -9 V REF - Figure 9. Digital Output Stage Figure. DFS/Gain Input Rev. C Page of 8

13 AD98 TYPICAL PERFORMANCE CHARACTERISTICS ENCODE = MSPS A IN =.MHz AT.dBFS SNR =.8dB SINAD =.db H = 9dB H =.8dB ENCODE = MSPS A IN = 9.7MHz AT.dBFS SNR = 8.dB SINAD = 8.dB H = 87dB H = 8dB Figure. FFT: FS = MSPS, AIN =. dbfs, Differential, V p-p Input Range - 9 Figure 7. FFT: FS = MSPS, AIN = 9.7 dbfs, Differential, V p-p Input Range -7 ENCODE = 8MSPS A IN = 9MHz AT.dBFS SNR =.db SINAD =.db H = 7.8dB H =.db ENCODE = MSPS A IN = 7MHz AT.dBFS SNR =.9dB SINAD =.8dB H = 7.dB H = 7.dB Figure. FFT: FS = 8 MSPS, AIN = 9 dbfs, Differential, V p-p Input Range - 9 Figure 8. FFT: FS = MSPS AIN = 7 dbfs, Differential, V p-p Input Range -8 ENCODE = MSPS A IN =.MHz AT.dBFS SNR =.db SINAD =.9dB SFDR = 7dB H = 8.dB H = 79dB ENCODE = MSPS A IN = MHz AT.dBFS SNR =.db SINAD =.9dB H = 7.9dB H = 7.7dB Figure. FFT: FS = MSPS, AIN =. dbfs, Differential, V p-p Input Range - 9. Figure 9. FFT: FS = MSPS, AIN = dbfs; with AD88 Driving ADC Inputs, V p-p Input Range -9 Rev. C Page of 8

14 AD98 ENCODE = MSPS A IN = 8MHz AT.dBFS SNR = 9.dB SINAD = 9.dB H = 87dB H = 8dB ENCODE = MSPS A IN = 8MHz AT.dBFS SNR = 9dB SINAD = 8.8dB H = 78.7dB H = 7.9dB Figure. FFT: FS = MSPS, AIN = 8 dbfs, Differential, V p-p Input Range - 9. Figure. FFT: FS = MSPS, AIN = 8 dbfs, Differential, with AD88 Driving ADC Inputs, V p-p Input Range SECOND SFDR THIRD ENCODE = MSPS A IN =.MHz AT 7dBFS A IN =.MHz AT 7dBFS SFDR = 7dBFS 7 8 A IN FREQUENCY (MHz) Figure. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency ( V p-p, FS = MSPS) - 9. Figure. Two-Tone Intermodulation Distortion (. MHz and. MHz; V p-p, FS = MSPS) THIRD 7 SECOND SFDR ENCODE = 8MSPS A IN = 9.MHz AT 7dBFS A IN =.MHz AT 7dBFS SFDR = 77dBFS 7 8 A IN FREQUENCY (MHz) Figure. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency ( V p-p, FS = 8 MSPS) Figure. Two-Tone Intermodulation Distortion (9. MHz and. MHz; V p-p, FS = 8 MSPS) Rev. C Page of 8

15 AD H V SFDR V H V V DIFFERENTIAL DRIVE ENCODE = MSPS A IN = 8.MHz AT 7dBFS A IN = 9.MHz AT 7dBFS SFDR = 7.9dBFS H V SFDR V H V 7 V SINGLE-ENDED DRIVE 8 8 A IN FREQUENCY (MHz) Figure. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency (FS = MSPS) Figure 9. Two-Tone Intermodulation Distortion (8 MHz, 9 MHz; V p-p, FS = MSPS) SFDR THIRD SECOND ENCODE = MSPS A IN = MHz AT 7dBFS A IN = MHz AT 7dBFS SFDR = 7dBc A IN FREQUENCY (MHz) Figure 7. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency ( V p-p, FS = MSPS) Figure. Two-Tone Intermodulation Distortion ( MHz, MHz; V p-p, FS = MSPS) SFDR 7 SFDR 7 SINAD SNR SINAD 8 ENCODE RATE (MSPS) -8 ENCODE RATE (MHz) Figure 8. SINAD and SFDR vs. Encode Rate (AIN =. MHz, MSPS Grade) AIN =. dbfs Differential, V p-p Analog Input Range ) Figure. SINAD and SFDR vs. Encode Rate (AIN =. MHz, MSPS Grade) AIN =. dbfs Differential, V p-p Analog Input Range Rev. C Page of 8

16 AD SFDR 7 SFDR SINAD SINAD ENCODE POSITIVE PULSEWIDTH (ns) 7 8 Figure. SINAD and SFDR vs. Encode Pulse Width High, AIN =. dbfs Single-Ended, V p-p Analog Input Range MSPS - 8 ENCODE POSITIVE PULSEWIDTH (ns) Figure. SINAD and SFDR vs. Encode Pulse Width High, AIN =. dbfs Single-Ended, V p-p Analog Input Range MSPS -. (ma) 8 IV D IV D / IV DD IV DD (ma) (%)... GAIN GAIN. 8 8 ENCODE CLOCK RATE (MSPS) Figure. IVD and IVDD vs. Encode Rate (AIN =. dbfs), MSPS/ MSPS Grade CI = pf TEMPERATURE ( C) Figure. Gain Error vs. Temperature, AIN =. MHz, MSPS Grade, MSPS Grade, V p-p SFDR SFDR (V).. 8 SNR SINAD..9 SNR 8 TEMPERATURE ( C) Figure. VREF Output Voltage vs. Temperature (ILOAD = μa) - SINAD 8 TEMPERATURE ( C) Figure 7. SNR, SINAD, SFDR vs. Temperature, AIN =. MHz, MSPS Grade, MSPS Grade, V p-p -7 Rev. C Page of 8

17 AD SFDR dbfs. 7 (V)..... SFDR dbc 7dB REF LINE.. SNR dbc I LOAD (ma) Figure 8. VREF vs. ILOAD -8 A IN INPUT LEVEL (dbfs) Figure. SFDR vs. AIN Input Level,. MHz 8 MSPS (LSB) (LSB) CODES -9. CODES - Figure 9. Typical INL Plot,. MHz 8 MSPS Figure. Typical DNL Plot,. MHz 8 MSPS Rev. C Page 7 of 8

18 AD98 THEORY OF OPERATION The AD98 ADC architecture is a bit-per-stage pipeline-type converter utilizing switch capacitor techniques. These stages determine the 7 MSBs and drive a -bit flash. Each stage provides sufficient overlap and error correction, allowing optimization of comparator accuracy. The input buffers are differential, and both sets of inputs are internally biased. This allows the most flexible use of ac-coupled or dc-coupled and differential or single-ended input modes. The output staging block aligns the data, carries out the error correction, and feeds the data to output buffers. The set of output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. There is no discernible difference in performance between the two channels. USING THE AD98 ENCODE INPUT Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer. Any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-todigital output. For that reason, considerable care has been taken in the design of the ENCODE input of the AD98, and the user is advised to give commensurate thought to the clock source. The ENCODE input is fully TTL/CMOS compatible. DIGITAL OUTPUTS The digital outputs are TTL/CMOS compatible for lower power consumption. During power-down, the output buffers transition to a high impedance state. A data format selection option supports either twos complement (set high) or offset binary output (set low) formats. ANALOG INPUT The analog input to the AD98 is a differential buffer. For best dynamic performance, impedance at AIN and AIN should match. Special care was taken in the design of the analog input section of the AD98 to prevent damage and data corruption when the input is overdriven. The nominal input range is. V p-p. Optimum performance is obtained when the part is driven differentially where common-mode noise is minimized and even-order harmonics are reduced. Figure shows an example of the AD98 being driven differentially via a wideband RF transformer for ac-coupled applications. As shown in Figure, applications that require dc-coupled differential drives can be accommodated using the AD88 differential output op amp. ANALOG SIGNAL SOURCE ANALOG SIGNAL SOURCE : Ω Ω A IN AD98 Figure. Using a Wideband Transformer to Drive the AD98 kω kω AV DD VOCM AD88 Ω A IN Ω pf Ω - AD98 A IN A IN - Figure. Using the AD88 to Drive the AD98 Rev. C Page 8 of 8

19 AD98 VOLTAGE REFERENCE A stable and accurate. V voltage reference is built into the AD98 (VREF OUT). Typically, the internal reference is used by strapping Pin (REFINA) and Pin 7 (REFINB) to Pin (REFOUT). The input range for each channel can be adjusted independently by varying the reference voltage inputs applied to the AD98. No appreciable degradation in performance occurs when the reference is adjusted ±%. The full-scale range of the ADC tracks reference voltage, which changes linearly (a % change in VREF results in a % change in full scale). TIMING The AD98 provides latched data outputs, with five pipeline delays. Data outputs are available one propagation delay (tpd) after the rising edge of the encode command (see Figure through Figure ). The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD98. These transients can detract from the dynamic performance of the converter. The minimum guaranteed conversion rate is MSPS. At clock rates below MSPS, dynamic performance degrades. USER SELECT OPTIONS Two pins are available for a combination of operational modes, enabling the user to power down both channels, excluding the reference, or just the B channel. Both modes place the output buffers in a high impedance state. Recovery from a power-down state is accomplished in clock cycles following power-on. The other option allows the user to skew the B channel output data by one-half a clock cycle. In other words, if two clocks are fed to the AD98 and are 8 degrees out of phase, enabling the data align allows Channel B output data to be available at the rising edge of Clock A. If the same encode clock is provided to both channels and the data align pin is enabled, output data from Channel B is 8 degrees out of phase with respect to Channel A. If the same encode clock is provided to both channels and the data align pin is disabled, both outputs are delivered on the same rising edge of the clock. APPLICATION INFORMATION The wide analog bandwidth of the AD98 makes it very attractive for a variety of high performance receiver and encoder applications. Figure shows the dual ADC in a typical low cost I and Q demodulator implementation for cable, satellite, or wireless LAN modem receivers. The excellent dynamic performance of the ADC at higher analog input frequencies and encode rates lets users employ direct IF sampling techniques. IF sampling eliminates or simplifies analog mixer and filter stages to reduce total system cost and power. IF IN 9 VCO BPF BPF AD98 Q ADC I ADC VCO Figure. Typical I/Q Demodulation Scheme - Rev. C Page 9 of 8

20 AD98 AD98/AD988 CUSTOMER PCB BOM Table 8. Bill of Materials No. Qty Reference Designator Device Package Value Comments 9 C, C to C, C, C, C, Capacitor. μf C, C7, C to C, C9 to C C, C Capacitor pf 88 out 7 C C9, C, C7, C8 Capacitor TAJD μf 8 E, E, E, E, E to E, W-HOLE W-HOLE E to E8 H, H, H, H MTHOLE MTHOLE J, J, J, J, J SMA SMA J, J not placed 7 P, P, P -lead power connector Post Z... Wieland 8 P, P, P -lead power connector Detachable... Wieland connector 9 P, P 8-lead rt. angle male TSW--8- Samtec L-D-RA R, R, R, R Resistor Ω R, R, R, R, not placed 9 R, R7, R, R, R, R, R, R, R 7 R, R, R8, R9, R, R, R, R, R, R, R, R7, R, R, R, R, R Resistor Ω R, R, R, R, R, R not placed Resistor Ω R, R not placed R, R8 Resistor Ω R, R8 not placed R, R, R8, R, R9, R Resistor Ω R, R9 not placed R7, R Resistor Ω R9, R7 Resistor kω 7 R, R8, R9, R, R, Resistor kω R to R9, R, R, R 8 T, T Transformer ADT-WT Minicircuits 9 U AD988 or AD98 LQFP8 U, U 7LCX8 U, U SN7VCX8 U7, U8, U9, U Resistor array CTS 7 Ω 787G U, U AD88 op amp P, P are implemented as one physical 8-lead connector SAMTEC TSW--8-L-D-RA. AD988/PCB populated with AD988-, AD98-/PCB populated with AD98-, AD98-/PCB populated with AD98-. To use optional amp place R, R, R, R, R, R9, remove R, R. Rev. C Page of 8

21 AD98 EVALUATION BOARD The AD98/AD988 customer evaluation board offers an easy way to test the AD98 or the AD988. The compatible pinout of the two parts facilitates the use of one PCB for testing either part. The PCB requires power supplies, a clock source, and a filtered analog source for most ADC testing required. POWER CONNECTOR Power is supplied to the board via a detachable -lead power strip. The minimum V supplies required to run the board are VD, VDL, and VDD. To allow the use of the optional amplifier path, ± V supplies are required. ANALOG INPUTS Each channel has an independent analog path that uses a wideband transformer to drive the ADC differentially from a single-ended sine source at the input SMAs. The transformer paths can be bypassed to allow the use of a dc-coupled path using two AD88 op amps with a simple board modification. The analog input should be band-pass filtered to remove any harmonics in the input signal and to minimize aliasing. VOLTAGE REFERENCE The AD98 has an internal. V voltage reference; an external reference for each channel can be employed instead by connecting two external voltage references at the power connector and setting jumpers at E8 and E9. The evaluation board is shipped configured for internal reference mode. CLOCKING Each channel can be clocked by a common clock input at SMA inputs ENCODE A and ENCODE B. The channels can also be clocked independently by a simple board modification. The clock input should be a low jitter sine source for maximum performance. DATA OUTPUTS The data outputs are latched on board by two -bit latches and drive an 8-lead connector, which is compatible with the dualchannel FIFO board that is available from Analog Devices, Inc. This board, together with ADC analyzer software, can greatly simplify ADC testing. DATA FORMAT/GAIN The DFS/GAIN pin can be biased for desired operation at the DFS jumper located at the S, S jumpers. TIMING Timing on each channel can be controlled, if needed, on the PCB. Clock signals at the latches or the data ready signals that go to the output 8-lead connector can be inverted if required. Jumpers also allow for biasing of Pin S and Pin S for powerdown and timing alignment control. TROUBLESHOOTING If the board does not seem to be working correctly, try the following: Verify power at the IC pins. Check that all jumpers are in the correct position for the desired mode of operation. Verify that VREF is at. V. Try running encode clock and analog inputs at low speeds ( MSPS/ MHz) and monitor the LCX8 outputs, DAC outputs, and ADC outputs for toggling. The AD98 evaluation board is provided as a design example for customers of Analog Devices. Analog Devices makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose. Rev. C Page of 8

22 AD98 V +V C7 µf V +V V D V DD V DL V REF A V REF B + C8 µf P P P7 C µf C7 µf V D V DD V DL C8 µf C9 µf C µf H MTHOLE H MTHOLE H MTHOLE H MTHOLE ENCA D9A (MSB) D8A D7A DA VD VDD - DA DA DA DA C7 C8 D A D A D B D B C C V DD V DD C V D VDD VD ENCB (MSB) D9B D8B D7B DB DB DB DB DB R C C C9 R Ω R8 Ω REFOUT VD E8 E E VD E E7 E E VREFA E VD E9 E E E E8 E7 E A IN A A IN A DFS/GAIN REF IN A REF OUT REF IN B S S A IN B A IN B C C VD ENCA VDD D9A D8A D7A DA 8 7 DA DA DA DA AD98 U D A D A V DD V D V D V DD D B D B VD ENCB VDD D9B D8B D7B DB DB DB DB DB A B Y A B VCC B A Y B ENCXA ENCA E E ENCXA VDL TIEA Y A 9 7 Y 8 R R R9 kω C ENCODE A J VDL R kω R R kω U SN7VCX8 C R R9 DRA VDL CLKLATA R kω R7 kω E E **DUT CLOCK SELECTABLE** **TO BE DIRECT OR BUFFERED** E E VDL VDL ENCODE B J R Ω TIEB C C C9 VDL ENCXB ENCB R R kω R kω VDL R ENCXB E VDL E R9 kω C 8 9 U SN7VCX8 Y A B Y A Y B A Y B B VCC A 7 R **DUT CLOCK SELECTABLE** **TO BE DIRECT OR BUFFERED** R CLKLATB DRB R8 kω R kω E E7 E E8 VDL VDL TO TIE CLOCKS TOGETHER ENC A ENC B R8 J R TIEA R AMPOUTA R R R Ω C R J AIN A C AMPINA R R Ω T TIEB C7 AMPOUTAB R SINGLE-ENDED C R SINGLE-ENDED AMPOUTBB R Ω V DL V REF B V DD V REF A V D AMPINB R R Ω C P P P J AIN B AMPOUTB R7 REF IN A REF IN B Figure. PCB Schematic R C C R7 T Rev. C Page of 8

23 AD98 - OPAMP INPUT OFF PIN ONE OF TRANSFORMER AMPINA R R7 Ω AD88 +V R V C 8 7 +IN NC V OUT IN VOCM V+ +OUT U +V C R9 kω R kω R C pf R AMPOUTAB AMPOUTA AMPINB R9 R Ω R V C 8 7 +IN NC V AD88 OUT IN VOCM V+ +OUT U +V C +V R7 kω R8 kω R C pf R AMPOUTB AMPOUTBB NC = NO CONNECT R8 R D9A D8A D7A DA DA DA 7 DA 7 8 DA 8 9 DA 9 DA DB DB DB DB DB DB 7 DB 7 8 D7B 8 9 D8B 9 D9B U7 CTS VALUE = U8 CTS VALUE = D9M D8M D7M DM DM DM DM DM DM DM DN DN DN DN DN DN DN D7N D8N D9N D9M D8M D7M DM DM DM 7 DM 8 DM 9 DM DM DN DN DN DN DN DN 7 DN 8 D7N 9 D8N D9N U 7LCX8 OE VCC X Y X Y X Y X Y X Y X Y X Y X7 Y7 X8 Y8 X9 Y9 CLK U 7LCX8 OE VCC X Y X Y X Y X Y X Y X Y X Y X7 Y7 X8 Y8 X9 Y9 CLK C VDL D9X D8X D7X DX DX DX DX DX DX DX CLKLATA D9X D8X D7X DX DX DX DX 7 DX 8 DX 9 DX C VDL DY DY DY DY DY DY DY D7Y D8Y DY DY DY DY DY DY DY 7 D7Y 8 D8Y 9 D9Y D9Y CLKLATB U9 CTS VALUE = U CTS VALUE = D9P D8P D7P DP DP DP DP DP DP DP DQ DQ DQ DQ DQ DQ DQ D7Q D8Q D9Q P HEADER P HEADER DRA D9P D8P D7P DP DP DP DP DP DP DP DRB D9Q D8Q D7Q DQ DQ DQ DQ DQ DQ DQ Figure. PCB Schematic (Continued) Rev. C Page of 8

24 AD Figure 7. Top Silkscreen Figure. Split Power Plane -8 - Figure 8. Top Routing Figure. Bottom Routing Figure 9. Ground Plane -9 Figure. Bottom Silkscreen - Rev. C Page of 8

25 AD98 OUTLINE DIMENSIONS.7... MAX SQ SEATING PLANE VIEW A ROTATED 9 CCW COPLANARITY VIEW A. BSC LEAD PITCH PIN TOP VIEW (PINS DOWN) COMPLIANT TO JEDEC STANDARDS MS--BBC Figure. 8-Lead Low Profile Quad Flat Package [LQFP] (ST-8) Dimensions shown in millimeters SQ.8 7-A ORDERING GUIDE Model Temperature Range Package Description Package Option AD98BST- C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BST-RL C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BSTZ- C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BSTZ-RL C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BST- C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BST-RL C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BSTZ- C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BSTZ-RL C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BST-8 C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BST-RL8 C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BSTZ-8 C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BSTZ-RL8 C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BST- C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BST-RL C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BSTZ- C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98BSTZ-RL C to +8 C 8-Lead Low Profile Quad Flat Pack (LQFP) ST-8 AD98-PCB Evaluation Board (Supports -/- Grade) AD98-PCB Evaluation Board (Supports -8/- Grade) Z = Pb-free part. Rev. C Page of 8

26 AD98 NOTES Rev. C Page of 8

27 AD98 NOTES Rev. C Page 7 of 8

28 AD98 NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C--/(C) Rev. C Page 8 of 8