8-Bit, 250 MSPS 3.3 V A/D Converter AD9481

Transcription

1 FEATURES DNL = ±0. LSB INL = ±0. LSB Single. V supply operation (.0 V to. V) Power dissipation of 9 mw at 0 MSPS V p-p analog input range Internal.0 V reference Single-ended or differential analog inputs De-multiplexed CMOS outputs Power-down mode Clock duty cycle stabilizer VIN+ VIN DS+ DS CLK+ CLK -Bit, 0 MSPS. V A/D Converter AD9 FUNCTIONAL BLOCK DIAGRAM VREF SENSE REFERENCE T AND H CLOCK MGMT A DR DRVDD -BIT ADC PIPELINE CORE AD9 PORT A PORT B D7A TO D0A D7B TO D0B DCO+ DCO APPLICATIONS Digital oscilloscopes Instrumentation and measurement Communications Point-to-point radios Digital predistortion loops PDWN LOGIC S Figure GENERAL DESCRIPTION The AD9 is an -bit, monolithic analog-to-digital converter (ADC) optimized for high speed and low power consumption. Small in size and easy to use, the product operates at a 0 MSPS conversion rate, with excellent linearity and dynamic performance over its full operating range. To minimize system cost and power dissipation, the AD9 includes an internal reference and track-and-hold circuit. The user only provides a. V power supply and a differential encode clock. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS-compatible with an option of twos complement or binary output format. The output data bits are provided in an interleaved fashion along with output clocks that simplifies data capture. The AD9 is available in a Pb-free, -lead, surface-mount package (TQFP-) specified over the industrial temperature range ( 0 C to + C). PRODUCT HIGHLIGHTS. Superior linearity. A DNL of ±0. makes the AD9 suitable for many instrumentation and measurement applications. Power-down mode. A power-down function may be exercised to bring total consumption down to mw.. De-multiplexed CMOS outputs allow for easy interfacing with low cost FPGAs and standard logic. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 90, Norwood, MA 00-90, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS DC Specifications... Digital Specifications... AC Specifications... Switching Specifications... Timing Diagram... 7 Absolute Maximum Ratings... Explanation of Test Levels... ESD Caution... Pin Configuration and Function Descriptions... 9 Terminology... 0 Typical Performance Characteristics... Equivalent Circuits... Applications... 7 Analog Inputs... 7 Voltage Reference... 7 Clocking the AD DS Inputs... 9 Digital Outputs... 0 Data Clock Out... 0 Power-Down Input... 0 AD9 Evaluation Board... Power Connector... Analog Inputs... Gain... Optional Operational Amplifier... Clock... Optional Clock Buffer... DS... Optional TAL... Voltage Reference... Data Outputs... Evaluation Board Bill of Materials (BOM)... PCB Schematics... PCB Layers... Outline Dimensions... Ordering Guide... Interleaving Two AD9s... 0 REVISION HISTORY 0/0 Revision 0: Initial Version Rev. 0 Page of

3 DC SPECIFICATIONS AD9 =. V, DRVDD =. V; TMIN = 0 C, TMA = + C, AIN = dbfs, full scale =.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table. AD9-0 Parameter Temp Test Level Min Typ Max Unit RESOLUTION Bits ACCURACY No Missing Codes Full VI Guaranteed Offset Error C I 0 0 mv Gain Error C I.0.0 % FS Differential Nonlinearity (DNL) Full VI 0. ±0. 0. LSB Integral Nonlinearity (INL) Full VI 0.9 ± LSB TEMPERATURE DRIFT Offset Error Full V 0 µv/ C Gain Error Full V 0.0 % FS/ C Reference Full V ±0.0 mv/ C REFERENCE Internal Reference Voltage Full VI V Output Current C IV. ma IVREF Input Current C I 00 µa ISENSE Input Current C I 0 µa ANALOG INPUTS (VIN+, VIN ) Differential Input Voltage Range Full V V p-p Common-Mode Voltage Full VI..9. V Input Resistance Full VI. 0. kω Input Capacitance C V pf Analog Bandwidth, Full Power C V 70 MHz POWER SUPPLY Full IV.0.. V DRVDD Full IV.0.. V Supply Currents I Full VI ma IDRVDD Full VI 9. ma Power Dissipation C V 9 mw Power-Down Dissipation C V 7 mw Power Supply Rejection Ratio (PSRR) C V. mv/v Gain error and gain temperature coefficients are based on the ADC only (with a fixed V external reference and V p-p input range). Internal reference mode; SENSE = A. External reference mode; VREF driven by external.0 V reference; SENSE =. In FS = V, both analog inputs are 00 mv p-p and out of phase with each other. Supply current measured with rated encode and a 0 MHz analog input. Power dissipation measured with dc input, see the T erminology section for power vs. clock rate. Rev. 0 Page of

4 DIGITAL SPECIFICATIONS =. V, DRVDD =. V; TMIN = 0 C, TMA = + C, AIN = dbfs, full scale =.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table. AD9-0 Parameter Temp Test Level Min Typ Max Unit CLOCK AND DS INPUTS (CLK+, CLK, DS+, DS ) Differential Input Full IV 00 mv p-p Common-Mode Voltage Full VI... V Input Resistance Full VI...0 kω Input Capacitance C V pf LOGIC INPUTS (PDWN, S) Logic Voltage Full IV.0 V Logic 0 Voltage Full IV 0. V Logic Input Current Full VI ±0 µa Logic 0 input Current Full VI 0 µa Input Resistance C V 0 kω Input Capacitance C V pf DIGITAL OUTPUTS Logic Voltage Full VI DRVDD 0.0 mv Logic 0 Voltage Full VI 0.0 V Output Coding Full IV Twos complement or binary The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK ± <. V. Capacitive loading only. Rev. 0 Page of

5 AC SPECIFICATIONS AD9 =. V, DRVDD =. V; TMIN = 0 C, TMA = + C, AIN = dbfs, full scale =.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table. AD9-0 Parameter Temp Test Level Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fin = 9.7 MHz C V db fin = 70. MHz C I..7 db SIGNAL-TO-NOISE AND DISTORTION (SINAD) fin = 9.7 MHz C V.9 db fin = 70. MHz C I..7 db EFFECTIVE NUMBER OF BITS (ENOB) fin = 9.7 MHz C V 7. Bits fin = 70. MHz C I Bits WORST SECOND OR THIRD HARMONIC DISTORTION fin = 9.7 MHz C V. dbc fin = 70. MHz C I. dbc WORST OTHER fin = 9.7 MHz C V dbc fin = 70. MHz C I. dbc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fin = 9.7 MHz C V. dbc fin = 70. MHz C I. dbc TWO-TONE INTERMODULATION DISTORTION (IMD) fin = 9. MHz, fin = 70. MHz C V.9 dbc DC and Nyquist bin energy ignored. Rev. 0 Page of

6 SWITCHING SPECIFICATIONS =. V, DRVDD =. V; differential encode input, duty cycle stabilizer enabled, unless otherwise noted. Table. AD9-0 Parameter Temp Test Level Min Typ Max Unit CLOCK Maximum Conversion Rate Full VI 0 MSPS Minimum Conversion Rate Full IV 0 MSPS Clock Pulse-Width High (teh) Full IV. ns Clock Pulse-Width Low (tel) Full IV. ns DS Input Setup Time (tsds) Full IV 0. ns DS Input Hold Time (thds) Full IV 0. ns OUTPUT PARAMETERS Valid Time (tv) Full VI. ns Propagation Delay (tpd) Full VI. ns Rise Time (tr) 0% to 90% Full V 70 ps Fall Time (tf) 0% to 90% Full V 0 ps DCO Propagation Delay (tcpd) Full VI..9. ns Data-to-DCO Skew (tpd tcpd) Full VI ns A Port Data to DCO Rising (tska) Full IV ns B Port Data to DCO+ Rising (tskb) Full IV ns Pipeline Latency (A, B) Full IV Cycles APERTURE Aperture Delay (ta) C V. ns Aperture Uncertainty (Jitter) C V 0. ps rms OUT-OF-RANGE RECOVERY TIME C V Cycle CLOAD equals pf maximum for all output switching specifications. Valid time is approximately equal to minimum tpd. TCPD equals clock rising edge to DCO (+ or ) rising edge delay. Data changing to (DCO+ or DCO ) rising edge delay. TSKA, TSKB are both clock rate dependent delays equal to TCYCLE (Data to DCO skew). Rev. 0 Page of

7 TIMING DIAGRAM VIN N N t A N+ N+9 N+0 N+ N+7 CYCLES CLK+ t EH t EL /f S CLK DS+ t HDS DS t SDS INTERLEAVED DATA OUT t PD t V PORT A STATIC INVALID N D7A TO D0A PORT B D7B TO D0B DCO+ DCO STATIC INVALID INVALID N+ t SKA t t SKB CPD STATIC Figure. Timing Diagram Rev. 0 Page 7 of

8 ABSOLUTE MAIMUM RATINGS Thermal impedance (θja) =. C/W (-layer PCB). EPLANATION OF TEST LEVELS Table. Parameter Min. Rating Max. Rating ELECTRICAL (With respect to A) 0. V +.0 V DRVDD 0. V +.0 V (With respect to DR) A (With respect to DR) 0. V +0. V Digital I/0 0. V DRVDD + 0. V (With respect to DR) Analog Inputs 0. V + 0. V (With respect to A) ENVIRONMENTAL Operating Temperature 0 C + C Junction Temperature 0 C Storage Temperature 0 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table. Level Description I 00% production tested. II 00% production tested at C and guaranteed by design and characterization at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 00% production tested at C and guaranteed by design and characterization for industrial temperature range. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 Page of

9 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK+ CLK PIN SENSE A A DRVDD DR 0 9 PDWN S D7A (MSB) 7 7 DR DA D7B (MSB) DA 9 DB DA 0 DB DA DB DA DA D0A (LSB) DR DCO DCO+ DRVDD D0B (LSB) DB DB DB DS+ DS S A VIN+ VIN A A VREF AD9 TOP VIEW (Not to Scale) Figure. Pin Configuration Table 7. Pin Function Descriptions Pin No. Name Description CLK+ Input Clock True CLK Input Clock Complement. V Analog Supply A Analog Ground DRVDD. V Digital Output Supply DR Digital Ground 7 D7A Data Output Bit 7 Channel A (MSB) DA Data Output Bit Channel A 9 DA Data Output Bit Channel A 0 DA Data Output Bit Channel A DA Data Output Bit Channel A DA Data Output Bit Channel A DA Data Output Bit Channel A D0A Data Output Bit 0 Channel A (LSB) DR Digital Ground DCO Data Clock Output Complement 7 DCO+ Data Clock Output True DRVDD. V Digital Output Supply 9 D0B Data Output Bit 0 Channel B (LSB) 0 DB Data Output Bit Channel B DB Data Output Bit Channel B DB Data Output Bit Channel B DB Data Output Bit Channel B DB Data Output Bit Channel B Pin No. Name Description DB Data Output Bit Channel B D7B Data Output Bit 7 Channel B (MSB) 7 DR Digital Ground S Data Format Select and Duty Cycle Stabilizer Select 9 PDWN Power-Down Selection 0. V Analog Supply. V Analog Supply A Analog Ground SENSE Reference Mode Selection VREF Voltage Reference Input/Output A Analog Ground. V Analog Supply 7 A Analog Ground VIN Analog Input Complement 9 VIN+ Analog Input True 0 A Analog Ground. V Analog Supply S DCO Enable Select (Tie to for DCO Active) DS Data Sync Complement (If Unused, Tie to DRVDD) DS+ Data Sync True (If Unused, Tie to D) Rev. 0 Page 9 of

10 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by db. Aperture Delay The delay between the 0% point of the rising edge of the encode command and the instant the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse-Width/Duty Cycle Pulse-width high is the minimum amount of time that the clock pulse should be left in a Logic state to achieve rated performance; pulse-width low is the minimum time clock pulse should be left in a low state. See timing implications of changing teh in the Clocking the AD9 section. At a given clock rate, these specifications define an acceptable clock duty cycle. Crosstalk Coupling onto one channel being driven by a low level ( 0 dbfs) signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 0 out of phase. Peak-to-peak differential is computed by rotating the inputs phase 0 and taking the peak measurement again. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal LSB step. Effective Number of Bits (ENOB) ENOB is calculated from the measured SINAD based on the equation (assuming full-scale input) ENOB = SINAD MEASURED.0.7 db Full-Scale Input Power Expressed in dbm. Computed using the following equation Power FULLSCALE = V log FULLSCALE Z INPUT rms Gain Error Gain error is the difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of LSB using a best straight line determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than db below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK and the time when all output data bits are within valid logic levels. Noise (for Any Range within the ADC) This value includes both thermal and quantization noise. V where: noise = FS Z Z is the input impedance. dbm SNRdBc Signal 0 dbfs FS is the full scale of the device for the frequency in question. SNR is the value for the particular input level. Signal is the signal level within the ADC reported in db below full scale. Rev. 0 Page 0 of

11 Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set db below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in dbc (degrades as signal level is lowered) or dbfs (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, in dbc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It also may be reported in dbc (degrades as signal level is lowered) or in dbfs (always relates back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic), reported in dbc. Transient Response Time The time it takes for the ADC to reacquire the analog input after a transient from 0% above negative full scale to 0% below positive full scale. Out-of-Range Recovery Time This is the time it takes for the ADC to reacquire the analog input after a transient from 0% above positive full scale to 0% above negative full scale, or from 0% below negative full scale to 0% below positive full scale. Rev. 0 Page of

12 TYPICAL PERFORMANCE CHARACTERISTICS, DRVDD =. V, T = C, AIN differential drive, FS =, internal reference mode, unless otherwise noted SNR =.db H =.dbc H =.dbc SFDR =.dbc SNR =.db H = 7.9dBc H =.dbc SFDR = 9.dBc (db) 0 (db) (MHz) (MHz) Figure. FFT: fs = 0 MSPS, AIN = 0. dbfs Figure 7. FFT: fs = 0 MSPS, AIN = 70 dbfs (db) (db) SNR =.db H =.dbc H =.dbc SFDR =.dbc (MHz) Figure. FFT: fs = 0 MSPS, AIN = 70 dbfs SNR =.9dB H =.dbc H = 70.dBc SFDR =.9dBc (MHz) Figure. FFT: fs = 0 MSPS, AIN = 70 dbfs, Single-Ended Input (db) (db) H SFDR SNR SINAD A IN (MHz) H Figure. Analog Input Frequency Sweep, AIN = dbfs, FS = V, fs = 0 MSPS SFDR H SNR SINAD A IN (MHz) Figure 9. Analog Input Frequency Sweep, AIN = dbfs, FS = 0.7 V, fs = 0 MSPS, External VREF Mode H Rev. 0 Page of

13 SFDR 0 I (db) 0 CURRENT (ma) SNR SINAD SAMPLE CLOCK (MHz) Figure 0. SNR, SINAD, SFDR vs. Sample Clock Frequency, AIN = 70 db I DRVDD SAMPLE CLOCK (MSPS) Figure. I and IDRVDD vs. Clock Rate, CLOAD = pf AIN = 70 dbfs SFDR (dbfs) 9 7 DCS ON 0 (db) SFDR (dbc) 0dB REFERENCE LINE ANALOG INPUT DRIVE LEVEL (dbfs) 00-0 (db) DCS OFF CLOCK POSITIVE DUTY CYCLE (%) 00-0 Figure. SFDR vs. AIN Input Level; AIN = 70 0 MSPS Figure. SNR, SINAD vs. Clock Pulse-Width High, AIN = 70 dbfs, 0 MSPS, DCS On/Off 0 0 F, F = 7dBFS F F =.9dBc F F =.9dBc SNR 70 (db) SNR, SINAD (db).0 SINAD SFDR SFDR (dbc) (MHz) ETERNAL VREF VOLTAGE (V) 00-0 Figure. Two-Tone Intermodulation Distortion (9. MHz and 70. MHz; fs = 0 MSPS) Figure. SNR, SINAD, and SFDR vs. VREF in External Reference Mode, AIN = 70 dbfs, 0 MSPS Rev. 0 Page of

14 FS = V ETERNAL REFERENCE SFDR GAIN ERROR (%) (db) 0.0. FS = V INTERNAL REFERENCE TEMPERATURE ( C) SINAD (V) SNR Figure. Full-Scale Gain Error vs. Temperature, AIN = dbfs, 0 MSPS Figure 9. SNR, SINAD, and SFDR vs. Supply Voltage, AIN = 70. dbfs, 0 MSPS 70 0 SFDR (db) LSB 0 0 SINAD TEMPERATURE ( C) CODE Figure 7. SINAD, SFDR vs. Temperature, AIN = 70 dbfs, 0 MSPS Figure 0. Typical DNL Plot, AIN = dbfs, 0 MSPS CHANGE IN VREF (%) LSB (V) Figure. VREF Sensitivity to CODE Figure. Typical INL Plot, AIN = dbfs, 0 MSPS 00-0 Rev. 0 Page of

15 0. T PD _F DELAY CHANGE (ps) T CPD _F T CPD _R 0. T PD _R TEMPERATURE ( C) 00-0 Figure. Propagation Delay Sensitivity vs. Temperature Rev. 0 Page of

16 EQUIVALENT CIRCUITS.7kΩ.7kΩ VIN+ 0Ω 0Ω VIN PDWN kω.pf kω.pf 0kΩ 00-0 Figure. Analog Inputs kω kω CLK+ 0Ω 0kΩ 0Ω 0kΩ CLK 00-0 Figure. Clock Inputs VDD 0kΩ S Figure. Power-Down Input DRVDD Figure 7. Data, DCO Outputs Figure. S Input Rev. 0 Page of

17 APPLICATIONS The AD9 uses a. bit per stage architecture. The analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the -bit core. For ease of use, the part includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are CMOS-compatible. ANALOG INPUTS The analog input to the AD9 is a differential buffer. For best dynamic performance, impedances at VIN+ and VIN should match. Optimal performance is obtained when the analog inputs are driven differentially. SNR and SINAD performance can degrade if the analog input is driven with a single-ended signal. The analog inputs self-bias to approximately.9 V; this common-mode voltage can be externally overdriven by approximately ±00 mv if required. A wideband transformer, such as the Mini-Circuits ADT-WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Note that the filter and center-tap capacitor on the secondary side is optional and dependent on application requirements. An RC filter at the secondary side helps reduce any wideband noise getting aliased by the ADC. 9.9Ω 0.µF (R, C OPTIONAL) Ω 0pF Ω VIN+ AD9 VIN A Figure. Driving the ADC with an RF Transformer For dc-coupled applications, the AD/AD9 or AD can serve as a convenient ADC driver, depending on requirements. Figure 9 shows an example with the AD. The AD9 PCB has an optional AD on board, as shown in Figure 9 and Figure 0. The AD typically yields better performance for frequencies greater than 0 MHz to 0 MHz. The AD9 s linearity and SFDR start to degrade at higher analog frequencies (see the Typical Performance Characteristics section). For higher frequency applications, the AD90 with LVDS outputs and superior AC performance should be considered µF.kΩ 9.9Ω kω 99Ω Ω 99Ω AD 99Ω Ω 0pF Ω VIN+ AD9 VIN Figure 9. Driving the ADC with the AD A The AD9 can be easily configured for different full-scale ranges. See the Voltage Reference section for more information. Optimal performance is achieved with a V p-p analog input. SENSE = VIN+ 00mV.0V.0V VIN DIGITALOUT = ALL s VOLTAGE REFERENCE Figure 0. Analog Input Full Scale DIGITALOUT = ALL 0s A stable and accurate.0 V reference is built into the AD9. Users can choose this internal reference or provide an external reference for greater accuracy and flexibility. Figure shows the typical reference variation with temperature. Table summarizes the available reference configurations. 0µF + 0.µF VIN+ VIN VREF 7kΩ SELECT LOGIC ADC CORE SENSE 7kΩ 0.V 00-0 Figure. Internal Reference Equivalent Circuit Rev. 0 Page 7 of

18 Fixed Reference The internal reference can be configured for a differential span of V p-p (see Figure ). It is recommended to place a 0. µf capacitor as close as possible to the VREF pin; a 0 µf capacitor is also required (see the PCB layout for guidance). If the internal reference of the AD9 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure depicts how the internal reference voltage is affected by loading VREF 0µF 0.µF SENSE Figure. Internal Fixed Reference ( V p-p) 00-0 VREF (V) % CHANGE IN VREF VOLTAGE TEMPERATURE ( C) Figure. Typical Reference Variation with Temperature IREF (ma) Figure. Internal VREF vs. Load Current 00-0 Table. Reference Configurations SENSE Voltage Resulting VREF Reference Differential Span N/A (external reference input) External external reference voltage 0. V (Self-Biased) 0. ( + R/R) V Programmable VREF (0.7 V p-p to. V p-p) A to 0. V.0 V Internal fixed V p-p Rev. 0 Page of

19 External Reference An external reference can be used for greater accuracy and temperature stability when required. The gain of the AD9 can also be varied using this configuration. A voltage output DAC can be used to set VREF, providing for a means to digitally adjust the full-scale voltage. VREF can be externally set to voltages from 0.7 V to. V; optimum performance is typically obtained at VREF = V. (See the Typical Performance Characteristics section.) MAY REQUIRE RC FILTER ETERNAL REFERENCE OR DAC INPUT VREF SENSE Figure. External Reference Programmable Reference The programmable reference can be used to set a differential input span anywhere between 0.7 V p-p and. V p-p by using an external resistor divider. The SENSE pin self-biases to 0. V, and the resulting VREF is equal to 0. ( + R/R). It is recommended to keep the sum of R + R 0 kω to limit VREF loading (for VREF =. V, set R equal to 7 kω and R equal to. kω). 0µF 0.µF CLOCKING THE AD9 R R VREF SENSE Figure. Programmable Reference Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. Considerable care has been taken in the design of the CLOCK input of the AD9, and the user is advised to give commensurate thought to the clock source. The AD9 has an internal clock duty cycle stabilization circuit that locks to the rising edge of CLOCK and optimizes timing internally for sample rates between 00 MSPS and 0 MSPS. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter on the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 70 MHz nominally. The loop has a time constant associated with it that needs to be considered in applications where the clock rate can change dynamically, requiring a wait time of µs after a dynamic clock frequency increase before valid data is available. The clock duty cycle stabilizer can be disabled at Pin (S). The clock inputs are internally biased to. V (nominal) and support either differential or single-ended signals. For best dynamic performance, a differential signal is recommended. An MC00LVEL performs well in the circuit to drive the clock inputs (ac coupling is optional). If the clock buffer is greater than two inches from the ADC, a standard LVPECL termination may be required instead of the simple pull-down termination shown in Figure 7. DS INPUTS PECL GATE 0kΩ 0.µF 0.µF 0kΩ Figure 7. Clocking the AD9 AD9 CLK+ CLK The data sync inputs (DS+, DS ) can be used in applications which require that a given sample appear at a specific output port (A or B) relative to a given external timing signal. The DS inputs can also be used to synchronize two or more ADCs in a system to maintain phasing between Ports A and B on separate ADCs (in effect, synchronizing multiple DCO outputs). The DS inputs are internally biased to. V (nominal) and support either differential or single-ended signals. When DS+ is held high (DS low), the ADC data outputs and DCO outputs do not switch and are held static. Synchronization is accomplished by the assertion (falling edge) of DS+ within the timing constraints tsds and thds, relative to a clock rising edge. (On initial synchronization, thds is not relevant.) If DS+ falls within the required setup time (tsds) before a given clock rising edge N, the analog value at that point in time is digitized and available at Port A, eight cycles later in interleaved mode. The next sample, N +, is sampled by the next rising clock edge and available at Port B, eight cycles after that clock edge. Driving each ADC s DS inputs by the same sync signal accomplishes synchronization between multiple ADCs. In applications which require synchronization, one-shot synchronization is recommended. An easy way to accomplish synchronization is by a one-time sync at power-on reset Rev. 0 Page 9 of

20 Table 9. S Voltage Levels S Voltage Data Format Duty Cycle Stabilizer (0.9 ) Offset binary Disabled (/ ) ± (0. ) Offset binary Enabled (/ ) ± (0. ) Twos complement Enabled A (0. ) Twos complement Disabled DIGITAL OUTPUTS The CMOS digital outputs are TTL-/CMOS-compatible for lower power consumption. The outputs are biased from a separate supply (DRVDD), allowing easy interface to external logic. The outputs are CMOS devices that swing from ground to DRVDD (with no dc load). It is recommended to minimize the capacitive load the ADC drives by keeping the output traces short (< inch, for a total CLOAD < pf). When operating in CMOS mode, it is also recommended to place low value series damping resistors on the data lines close to the ADC to reduce switching transient effects on performance. Table 0. Output Coding (FS = V) Code (VIN+) (VIN ) Offset Binary Twos Complement > +0. V V V V V V V V V < 0. V INTERLEAVING TWO AD9s Instrumentation applications may prefer to interleave (or pingpong) two AD9s to achieve twice the sample rate, or 00 MSPS. In these applications, it is important to match the gain and offset of the two ADCs. Varying the reference voltage allows the gain of the ADCs to be adjusted; external dc offset compensation can be used to reduce offset mismatch between two ADCs. The sampling phase offset between the two ADCs is extremely important as well and requires very low skew between clock signals driving the ADCs (< ps clock skew for a 00 MHz analog input frequency). DATA CLOCK OUT A data clock is available at DCO+ and DCO. These clocks can facilitate latching off-chip, providing a low skew clocking solution. The on-chip delay of the DCO clocks tracks with the on-chip delay of the data bits, (under similar loading) such that the variation between tpd and tcpd is minimized. It is recommended to keep the trace lengths on the data and DCO pins matched and inches maximum. A series damping resistor at the clock outputs is also recommended. The DCO outputs can be disabled and placed in a high impedance state by tying S to ground (tie to for DCO active). Switching both into and out of high impedance is accomplished in ns from S switching. POWER-DOWN INPUT The ADC can be placed into a low power state by setting the PDWN pin to. Time to go into (or come out of) power down equals 0 ns typically from PDWN switching. Rev. 0 Page 0 of

21 AD9 EVALUATION BOARD The AD9 evaluation board offers an easy way to test the device. It requires a clock source, an analog input signal, and a. V power supply. The clock source is buffered on the board to provide the clocks for the ADC and a data-ready signal. The digital outputs and output clocks are available at an 0-pin output connector, P, P. (Note that P, P are represented schematically as two 0-pin connectors, and this connector is implemented as one 0-pin connector on the PCB.) The board has several different modes of operation and is shipped in the following configuration: Offset binary Internal voltage reference POWER CONNECTOR Power is supplied to the board via two detachable -pin power strips. Table. Power Connector Terminal Comments VDL (. V). V DRVDD. V VCTRL. V Op amp, ext. ref Output supply for external latches and data ready clock buffer ~ 0 ma Analog supply for ADC ~ 0 ma Output supply for ADC ~ 0 ma Supply for support clock circuitry ~ 0 ma Optional supply for op amp and ADR0 reference, DRVDD, VDL, and VCTRL are the minimum required power connections. ANALOG INPUTS The evaluation board accepts a 700 mv p-p analog input signal centered at ground at SMB Connector J. This signal is terminated to ground through 0 Ω by R. The input can be alternatively terminated at the T transformer secondary by R and R. T is a wideband RF transformer that provides the single-ended-to-differential conversion, allowing the ADC to be driven differentially, minimizing even-order harmonics. An optional transformer, T, can be placed if desired (remove T, as shown in Figure 9 and Figure 0). The analog signal can be low-pass filtered by R, C and R, C9 at the ADC input. GAIN Full scale is set by the sense jumper. This jumper applies a bias to the SENSE pin to vary the full-scale range; the default position is SENSE = ground, setting the full scale to V p-p. OPTIONAL OPERATIONAL AMPLIFIER The PCB has been designed to accommodate an optional AD op amp that can serve as a convenient solution for dccoupled applications. To use the AD op amp, remove R9, R, and C. Populate R, R7, and R with Ω resistors, and populate C, C, C, C, C9, and C0 with 0. µf capacitors. Populate R, R0, and R with 0 Ω resistors, and R and R with kω resistors. Populate R with a. kω resistor and R with a 00 Ω resistor. Populate R7 with a 0 kω resistor. CLOCK The clock input is terminated to ground through 0 Ω at SMA Connector J. The input is ac-coupled to a high speed differential receiver (LVEL) that provides the required low jitter, fast edge rates needed for best performance. J input should be > 0. V p-p. Power to the LVEL is set to VCTRL (default) or by jumper placement at the device. OPTIONAL CLOCK BUFFER The PCB has been designed to accommodate the SNLVDS line driver. The SNLVDS is used as a high speed LVDS-level optional encode clock. To use this clock, please remove C, C, and C. Place 0. µf capacitors on C, C, and C. Place a 0 Ω resistor on R, and place a 00 Ω resistor on R. Place a 0 Ω resistor on both R9 and R. For best results using the line driver, J input should be >. V p-p. DS The DS inputs are available on the PCB at J and J. If driving DS+ externally, place a 0 Ω resistor at C and remove R. Rev. 0 Page of

22 OPTIONAL TAL The PCB has been designed to accommodate an optional crystal oscillator that can serve as a convenient clock source. The footprint can accept both through-hole and surface-mount devices, including Vectron O-00 and Vectron VCC family oscillators. VCC OUT VCC Figure. TAL Footprint OUT To use either crystal, populate C and C0 with 0. µf capacitors. Populate R and R9 with 0 Ω resistors. Place R0, R, R9, and R0 with kω resistors. Remove C and C. If the Vectron VCC family crystal is being used, populate R7 with a 0 Ω resistor. If using the O-00 crystal, place jumper E or E to E. VOLTAGE REFERENCE The AD9 has an internal V reference mode. The ADC uses the internal V reference as the default when sense is set to ground. An optional on-board external.0 V reference (ADR0) can be used by setting the sense jumper to, by placing a jumper on E to E, and by placing a 0 Ω resistor on R. When using an external programmable reference, (R0, R0) remove the sense jumper. DATA OUTPUTS The ADC outputs are buffered on the PCB by LVT7 latches on the data outputs. The latch outputs have series terminating resistors at the output pins to minimize reflections. Rev. 0 Page of

23 EVALUATION BOARD BILL OF MATERIALS (BOM) Table. No. Quantity Reference Designator Device Package Value AD9 C to C, C0 to C, C to C, Capacitors µf C7 to C9, C to C9, C, C to C9 C Capacitor Tantalum () 0 µf C to C Capacitors Tantalum (0) 0 µf J to J SMA SMA Degrees P, P to P -pin power connectors Post Z...0 P, P to P -pin power connectors Detachable connector P, P 0-pin connectors Connector TSW-0-0-L-D-RA 7 R, R, R9, R, R7, R, R Resistors 00 0 Ω 9 R to R, R to R9, R, R Resistors Ω 0 7 R, R to R, R, R Resistors 00 kω R, R Resistors 00 0 Ω R, R Resistors 00 0 Ω R, R Resistors 00 Ω R9, R Resistors Ω R, R7 Resistors 00 0 kω R Resistor 00 kω 7 R, R7, R Resistors 00 Ω R Resistor 00. kω 9 R, R0 to R Resistors 00 0 Ω 0 RP to RP Resistor Pack 00 Ω Res. Array 7C00JTR U, U to U, U Resistor Pack 00 Ω 00 Ω Res. Array EB-V0JV U, U7 7LVT7 SO0 7LVT7WM T Transformer CD ADT-WT U AD MSOP-0 Op Amp U 7VC SO- OR U0 ADR0 SOT- Voltage Regulator 7 U9 VCCPECL VCC-QAB-0M000 Vectron Crystal U AD9 TQFP- ADC 9 U MC00-LVELD S0NB Clock Buffer 0 T ETC-- - T M/A-COM/ETC -- C, C7 to C9, C, C0, C0, C, C to C0 Capacitors 00 R0 to R, R, R0, R to R, Resistors 00 R to R, R to R0 E9 to E0, E7 to E Jumpers Not placed. Rev. 0 Page of

24 PCB SCHEMATICS U 7LVT7 00Ω OUT_EN VCC RPAK_ D0 Q0 D Q D Q D Q U D Q 7 D Q D Q 9 D7 Q7 U RPAK_ 0 CLOCK U7 7LVT7 00Ω OUT_EN VCC RPAK_ D0 Q0 D Q D Q D Q U D Q 7 D Q D Q 9 D7 Q7 U RPAK_ 0 CLOCK DB7 DB DB DB DB DB DB DB0 E7 E7 E E E70 E7 DA0 DA DA DA DA DA 0 DB DB DB D0B DRVDD DR D0A DA DA E COUT 7 E DB7 E E E E E VDL VDL 00Ω RP OUTPUT CONNECTOR P0 P P P P P0 P P P P P0 P P P P P0 P P P P P9 P7 P P P P9 P7 P P P P9 P7 P P P P9 P7 P P P 9 7 P DR+ DB7 DB DB DB DB DB DB DB0 DB DB DB P P P R 00Ω C0 COUT+ R 00Ω C DB7 DB DB DB DB DB DB DB0 7 CLKLAT+ VDL R0 R NOTE: TWO 0 PIN OUTPUT CONNECTOR IMPLEMENTED AS ONE 0 PIN CONNECTOR 00Ω RP OUTPUT CONNECTOR P0 P P P P P0 P P P P P0 P P P P P0 P P P P P9 P7 P P P P9 P7 P P P P9 P7 P P P P9 P7 P P P 9 7 P DR DA7 DA DA DA DA DA DA DA0 DA0 DA DA DA DA DA DA DA7 7 CLKLAT VDL R R P P P P P P P P P P P P VAMP VDL DRVDD VCTRL PWDN S R0 E E R0 R 0kΩ SENSE A PWDN S DR D7B DB DB DB VAMP VREF E9 DB DB DB A A 0 DB0 DRVDD 9 7 R DCO+ DCO E VIN VIN+ A S DS DS+ 7 9 U AD9 0 DA0 DA DA S U0 ADR0 V+ TRIM/NC V C 0.µF + C 0µF C 0.µF R 0Ω J DS E7 C9 0.µF J DS+ CLK+ CLK A DRVDD DR D7A DA DA DA DA AMPOUT E9 AMPOUT E E C 0.µF C9 C R 0Ω R 0Ω DA DA DA DA DA7 R 0Ω T SEC PRI E0 J ANALOG INPUT DRVDD CM CM C0 0.µF R CM T-T T TIN R 0Ω C 0.µF DA DA7 R9 0Ω R T+ AMPIN OP AMP CONFIGURATION REMOVE C REMOVE R9 AND R VCTRL R 0Ω C 0.µF E9 E0 E C 0.µF VCTRL VCTRL VCTRL VDL DRVDD DRVDD = NOT NORMALLY POPULATED = NOT POPULATED, USER SELECTED E CLK+ Q J 7 E CLK CLK Q R VCC CLK Q 00LVEL CLKN Q VBB VEE R 0Ω R Ω C 0.µF R Ω R7 0Ω C 0.µF U OPTIONAL TRANSFORMER T ETC-- R 0Ω R 0Ω T+ TIN CM C 0.µF CM PADS FOR SHORTING EL, USED IF BYPASSING EL P P T Q CLK PRI SEC P7 P Q CLKN Figure 9. PCB Schematic ( of ) Rev. 0 Page of

25 VDL VDL VDL VDL E E E E E0 E E9 E7 E E E E R9 00Ω R 00Ω R 00Ω R7 00Ω COUT+ COUT+ COUT COUT 9 0 A B A B A B A B U 7VC Y Y Y Y 7 R 00Ω R9 0Ω R 00Ω R 0Ω PWR VDL CLKLAT+ DR+ CLKAT DR C 0µF + R VAMP VAMPF C VDL C 0µF C 0µF DRVDD C 0µF VCTRL C 0µF + C C7 C C9 0.µF 0.µF 0.µF 0.µF + C C C C7 0.µF 0.µF 0.µF 0.µF + C9 C 0.µF 0.µF + C 0.µF R VDL AMPIN R C C VAMPF R7 R0 R PWUP RGP INHI INLO U AD 0 VOCM VPOS OPHI OPLO RPG COMM 7 9 VAMPF VAMPF R C R R7 R C9 C0 R C7 AMPOUT AMPOUT E E E VCTRL C R7 C0 NC E/D OPTIONAL TALS U O-00 VCC OUT 7 VEE OUT VCC PECL VC OUTPUTB OUTPUT R R = NOT NORMALLY POPULATED = NOT POPULATED, USER SELECTED R0 R R R9 CLK CLK VCTRL R kω R kω R kω E E E E9 E E E E7 S VCTRL R R E0 E VCTRL PWDN E S E90 E9 R kω VCTRL VCTRL R9 R0 VCTRL Figure 0. PCB Schematic ( of ) Rev. 0 Page of

26 PCB LAYERS August, Figure. PCB Top-Side Silkscreen Figure. PCB Ground Layer Figure. PCB Top-Side Copper Routing 00-0 Figure. PCB Split Power Plane 00-0 Rev. 0 Page of

27 Figure. PCB Bottom-Side Copper Routing 00-0 Figure. PCB Bottom-Side Silkscreen Rev. 0 Page 7 of

28 OUTLINE DIMENSIONS.0 MA.00 SQ PIN TOP VIEW (PINS DOWN) 0.00 SQ SEATING PLANE 0 MIN VIEW A ROTATED 90 CCW VIEW A MA COPLANARITY 0.0 BSC COMPLIANT TO JEDEC STANDARDS MS-0ACB Figure 7. -Lead Thin Plastic Quad Flat Package [TQFP] (SU-) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9BSUZ-0 0 C to + C -Lead Thin Plastic Quad Flat Package (TQFP) SU- AD9-PCB Evaluation Board Z = Pb-free part. Evaluation board shipped with AD9BSUZ-0 installed. 00 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00 0 0/0(0) Rev. 0 Page of