16-Bit, 80 MSPS/105 MSPS ADC AD9460

Transcription

1 6-Bit, 8 MSPS/5 MSPS ADC AD946 FEATURES 5 MSPS guaranteed sampling rate (AD946-5) 79.4 dbfs SNR/9 dbc SFDR with MHz input (.4 V p-p input, 8 MSPS) 78. dbfs SNR/ with 7 MHz input (4. V p-p input, 8 MSPS) 77.8 dbfs SNR/87 dbc SFDR with 7 MHz input (.4 V p-p input, 8 MSPS) 77. dbfs SNR/84 dbc SFDR with 7 MHz input (.4 V p-p input, 5 MSPS) 9 dbfs two-tone SFDR with 9 MHz/4 MHz input (.4 V p-p input, 5 MSPS) 6 fsec rms jitter Excellent linearity DNL = ±.5 LSB typical INL = ±. LSB typical. V p-p to 4. V p-p differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output data capture clock available. V and 5 V supply operation APPLICATIONS MRI receivers Multicarrier, multimode, cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaging Communications instrumentation GENERAL DESCRIPTION The AD946 is a 6-bit, monolithic, sampling, analog-to-digital converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use. The AD946 operates up to 5 MSPS, providing a superior signalto-noise ratio (SNR) for instrumentation, medical imaging, and radar receivers using baseband (< MHz) and IF frequencies. The ADC requires. V and 5. V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are CMOS or LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances. Rev. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. VIN+ VIN CLK+ CLK AD946 BUFFER FUNCTIONAL BLOCK DIAGRAM A T/H CLOCK AND TIMING MANAGEMENT PIPELINE ADC REF DR CMOS OR LVDS OUTPUT STAGING DFS DCS MODE OUTPUT MODE One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved. 6 VREF SENSE REFT REFB Figure. OR D5 TO D DCO Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data mode. The AD946 is available in a Pb-free, -lead, surface-mount, plastic package (TQFP_EP) specified over the industrial temperature range of 4 C to +85 C. PRODUCT HIGHLIGHTS. True 6-bit linearity.. High performance: outstanding SNR performance for baseband IFs in data acquisition, instrumentation, magnetic resonance imaging, and radar receivers.. Ease of use: on-chip reference and high input impedance, track-and-hold with adjustable analog input range, and an output clock simplifies data capture. 4. Packaged in a Pb-free, -lead TQFP/EP. 5. Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of clock pulse widths. 6. Out-of-range (OR) outputs indicate when the signal is beyond the selected input range. 66-

2 AD946 TABLE OF CONTENTS Features... Functional Block Diagram... Applications... General Description... Product Highlights... Revision History... Specifications... DC Specifications... AC Specifications... 4 Digital Specifications... 5 Switching Specifications... 5 Timing Diagrams... 6 Absolute Maximum Ratings... 7 Thermal Resistance... 7 Pin Configurations and Function Descriptions...8 Equivalent Circuits... Typical Performance Characteristics... Terminology... 9 Theory of Operation... Analog Input and Reference Overview... Clock Input Considerations... Power Considerations... Digital Outputs... Timing... Operational Mode Selection... Evaluation Board... 4 Outline Dimensions... Ordering Guide... ESD Caution... 7 REVISION HISTORY 7/6 Revision : Initial Version Rev. Page of

3 SPECIFICATIONS DC SPECIFICATIONS AD946 =. V, = 5. V, =. V, LVDS mode, specified minimum sampling rate,.4 V p-p differential input, internal trimmed reference (. V mode), analog input amplitude =. dbfs, DCS = A (on), SFDR = A, unless otherwise noted. Table. AD946BSVZ-8 AD946BSVZ-5 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION Full 6 6 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full 5. ± ±. +5. mv Gain Error 5 C ±.5 + ±.5 + % FSR Full % FSR Differential Nonlinearity (DNL) 5 C.8 ± ± LSB Full Integral Nonlinearity (INL) 5 C 6 ± +6 6 ± +6 LSB VOLTAGE REFERENCE Output Voltage VREF =.7 V Full.7.7 V Load ma Full ± ± mv Reference Input Current (External VREF =.7 V) Full 5 5 μa INPUT REFERRED NOISE 5 C.4.5 LSB rms ANALOG INPUT Input Span VREF =.7 V Full.4.4 V p-p VREF =. V Full.. V p-p Internal Input Common-Mode Voltage Full.5.5 V External Input Common-Mode Voltage Full V Input Resistance Full kω Input Capacitance Full 6 6 pf POWER SUPPLIES Supply Voltages Full V Full V LVDS Outputs Full V CMOS Outputs Full V Supply Currents Full ma, Full 6 ma I LVDS Outputs Full ma I CMOS Outputs Full 4 4 ma PSRR Offset Full mv/v Gain Full.. %/V POWER CONSUMPTION LVDS Outputs Full W CMOS Outputs (DC Input) Full.5.7 W Measured at the maximum clock rate, fin = 5 MHz, full-scale sine wave, with a Ω differential termination on each pair of output bits for LVDS output mode and approximately 5 pf loading on each output bit for CMOS output mode. Input capacitance or resistance refers to the effective impedance between one differential input pin and A. Refer to Figure 6 for the equivalent analog input structure. For SFDR =, I power increases by ~7 mw for the AD946BSVZ-8 and ~ mw for the AD946BSVZ-5. Rev. Page of

4 AD946 AC SPECIFICATIONS =. V, = 5. V, =. V, LVDS mode, specified minimum sample rate,.4 V p-p differential input, internal trimmed reference (.7 V mode), AIN =. dbfs, DCS = A (on), SFDR = A, unless otherwise noted. Table. AD946BSVZ-8 AD946BSVZ-5 Parameter Temp Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fin = MHz 5 C db Full fin = 7 MHz 5 C db Full fin = 5 MHz 5 C db SIGNAL-TO-NOISE AND DISTORTION (SINAD) fin = MHz 5 C db Full fin = 7 MHz 5 C db Full fin = 5 MHz 5 C db EFFECTIVE NUMBER OF BITS (ENOB) fin = MHz 5 C.8.7 bits fin = 7 MHz 5 C.5.4 bits fin = 5 MHz 5 C.. bits SPURIOUS-FREE DYNAMIC RANGE (SFDR, SECOND OR THIRD HARMONIC) fin = MHz 5 C dbc Full fin = 7 MHz 5 C dbc Full fin = 5 MHz 5 C 8 8 dbc WORST SPUR EXCLUDING SECOND OR THIRD HARMONICS fin = MHz 5 C dbc Full 9 9 fin = 7 MHz 5 C dbc Full fin = 5 MHz 5 C 97 9 dbc TWO-TONE SFDR fin = dbfs, dbfs 5 C 89 9 dbfs ANALOG BANDWIDTH Full MHz Rev. Page 4 of

5 AD946 DIGITAL SPECIFICATIONS =. V, = 5. V, =. V, RLVDS_BIAS =.74 kω, unless otherwise noted. Table. AD946BSVZ-8/5 Parameter Temp Min Typ Max Unit CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Full. V Low Level Input Voltage Full.8 V High Level Input Current Full μa Low Level Input Current Full + μa Input Capacitance Full pf DIGITAL OUTPUT BITS CMOS MODE (D to D5, OTR) =. V High Level Output Voltage Full.5 V Low Level Output Voltage Full. V DIGITAL OUTPUT BITS LVDS MODE (D to D5, OTR) VOD Differential Output Voltage Full mv VOS Output Offset Voltage Full.5.75 V CLOCK INPUTS (CLK+, CLK ) Differential Input Voltage Full. V Common-Mode Voltage Full..5.6 V Input Resistance Full..4.7 kω Input Capacitance Full pf Output voltage levels measured with 5 pf load on each output. LVDS RTERM = Ω. SWITCHING SPECIFICATIONS =. V, = 5. V, =. V, unless otherwise noted. Table 4. AD946BSVZ-8 AD946BSVZ-5 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Maximum Conversion Rate Full 8 5 MSPS Minimum Conversion Rate Full MSPS CLK Period Full ns CLK Pulse Width High (tclkh) Full 5..8 ns CLK Pulse Width Low (tclkl) Full 5..8 ns DATA OUTPUT PARAMETERS Output Propagation Delay CMOS (tpd) (Dx, DCO+) Full.5.5 ns Output Propagation Delay LVDS (tpd) (Dx+), (tcpd) (DCO+) Full ns Pipeline Delay (Latency) Full cycles Aperture Delay (ta) Full ns Aperture Uncertainty (Jitter, tj) Full 6 6 fs, rms With duty cycle stabilizer (DCS) enabled. Output propagation delay is measured from clock 5% transition to data 5% transition with 5 pf load. LVDS RTERM = Ω. Measured from the 5% point of the rising edge of CLK+ to the 5% point of the data transition. Rev. Page 5 of

6 AD946 TIMING DIAGRAMS VIN N N N + N + N + 4 N + 5 t CLKL CLK+ t CLKH /f S CLK t PD Dx DCO+ N N N N + CLOCK CYCLES DCO t CPD Figure. LVDS Mode Timing Diagram 66- N N VIN t CLKL N + N + t CLKH CLK CLK+ t PD CLOCK CYCLES Dx N N N N DCO+ DCO Figure. CMOS Timing Diagram 66- Rev. Page 6 of

7 AD946 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating ELECTRICAL to A. V to +4 V to A. V to +6 V to D. V to +4 V A to D. V to +. V to 4 V to +4 V to 4 V to +6 V to 4 V to +6 V D± Through D5± to D. V to +. V CLK+/CLK to A. V to +. V OUTPUT MODE, DCS MODE, and. V to +. V DFS to A VIN+, VIN to A. V to +. V VREF to A. V to +. V SENSE to A. V to +. V REFT, REFB to A. V to +. V ENVIRONMENTAL Storage Temperature Range 65 C to +5 C Operating Temperature Range 4 C to +85 C Lead Temperature (Soldering sec) C Junction Temperature 5 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The heat sink of the AD946 package must be soldered to ground. Airflow increases heat dissipation, effectively reducing θja. Also, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the θja. It is required that the exposed heat sink be soldered to the ground plane. Table 6. Package Type θja θjb θjc Unit -Lead TQFP_EP C/W Typical θja = 9.8 C/W (heat sink soldered) for a multilayer board in still air. Typical θjb = 8. C/W (heat sink soldered) for a multilayer board in still air. Typical θjc = C/W (junction to exposed heat sink) represents the thermal resistance through heat sink path ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. Page 7 of

8 AD946 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SFDR A A A OR+ OR DR D5+ (MSB) D5 D4+ D4 D+ D D+ D D+ D DCS MODE DNC OUTPUT MODE PIN 75 DR 74 D+ 7 D DFS 4 7 D9+ LVDS_BIAS 5 7 D9 6 7 D8+ SENSE 7 69 D8 VREF A REFT REFB A VIN+ VIN A AD946 LVDS MODE TOP VIEW (Not to Scale) 68 DCO+ 67 DCO 66 D7+ 65 D DR 6 D6+ 6 D6 6 D5+ 59 D5 58 D4+ 57 D4 56 D+ 55 D 54 D+ 5 D 5 D+ 5 D DNC = DO NOT CONNECT Figure 4. -Lead TQFP_EP Pin Configuration in LVDS Mode Table 7. Pin Function Descriptions -Lead TQFP_EP in LVDS Mode Pin No. Mnemonic Description DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (A) to enable DCS (recommended). DCS = high () to disable DCS. DNC Do Not Connect. This pin should float. OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = for CMOS mode. OUTPUT MODE = () for LVDS outputs. 4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high () for twos complement DFS = low (ground) for offset binary format. 5 LVDS_BIAS Set Pin for LVDS Output Current. Place a.7 kω resistor terminated to DR. 6, 8 to, to 4, 6, 8,. V (±5%) Analog Supply. 4 to 45, 9 to 97 7 SENSE Reference Mode Selection. Connect to A for internal.7 V reference (.4 V p-p analog input range); connect to for external reference. 8 VREF.7 V Reference I/O. The function is dependent on the SENSE pin and external programming resistors. Decouple to ground with. μf and μf capacitors. 9,, 4, 9, 4, 46, 9, 98, 99, Exposed Heat Sink A A CLK+ CLK A Analog Ground. The exposed heat sink on the bottom of the package must be connected to A. A DR D (LSB) D Rev. Page 8 of

9 AD946 Pin No. Mnemonic Description REFT Differential Reference Output. Decoupled to ground with. μf capacitor and to REFB (Pin ) with. μf and μf capacitors. REFB Differential Reference Output. Decoupled to ground with a. μf capacitor and to REFT (Pin ) with. μf and μf capacitors. to 7, 5 to, 5, 7 5. V Analog Supply (±5%). VIN+ Analog Input True. VIN Analog Input Complement. 4 CLK+ Clock Input True. 4 CLK Clock Input Complement. 47, 6, 75, 87 DR Digital Output Ground. 48, 64, 76, 88. V Digital Output Supply (. V to.6 V). 49 D (LSB) D Complement Output Bit (LVDS Levels). 5 D+ D True Output Bit. 5 D D Complement Output Bit. 5 D+ D True Output Bit. 5 D D Complement Output Bit. 54 D+ D True Output Bit. 55 D D Complement Output Bit. 56 D+ D True Output Bit. 57 D4 D4 Complement Output Bit. 58 D4+ D4 True Output Bit. 59 D5 D5 Complement Output Bit. 6 D5+ D5 True Output Bit. 6 D6 D6 Complement Output Bit. 6 D6+ D6 True Output Bit. 65 D7 D7 Complement Output Bit. 66 D7+ D7 True Output Bit. 67 DCO Data Clock Output Complement. 68 DCO+ Data Clock Output True. 69 D8 D8 Complement Output Bit. 7 D8+ D8 True Output Bit. 7 D9 D9 Complement Output Bit. 7 D9+ D9 True Output Bit. 7 D D Complement Output Bit. 74 D+ D True Output Bit. 77 D D Complement Output Bit. 78 D+ D True Output Bit. 79 D D Complement Output Bit. 8 D+ D True Output Bit. 8 D D Complement Output Bit. 8 D+ D True Output Bit. 8 D4 D4 Complement Output Bit. 84 D4+ D4 True Output Bit. 85 D5 D5 Complement Output Bit. 86 D5+ (MSB) D5 True Output Bit. 89 OR Out-of-Range Complement Output Bit. 9 OR+ Out-of-Range True Output Bit. SFDR SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the AD946 analog front end. Connecting SFDR to A optimizes SFDR performance for applications with analog input frequencies < MHz for 8 MSPS and 5 MSPS speed grades. For applications with analog inputs > MHz, connect this pin to for optimum SFDR performance; power dissipation from increases by ~7 mw for the AD946BSVZ-8 and ~ mw for the AD946BSVZ-5. Rev. Page 9 of

10 AD946 SFDR A A A OR+ D5+ (MSB) DR D4+ D+ D+ D+ D+ D9+ D8+ D7+ D6+ D DCS MODE DNC OUTPUT MODE PIN 75 DR 74 D4+ 7 D+ DFS 4 7 D+ LVDS_BIAS 5 7 D+ 6 7 D+ (LSB) SENSE 7 69 DNC VREF A REFT REFB A VIN+ VIN A AD946 CMOS MODE TOP VIEW (Not to Scale) 68 DCO+ 67 DCO 66 DNC 65 DNC 64 6 DR 6 DNC 6 DNC 6 DNC 59 DNC 58 DNC 57 DNC 56 DNC 55 DNC 54 DNC 5 DNC 5 DNC 5 DNC DNC = DO NOT CONNECT Figure 5. -Lead TQFP_EP Pin Configuration in CMOS Mode Table 8. Pin Function Descriptions -Lead TQFP_EP in CMOS Mode Pin No. Mnemonic Description DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (A) to enable DCS (recommended). DCS = high () to disable DCS., 49 to 6, 65 to 66, 69 DNC Do Not Connect. These pins should float. OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = for CMOS mode. OUTPUT MODE = () for LVDS outputs. 4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high () for twos complement. DFS = low (ground) for offset binary format. 5 LVDS_BIAS Set Pin for LVDS Output Current. Place a.7 kω resistor terminated to DR. 6, 8 to, to 4, 6,. V (±5%) Analog Supply. 8, 4 to 45, 9 to 97 7 SENSE Reference Mode Selection. Connect to A for internal.7 V reference (.4 V p-p analog input range); connect to for external reference. 8 VREF.7 V Reference I/O. The function is dependent on the SENSE pin and external programming resistors. Decouple to ground with. μf and μf capacitors. 9,, 4, 9, 4, 46, 9, 98, 99, Exposed Heat Sink A Analog Ground. The exposed heat sink on the bottom of the package must be connected to A. REFT Differential Reference Output. Decoupled to ground with. μf capacitor and to REFB (Pin ) with. μf and μf capacitors. A CLK+ CLK A A DR DNC DNC 66-5 Rev. Page of

11 AD946 Pin No. Mnemonic Description REFB Differential Reference Output. Decoupled to ground with a. μf capacitor and to REFT (Pin ) with. μf and μf capacitors. to 7, 5 to, 5, 7 5. V Analog Supply (±5%). VIN+ Analog Input True. VIN Analog Input Complement. 4 CLK+ Clock Input True. 4 CLK Clock Input Complement. 47, 6, 75, 87 DR Digital Output Ground. 48, 64, 76, 88. V Digital Output Supply (. V to.6 V). 67 DCO Data Clock Output Complement. 68 DCO+ Data Clock Output True. 7 D+ (LSB) D True Output Bit (CMOS Levels). 7 D+ D True Output Bit. 7 D+ D True Output Bit. 7 D+ D True Output Bit. 74 D4+ D4 True Output Bit. 77 D5+ D5 True Output Bit. 78 D6+ D6 True Output Bit. 79 D7+ D7 True Output Bit. 8 D8+ D8 True Output Bit. 8 D9+ D9 True Output Bit. 8 D+ D True Output Bit. 8 D+ D True Output Bit. 84 D+ D True Output Bit. 85 D+ D True Output Bit. 86 D4+ D4 True Output Bit. 89 D5+ (MSB) D5 True Output Bit. 9 OR+ Out-of-Range True Output Bit. SFDR SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the AD946 analog front end. Connecting SFDR to A optimizes SFDR performance for applications with analog input frequencies < MHz for 8 MSPS and 5 MSPS speed grades. For applications with analog inputs > MHz, connect this pin to for optimum SFDR performance; power dissipation from increases by ~7 mw for the AD946BSVZ-8 and ~ mw for the AD946BSVZ-5. Rev. Page of

12 AD946 EQUIVALENT CIRCUITS VIN+ 6pF kω Dx. X T/H kω 66-9 VIN 6pF Figure 6. Equivalent Analog Input Circuit 66-6 Figure 9. Equivalent CMOS Digital Output Circuit VDD.V K LVDS_BIAS.74kΩ I LVDSOUT Figure 7. Equivalent LVDS_BIAS Circuit 66-7 DCS MODE, OUTPUT MODE, DFS kω Figure. Equivalent Digital Input Circuit, DFS, DCS MODE, OUTPUT MODE 66- V Dx V Dx+ CLK+ kω kω CLK V V.5kΩ.5kΩ Figure 8. Equivalent LVDS Digital Output Circuit 66-8 Figure. Equivalent Sample Clock Input Circuit 66- Rev. Page of

13 TYPICAL PERFORMANCE CHARACTERISTICS AD946 =. V, = 5. V, =. V, rated sample rate, LVDS mode, DCS enabled, TA = 5 C,.4 V p-p differential input, AIN = dbfs, internal trimmed reference (nominal VREF =.7 V), unless otherwise noted. AMPLITUDE (dbfs) SNR = 78.dB ENOB =.9 BITS SFDR = 88dBc FREQUENCY (MHz) Figure. 5 MSPS, 64k Point, Single-Tone FFT,. MHz 66- AMPLITUDE (dbfs) MSPS SNR = 75.dB ENOB =.6 BITS SFDR = 8dBc FREQUENCY (MHz) Figure 5. 5 MSPS, 64k Point, Single-Tone FFT, 5. MHz 66-5 AMPLITUDE (dbfs) MSPS SNR = 76.dB ENOB =.6 BITS SFDR = 84dBc FREQUENCY (MHz) Figure. 5 MSPS, 64k Point, Single-Tone FFT, 7. MHz 66-5 DNL (MSB) OUTPUT CODE Figure 6. 5 MSPS, DNL Error vs. Output Code,. MHz 66-6 AMPLITUDE (dbfs) MSPS SNR = 77.8dB ENOB =.6 BITS SFDR = 86dBc FREQUENCY (MHz) Figure 4. 5 MSPS, 64k Point, Single-Tone FFT, 7. MHz 66-4 INL (MSB) OUTPUT CODE Figure 7. 5 MSPS, INL Error vs. Output Code,. MHz 66-7 Rev. Page of

14 AD946 SNR = 78.4dB ENOB =.9 BITS SFDR = 9dBc 8MSPS SNR = 75.7dB ENOB =.6 BITS SFDR = 8dBc AMPLITUDE (dbfs) AMPLITUDE (dbfs) FREQUENCY (MHz) Figure 8. 8 MSPS, 64k Point Single-Tone FFT,. MHz FREQUENCY (MHz) Figure. 8 MSPS, 64k Point Single-Tone FFT, 5. MHz 66-5 AMPLITUDE (dbfs) MSPS SNR = 76.8dB ENOB =.5 BITS SFDR = 87dBc FREQUENCY (MHz) Figure 9. 8 MSPS, 64k Point, Single-Tone FFT, 7. MHz 66-9 DNL (MSB) OUTPUT CODE Figure. 8 MSPS, DNL Error vs. Output Code,. MHz 66- AMPLITUDE (dbfs) MSPS SNR = 77.8dB ENOB =.5 BITS SFDR = 86dBc INL (MSB) FREQUENCY (MHz) Figure. 8 MSPS, 64k Point, Single-Tone FFT, 7. MHz OUTPUT CODE Figure. 8 MSPS, INL Error vs. Output Code,. MHz 66- Rev. Page 4 of

15 AD SFDR dbc 9 SFDR +85 C SFDR +5 C SFDR 4 C 85 (db) 85 8 SNR +5 C SNR 4 C (db) 8 75 SNR db 75 SNR +85 C ANALOG INPUT FREQUENCY (MHz) Figure 4. 5 MSPS, SNR/SFDR vs. Analog Input Frequency,.4 V p-p ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 7. 5 MSPS, SNR/SFDR vs. Analog Input Common Mode SFDR dbfs 9 85 SFDR +85 C SFDR +5 C SFDR 4 C 8 SNR dbfs (db) (db) 6 8 SNR 4 C 4 SFDR dbc 75 7 SNR +5 C SNR +85 C 5 5 ANALOG INPUT FREQUENCY (MHz) Figure 5. 5 MSPS, SNR/SFDR vs. Analog Input Frequency,.4 V p-p, CMOS Mode SNR db ANALOG INPUT AMPLITUDE (db) Figure 8. 5 MSPS, 7. MHz SNR/SFDR vs. Analog Input Level, CMOS Output Mode 66-9 SFDR dbfs 95 SFDR +85 C SFDR +5 C 9 SFDR 4 C 8 SNR dbfs 85 (db) 6 (db) 8 SNR +5 C SNR 4 C 4 SFDR dbc 75 SNR +85 C SNR db ANALOG INPUT AMPLITUDE (db) Figure 6. 5 MSPS, 7. MHz SNR/SFDR vs. Analog Input Level ANALOG INPUT FREQUENCY (MHz) Figure 9. 8 MSPS, SNR/SFDR vs. Analog Input Frequency,.4 V p-p, CMOS Mode 66- Rev. Page 5 of

16 AD946 SFDR dbfs SFDR dbfs 8 SNR dbfs 8 SNR dbfs (db) 6 (db) 6 SFDR dbc 4 SFDR dbc 4 SNR db ANALOG INPUT AMPLITUDE (db) Figure. 8 MSPS, 7. MHz SNR/SFDR vs. Analog Input Level 66-9 SNR db ANALOG INPUT AMPLITUDE (db) Figure. 8 MSPS, 7. MHz SNR/SFDR vs. Analog Input Level, CMOS Output Mode SFDR +5 C SFDR +85 C 8MSPS 7dBFS 7dBFS SFDR = 89dBFS 4 (db) 85 8 SNR +5 C SNR 4 C SFDR 4 C (dbfs) SNR +85 C ANALOG INPUT FREQUENCY (MHz) Figure. 8 MSPS, SNR/SFDR vs. Analog Input Frequency,.4 V p-p FREQUENCY (MHz) Figure 4. 8 MSPS, 64k Point Two-Tone FFT, 9.6 MHz, 4.6 MHz 66-5 (db) SFDR dbc SNR db ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure. 8 MSPS, SNR/SFDR vs. Analog Input Common Mode SFDR dbc WORST IMD dbc 8 9 SFDR dbfs WORST IMD dbfs ANALOG INPUT AMPLITUDE (dbfs) Figure 5. 8 MSPS, 64k Point Two-Tone FFT, 9.6 MHz, 4.6 MHz SFDR AND IMD (db) 66-6 Rev. Page 6 of

17 AD MSPS 7dBFS 7dBFS SFDR = 9dBFS (dbfs) 6 8 FREQUENCY FREQUENCY (MHz) Figure 6. 5 MSPS, 64k Point Two-Tone FFT, 9.6 MHz, 4.6 MHz 66-4 N 9 N 8 N 7 N 6 N 5 N 4 N N N N+ N+ N+ N+ N+4 N+5 N+6 N+7 N+8 N+9 N+ BIN Figure 8. 8 MSPS, Grounded Input Histogram 66-4 SFDR AND IMD (db) SFDR dbfs WORST IMD dbc SFDR dbc WORST IMD dbfs ANALOG INPUT AMPLITUDE (dbfs) Figure 7. 5 MSPS, Two-Tone SFDR vs. Analog Input Level, 9.6 MHz, 4.6 MHz 66-4 FREQUENCY N N 9 N 8 N 7 N 6 N 5 N 4 N N N N+ N+ N+ N+ N+4 N+5 N+6 N+7 N+8 N+9 N+ BIN Figure 9 5 MSPS, Grounded Input Histogram Rev. Page 7 of

18 AD MHz, 8MSPS GAIN ERROR (%FS) MSPS 8MSPS (dbc) MHz, 5MSPS TEMPERATURE ( C) Figure 4. Gain vs. Temperature ANALOG INPUT RANGE (V p-p) Figure 4. SFDR vs. Analog Input Range MHz, 8MSPS 85 5 SFDR dbc SFDR dbc (dbfs) MHz, 5MSPS (db) 75 8 SNR db 5 SNR db ANALOG INPUT RANGE (V p-p) SAMPLE RATE (MSPS) Figure 4. SNR vs. Analog Input Range Figure 4. Single-Tone SNR/SFDR vs. Sample Rate, 7. MHz Rev. Page 8 of

19 AD946 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by db. Aperture Delay (ta) The delay between the 5% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter, tj) The sample-to-sample variation in aperture delay. Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 6-bit resolution indicates that all 65,56 codes must be present over all operating ranges. Integral Nonlinearity (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level ½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may be a harmonic. SFDR can be reported in dbc (that is, degrades as signal level is lowered) or dbfs (always related back to converter full scale). Total Harmonic Distortion (THD) The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula: ( SINAD.76) ENOB = 6. Gain Error The first code transition should occur at an analog value of ½ LSB above negative full scale. The last transition should occur at an analog value of ½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Maximum Conversion Rate The clock rate at which parametric testing is performed. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than db below the guaranteed limit. Offset Error The major carry transition should occur for an analog value of ½ LSB below VIN+ = VIN. Offset error is defined as the deviation of the actual transition from that point. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from % above positive full scale to % above negative full scale, or from % below negative full scale to % below positive full scale. Output Propagation Delay (tpd) The delay between the clock rising edge and the time when all bits are within valid logic levels. Power-Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at the maximum limit. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (5 C) value to the value at TMIN or TMAX. Rev. Page 9 of

20 AD946 THEORY OF OPERATION The AD946 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated, high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 6-bit pipeline ADC core. The device includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are user selectable as standard V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT MODE pin. ANALOG INPUT AND REFERENCE OVERVIEW A stable and accurate.5 V band gap voltage reference is built into the AD946. The input range can be adjusted by varying the reference voltage applied to the AD946, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. Internal Reference Connection A comparator within the AD946 detects the potential at the SENSE pin and configures the reference into three possible states, summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 44), setting VREF to ~.7 V. If a resistor divider is connected as shown in Figure 45, the switch again sets to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as VREF =.5 V R + R In all reference configurations, REFT and REFB drive the analog-to-digital conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. Internal Reference Trim The internal reference voltage is trimmed during the production test; therefore, there is little advantage to the user supplying an external voltage reference to the AD946. The gain trim is performed with the AD946 input range set to.4 V p-p nominal (SENSE connected to A). Because of this trim, and the maximum ac performance provided by the.4 V p-p analog input range, there is little benefit to using analog input ranges < V p-p. However, reducing the range can improve SFDR performance in some applications. Likewise, increasing the range up to.4 V p-p can improve SNR. Users are cautioned that the differential nonlinearity of the ADC varies with the reference voltage. Configurations that use <. V p-p can exhibit missing codes and, therefore, degraded noise and distortion performance. µf + µf + VIN+ VIN VREF SENSE SELECT LOGIC AD946. ADC CORE REFT + µf REFB Figure 44. Internal Reference Configuration VIN+ VIN VREF R SENSE SELECT LOGIC R. AD946 ADC CORE REFT + µf REFB Figure 45. Programmable Reference Configuration Rev. Page of

21 AD946 Table 9. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference AVDD N/A external reference Programmable Reference. V to VREF R VREF.5 + (See Figure 45) R Programmable Reference. V to VREF R.5 (Set for V p-p) +, R = R = kω. R Internal Fixed Reference A to. V.7.4 External Reference Operation When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 kω load. The internal buffer continues to generate the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of. V. See Figure 4 for gain variation vs. temperature. Analog Inputs As with most new high speed, high dynamic range ADCs, the analog input to the AD946 is differential. Differential inputs improve on-chip performance because signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection of stray signals, such as ground and power noise. Second, they provide good rejection of common-mode signals, such as local oscillator feedthrough. The specified noise and distortion of the AD946 cannot be realized with a single-ended analog input; therefore, such configurations are discouraged. Contact sales for recommendations of other 6-bit ADCs that support single-ended analog input configurations. With the.7 V reference, which is the nominal value (see the Internal Reference Trim section), the differential input range of the AD946 analog input is nominally.4 V p-p or.7 V p-p on each input (VIN+ or VIN )..7V p-p VIN+. The AD946 analog input voltage range is offset from ground by.5 V. Each analog input connects through a kω resistor to the.5 V bias voltage and to the input of a differential buffer. The internal bias network on the input properly biases the buffer for maximum linearity and range (see the Equivalent Circuits section). Therefore, the analog source driving the AD946 should be ac-coupled to the input pins. The recommended method for driving the analog input of the AD946 is to use an RF transformer to convert single-ended signals to differential signals (see Figure 47). ANALOG INPUT SIGNAL R T ADT WT R S R S VIN+ AD946 VIN Figure 47. Transformer-Coupled Analog Input Circuit Series resistors between the output of the transformer and the AD946 analog inputs help isolate the analog input source from switching transients caused by the internal sample-and-hold circuit. The series resistors, along with the kω resisters connected to the internal.5 V bias, must be considered in impedance matching the transformer input. For example, if RT is set to 5 Ω, RS is set to Ω, and there is a : impedance ratio transformer, then the input matches a 5 Ω source with a fullscale drive of 6. dbm. The 5 Ω impedance matching can also be incorporated on the secondary side of the transformer, as shown in the evaluation board schematic (see Figure 5). CLOCK INPUT CONSIDERATIONS Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock combines with the desired signal at the analog-todigital output. For that reason, considerable care was taken in the design of the clock inputs of the AD946, and the user is advised to give careful thought to the clock source VIN DIGITAL OUT = ALL s DIGITAL OUT = ALL s Figure 46. Differential Analog Input Range for VREF =.7 V Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, can be sensitive to the clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD946 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock Rev. Page of

22 AD946 signal with a nominal ~5% duty cycle. Noise and distortion performance are nearly flat for a % to 7% duty cycle with the DCS enabled. The DCS circuit locks to the rising edge of CLK+ and optimizes timing internally. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than MHz nominally. The loop is associated with a time constant that should be considered in applications where the clock rate can change dynamically, requiring a wait time of.5 μs to 5 μs after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time that the loop is not locked, the DCS loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock signal. In such an application, it can be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. The DCS circuit is controlled by the DCS MODE pin; a CMOS logic low (A) on DCS MODE enables the duty cycle stabilizer, and logic high ( =. V) disables the controller. The AD946 input sample clock signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 6-bit accuracy places a premium on the encode clock phase noise. SNR performance can easily degrade by db to 4 db with 7 MHz analog input signals when using a high jitter clock source. See the AN-5 Application Note, Aperture Uncertainty and ADC System Performance, for more information. For optimum performance, the AD946 must be clocked differentially. The sample clock inputs are internally biased to ~.5 V, and the input signal is usually ac-coupled into the CLK+ and CLK pins via a transformer or capacitors. Figure 48 shows one preferred method for clocking the AD946. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary of the transformer limit clock excursions into the AD946 to approximately.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD946 and limits the noise presented to the sample clock inputs. CRYSTAL SINE SOURCE ADT WT CLK+ AD946 CLK HSMS8 DIODES Figure 48. Crystal Clock Oscillator, Differential Encode If a low jitter clock is available, it helps to band-pass filter the clock reference before driving the ADC clock inputs. Another option is to ac couple a differential ECL/PECL signal to the encode input pins, as shown in Figure ECL/ PECL Jitter Considerations VT VT ENCODE AD946 ENCODE Figure 49. Differential ECL for Encode High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (finput) and rms amplitude due only to aperture jitter (tj) can be calculated using the following equation: SNR = log[πfinput tj] In the equation, the rms aperture jitter represents the root-meansquare of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter. The clock input should be treated as an analog signal in cases where aperture jitter can affect the dynamic range of the AD946. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be synchronized by the original clock during the last step. POWER CONSIDERATIONS Care should be taken when selecting a power source. The use of linear dc supplies is highly recommended. Switching supplies tend to have radiated components that can be received by the AD946. Each of the power supply pins should be decoupled as closely to the package as possible using. μf chip capacitors. The AD946 has separate digital and analog power supply pins. The analog supplies are denoted (. V) and (5 V), and the digital supply pins are denoted. Although the and supplies can be tied together, best performance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that both and must be held within 5% of the specified voltage. The supply of the AD946 is a dedicated supply for the digital outputs in either LVDS or CMOS output modes. When in LVDS mode, the should be set to. V. In CMOS mode, the supply can be connected from.5 V to.6 V for compatibility with the receiving logic Rev. Page of

23 AD946 DIGITAL OUTPUTS LVDS Mode The off-chip drivers on the chip can be configured to provide LVDS-compatible output levels via Pin (OUTPUT MODE). LVDS outputs are available when OUTPUT MODE is CMOS logic high (or for convenience) and a.74 kω RSET resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic performance, including both SFDR and SNR, maximizes when using the AD946 in LVDS mode; designers are encouraged to take advantage of this mode. The AD946 outputs include complementary LVDS outputs for each data bit (Dx+/Dx ), the overrange output (OR+/OR ), and the output data clock output (DCO+/DCO ). The RSET resistor current is multiplied on-chip, setting the output current at each output equal to a nominal.5 ma ( IRSET). A Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 5 mv swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended, with a Ω termination resistor located as close to the receiver as possible. It is recommended to keep the trace length less than two inches and to keep differential output trace lengths as equal as possible. CMOS Mode In applications that can tolerate a slight degradation in dynamic performance, the AD946 output drivers can be configured to interface with.5 V or. V logic families by matching to the digital supply of the interfaced logic. CMOS outputs are available when OUTPUT MODE is CMOS logic low (or A for convenience). In this mode, the output data bits, Dx, are single-ended CMOS, as is the overrange output, OR+. The output clock serves as a differential CMOS signal, DCO+/DCO. Lower supply voltages are recommended to avoid coupling switching transients back to the sensitive analog sections of the ADC. Minimize the capacitive load to the CMOS outputs and connect each output to a single gate through a series resistor ( Ω) to minimize switching transients caused by the capacitive loading. TIMING The AD946 provides latched data outputs with a pipeline delay of clock cycles. Data outputs are available one propagation delay (tpd) after the rising edge of CLK+. Refer to Figure and Figure for detailed timing diagrams. OPERATIONAL MODE SELECTION Data Format Select The data format select (DFS) pin of the AD946 determines the coding format of the output data. This pin is. V CMOS compatible, with logic high (or,. V) selecting twos complement and DFS logic low (A) selecting offset binary format. Table summarizes the output coding. Output Mode Select The OUPUT MODE pin controls the logic compatibility, as well as the pinout of the digital outputs. This pin is a CMOScompatible input. With OUTPUT MODE = (A), the AD946 outputs are CMOS compatible, and the pin assignment for the device is as defined in Table 8. With OUTPUT MODE = (,. V), the AD946 outputs are LVDS compatible, and the pin assignment for the device is as defined in Table 7. Duty Cycle Stabilizer The DCS circuit is controlled by the DCS MODE pin; a CMOS logic low (A) on DCS MODE enables the DCS, and logic high (,. V) disables the controller. SFDR Enhancement Under certain conditions, the SFDR performance of the AD946 improves by adding some additional power to the core of the ADC. The SFDR control pin (Pin ) is a CMOS-compatible control pin to optimize the configuration of the AD946 analog front end. Connecting SFDR to A optimizes SFDR performance for applications with analog input frequencies < MHz for 8 MSPS and 5 MSPS speed grades. For applications with analog inputs > MHz, this pin should be connected to for optimum SFDR performance; power dissipation from increases by ~7 mw for the AD946BSVZ-8 and ~ mw for the AD946BSVZ-5. Table. Digital Output Coding VIN+ VIN Code Input Span =.4 V p-p (V) VIN+ VIN Input Span = V p-p (V) Digital Output Offset Binary (D5 D) Digital Output Twos Complement (D5 D) 65, ,768, Rev. Page of

24 AD946 EVALUATION BOARD Evaluation boards are offered to configure the AD946 in either CMOS mode or LVDS mode only. This design represents a recommended configuration for using the device over a wide range of sampling rates and analog input frequencies. These evaluation boards provide all the support circuitry required to operate the ADC in its various modes and configurations. Complete schematics are shown in Figure 5 through Figure 5. Gerber files are available from engineering applications demonstrating the proper routing and grounding techniques that should be applied at the system level. It is critical that signal sources with very low phase noise (<6 fsec rms jitter) are used to realize the ultimate performance of the converter. Proper filtering of the input signal to remove harmonics and lower the integrated noise at the input is also necessary to achieve the specified noise performance. The evaluation boards are shipped with a 5 V ac to 6 V dc power supply. The evaluation boards include low dropout regulators to generate the various dc supplies required by the AD946 and its support circuitry. Separate power supplies are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (see Figure 5). The LVDS mode evaluation boards include an LVDS-to- CMOS translator, making them compatible with the high speed ADC FIFO evaluation kit (HSC-ADC-EVALA-SC, The kit includes a high speed data capture board that provides a hardware solution for capturing up to kb samples of high speed ADC output data in a FIFO memory chip (user upgradeable to 56 kb samples). Software is provided to enable the user to download the captured data to a PC via the USB port. This software also includes a behavioral model of the AD946 and many other high speed ADCs. Behavioral modeling of the AD946 using ADIsimADC software is also available at The ADIsimADC software supports virtual ADC evaluation using ADI proprietary behavioral modeling technology. This allows rapid comparison between the AD946 and other high speed ADCs with or without hardware evaluation boards. The user can choose to remove the translator and terminations to access the LVDS outputs directly. Rev. Page 4 of

25 AD946 Rev. Page 5 of OPTIONAL R kω R.74kΩ DR E4 EXTREF D_C (LSB) D_T D_C D_T D_C D_T D4_C D4_T D5_C D5_T D7_C D7_T DR D8_C/D_Y D8_T/D_Y D9_C/D_Y D9_T/D_Y D_C/D4_Y C98 D5_C/D4_Y E4 E5 E7 E6 E6 E5 E4 C C9 C86 R D4_C/D_Y DR D6_T D_T DR D_T/D_Y D_T/D5_Y DRB D6_C D_C D4_T/D_Y D_C/D_Y D_T/D9_Y D_C/D8_Y D_T/D7_Y D_C/D6_Y ENCB ENC SCLK C R5 Ω R8 Ω R9 C9 C8 EPAD U AD946 R4 5Ω P P P P PTMICRO4 P4 4 P P P P PTMICRO4 EXTREF XTALPWR DR P4 4 DCS MODE DNC OUTPUT MODE DFS LVDSBIAS SENSE VREF A REFT REFB A VIN+ VIN A DR DOR_C DOR_T/DOR_Y (MSB) D5_T/D5_Y E E9 E E4 E E E6 E8 E9 C C5 J4 SMBMST R5 TINB ANALOG L nh E5 R6 5Ω R C5 µf C C4 DR D_T D_C D9_T D9_C D8_T D8_C DCO DCOB D7_T D7_C DR D6_T D6_C D5_T D5_C D4_T D4_C D_T D_C D_T D_C D_T D_C D_T D_C D_T D_C SFDR A A OR_C OR_T A DR D5_T D5_C D4_T D4_C D_T D_C ENC A ENCB A A DR D_C D_T H4 MTHOLE6 DR H MTHOLE6 H MTHOLE6 H MTHOLE6 C9 µf + TOUT CT TOUTB C7 PRI SEC T5 ADT-WT T NC TINB TOUTB TOUT CT PRI SEC ETC PRI SEC T ETC = DO NOT POPULATE Figure 5. Evaluation Board Schematic

26 AD946 R7 J5 SMBMST J SMBMST R8 5Ω C6 XTALINPUT POWER OPTIONS P4 PJ-A VIN X + C µf = DO NOT POPULATE 66-6 ENCODE R9 Ω T C6 ADT-WT 6 NC 5 4 PRI SEC CR TO MAKE LAYOUT AND PARASITIC LOADING SYMMETRICAL CR C4 CR ENC ENCB VXTAL L5 FERRITE L4 FERRITE L FERRITE X X X ADP8-5 U4 ADP8-. U7.V 4 OUT OUT X X 4 OUT OUT IN VIN IN + C89 µf + C4 µf + C87 µf OPTIONAL ENCODE CIRCUITS VXTAL E E E + C44 µf XTALPWR U ECLOSC + C µf C4 VXTAL 4 7 OUT VEE ~OUT 8 XTALINPUT L Ω DR ADP8-. U.V DR X X VIN 4 OUT OUT X IN VIN + C6 µf + C88 µf + C4 µf DR DR Figure 5. Evaluation Board Schematic, Encode, Optional Encode and Power Options Rev. Page 6 of

27 AD946 BYPASS CAPACITORS + C64 C4 µf C5 C C.µF C8 C7 C9 C5 C6 C C6 C75 C C4 C7 C6 C5 C C8 C9 C9 + C65 C47 µf C C C C69 C7 C45 C49 DR DR + C56 C85 µf C5 C5 C58.µF C7 C48 EXTREF C8 + C55 µf C7 C7 C8 C9 C C94 C95 C C59 C9 C96 C97 C84 C46 = DO NOT POPULATE Figure 5. Evaluation Board Schematic, Bypass Capacitors 66-6 Rev. Page 7 of

28 AD946 Rev. Page 8 of RSO6ISO R8 R7 R6 R5 R4 R R R RSO6ISO RZ RZ5 DO DO DO D4O D5O D6O D7O DO D8O D9O DO DO DO DO D4O D5O END D4Y DY DY DY ENC C4Y CY CY CY 4 B4Y BY BY BY ENB A4Y AY AY AY ENA D4B D4A DB DA DB DA DB DA C4B C4A CB CA CB CA CB CA B4B B4A BB BA BB BA BB BA A4B A4A AB AA AB AA AB AA U8 SN75LVDT86 D5_C/D4_Y D4_C/D_Y D_C/D_Y D_C/D8_Y D_C/D6_Y D_C/D4_Y D9_C/D_Y D_C D5_T/D4_Y D4_T/D_Y D_T/D_Y D_T/D9_Y D_T/D7_Y D_T/D5_Y D9_T/D_Y D8_T/D_Y D8_C/D_Y D7_T D7_C D6_T D6_C D5_C D5_T D4_T D4_C D_T D_T D_C D_T D_C D_T D_C DR DR DR DR DR DR P P P5 P7 P9 P P P5 P7 P9 P P P5 P7 P9 P P P5 P7 P9 P P4 P6 P8 P P P4 P6 P8 P P P4 P6 P8 P P P4 P6 P8 P4 P6 C4MS D4_C/D_Y D_C/D8_Y D_C/D4_Y D8_C/DO_Y DRB D7_C D4_C D_C D_C D5_C D6_C D9_C/D_Y D_C/D6_Y D_C/D_Y D_C DOR_C DR D5_C/D4_Y DR D_C D4_T/D_Y D_T/D9_Y D_T/D5_Y D8_T/D_Y DR D7_T D4_T D_T D_T D5_T D6_T D9_T/D_Y D_T/D7_Y D_T/D_Y D_T DOR_T/DOR_Y DR D5_T/D5_Y DR D_T R8 R7 R6 R5 R4 R R R EN 4 4Y Y Y Y EN 4B 4A B A B A B A U5 SN75LVDT9 R9 Ω R Ω DRB DOR_C DR DRO_T/DOR_Y DRO DR ORO C76 C8 C77 C78 P P P5 P7 P9 P P P5 P7 P9 P P P5 P7 P9 P P P5 P7 P9 P P4 P6 P8 P P P4 P6 P8 P P P4 P6 P8 P P P4 P6 P8 P4 P7 C4MS D5O DO DO D9O D8O D7O D4O DO DO D5O D6O DO DO D4O DO DRO DR DR DR ORO DR DO 66-6 Figure 5. Evaluation Board Schematic