IF Diversity Receiver AD6655

Transcription

1 IF Diversity Receiver AD6655 FEATURES SNR = 74.5 dbc (75.5 dbfs) in a 3.7 MHz BW at MSPS SFDR = 80 dbc to MSPS.8 V analog supply operation.8 V to 3.3 V CMOS output supply or.8 V LVDS output supply Integer -to-8 input clock divider Integrated dual-channel ADC Sample rates up to 50 MSPS IF sampling frequencies to 450 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: V p-p to V p-p ADC clock duty cycle stabilizer 95 db channel isolation/crosstalk Integrated wideband digital downconverter (DDC) 3-bit complex, numerically controlled oscillator (NCO) Decimating half-band filter and FIR filter Supports real and complex output modes Fast attack/threshold detect bits Composite signal monitor Energy-saving power-down modes APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications PRODUCT HIGHLIGHTS. Integrated dual, 4-bit, 50 MSPS ADC.. Integrated wideband decimation filter and 3-bit complex NCO. 3. Fast overrange detect and signal monitor with serial output. 4. Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz. 5. Flexible output modes, including independent CMOS, interleaved CMOS, IQ mode CMOS, and interleaved LVDS. 6. SYNC input allows synchronization of multiple devices bit SPI port for register programming and register readback. FUNCTIONAL BLOCK DIAGRAM AVDD FD[0:3]A DVDD DRVDD VIN+A VIN A SHA FD BITS/THRESHOLD DETECT ADC I Q LP/HP DECIMATING HB FILTER + FIR AD6655 CMOS/LVDS OUTPUT BUFFER D3A D0A VREF SENSE CML RBIAS VIN B VIN+B REF SELECT SHA ADC SIGNAL MONITOR 3-BIT TUNING NCO Q I LP/HP DECIMATING HB FILTER + FIR f ADC /8 NCO DIVIDE TO 8 DUTY CYCLE STABILIZER PROGRAMMING DATA DCO GENERATION CMOS OUTPUT BUFFER CLK+ CLK DCOA DCOB D3B D0B MULTI-CHIP SYNC FD BITS/THRESHOLD DETECT SIGNAL MONITOR DATA SIGNAL MONITOR INTERFACE SPI AGND SYNC FD[0:3]B SMI SDFS SMI SCLK/ PDWN SMI SDO/ OEB NOTES. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 0 FOR LVDS PIN NAMES. SDIO/ DCS SCLK/ DFS CSB DRGND Figure. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 906, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... Product Highlights... Functional Block Diagram... Revision History... 3 General Description... 4 Specifications... 5 ADC DC Specifications AD6655BCPZ-80/ AD6655BCPZ ADC DC Specifications AD6655BCPZ-5/ AD6655BCPZ ADC AC Specifications AD6655BCPZ-80/ AD6655BCPZ ADC AC Specifications AD6655BCPZ-5/ AD6655BCPZ Digital Specifications AD6655BCPZ-80/ AD6655BCPZ Digital Specifications AD6655BCPZ-5/ AD6655BCPZ Switching Specifications AD6655BCPZ-80/ AD6655BCPZ Switching Specifications AD6655BCPZ-5/ AD6655BCPZ Timing Specifications... 5 Absolute Maximum Ratings... 8 Thermal Characteristics... 8 ESD Caution... 8 Pin Configurations and Function Descriptions... 9 Equivalent Circuits... 3 Typical Performance Characteristics... 4 Theory of Operation... 9 ADC Architecture... 9 Analog Input Considerations... 9 Voltage Reference... 3 Clock Input Considerations... 3 Power Dissipation and Standby Mode Digital Outputs Digital Downconverter Downconverter Modes Numerically Controlled Oscillator (NCO) Half-Band Decimating Filter and FIR Filter fadc/8 Fixed-Frequency NCO Numerically Controlled Oscillator (NCO) Frequency Translation NCO Synchronization Phase Offset NCO Amplitude and Phase Dither Decimating Half-Band Filter and FIR filter Half-Band Filter Coefficients Half-Band Filter Features Fixed-Coefficient FIR Filter Synchronization Combined Filter Performance Final NCO ADC Overrange and Gain Control... 4 Fast Detect Overview... 4 ADC Fast Magnitude... 4 ADC Overrange (OR)... 4 Gain Switching... 4 Signal Monitor Peak Detector Mode RMS/MS Magnitude Mode Threshold Crossing Mode Additional Control Bits DC Correction Signal Monitor SPORT Output Channel/Chip Synchronization Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Memory Map Register Table... 5 Memory Map Register Description Applications Information Design Guidelines Evaluation Board... 6 Power Supplies... 6 Rev. 0 Page of 84

3 Input Signals...6 Output Signals...6 Default Operation and Jumper Selection Settings...6 Alternative Clock Configurations...6 Alternative Analog Input Drive Configuration...63 Schematics...64 Evaluation Board Layouts...74 Bill of Materials...8 Outline Dimensions...84 Ordering Guide...84 REVISION HISTORY /07 Revision 0: Initial Version Rev. 0 Page 3 of 84

4 GENERAL DESCRIPTION The AD6655 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 4-bit, 80 MSPS/05 MSPS/5 MSPS/50 MSPS ADCs and a wideband digital downconverter (DDC). The AD6655 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver, simplifying layout and reducing interconnection parasitics. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 3-bit frequency translator (numerically controlled oscillator (NCO)), a halfband decimating filter, a fixed FIR filter, and an fadc/8 fixedfrequency NCO. In addition to the receiver DDC, the AD6655 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with short latency. In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition. The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system. After digital processing, data can be routed directly to the two external 4-bit output ports. These outputs can be set from.8 V to 3.3 V CMOS or as.8 V LVDS. The CMOS data can also be output in an interleaved configuration at a double data rate using only Port A. The AD6655 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface. The AD6655 is available in a 64-lead LFCSP and is specified over the industrial temperature range of 40 C to +85 C. Rev. 0 Page 4 of 84

5 SPECIFICATIONS ADC DC SPECIFICATIONS AD6655BCPZ-80/AD6655BCPZ-05 AD6655 AVDD =.8 V, DVDD =.8 V, DRVDD =.8 V, maximum sample rate, VIN =.0 dbfs differential input,.0 V internal reference, DCS enabled, unless otherwise noted. Table. AD6655BCPZ-80 AD6655BCPZ-05 Parameter Temperature Min Typ Max Min Typ Max Unit RESOLUTION Full 4 4 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0. ±0.6 ±0. ±0.6 % FSR Gain Error Full % FSR MATCHING CHARACTERISTIC Offset Error 5 C ±0. ±0.6 ±0. ±0.6 % FSR Gain Error 5 C ±0. ±0.75 ±0. ±0.75 % FSR TEMPERATURE DRIFT Offset Error Full ±5 ±5 ppm/ C Gain Error Full ±95 ±95 ppm/ C INTERNAL VOLTAGE REFERENCE Output Voltage Error ( V Mode) Full ±5 ±8 ±5 ±8 mv Load ma Full 7 7 mv INPUT-REFERRED NOISE VREF =.0 V 5 C LSB rms ANALOG INPUT Input Span, VREF =.0 V Full V p-p Input Capacitance Full 8 8 pf VREF INPUT RESISTANCE Full 6 6 kω POWER SUPPLIES Supply Voltage AVDD, DVDD Full V DRVDD (CMOS Mode) Full V DRVDD (LVDS Mode) Full V Supply Current IAVDD, 3 Full ma IDVDD, 3 Full 75 5 ma IDRVDD (3.3 V CMOS) Full 8 ma IDRVDD (.8 V CMOS) Full 8 ma IDRVDD (.8 V LVDS) Full ma POWER CONSUMPTION DC Input Full mw Sine Wave Input (DRVDD =.8 V) Full mw Sine Wave Input (DRVDD = 3.3 V) Full mw Standby Power 4 Full 5 68 mw Power-Down Power Full mw Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure for the equivalent analog input structure. Measured with a 9.7 MHz, full-scale sine wave input, NCO enabled with a frequency of 3 MHz, FIR filter enabled and the fs/8 output mix enabled with approximately 5 pf loading on each output bit. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pin inactive (set to AVDD or AGND). Rev. 0 Page 5 of 84

6 ADC DC SPECIFICATIONS AD6655BCPZ-5/AD6655BCPZ-50 AVDD =.8 V, DVDD =.8 V, DRVDD =.8 V, maximum sample rate, VIN =.0 dbfs differential input,.0 V internal reference, DCS enabled, unless otherwise noted. Table. AD6655BCPZ-5 AD6655BCPZ-50 Parameter Temperature Min Typ Max Min Typ Max Unit RESOLUTION Full 4 4 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.3 ±0.6 ±0. ±0.6 % FSR Gain Error Full % FSR MATCHING CHARACTERISTIC Offset Error 5 C ±0.3 ±0.7 ±0. ±0.7 % FSR Gain Error 5 C ±0. ±0.7 ±0. ±0.8 % FSR TEMPERATURE DRIFT Offset Error Full ±5 ±5 ppm/ C Gain Error Full ±95 ±95 ppm/ C INTERNAL VOLTAGE REFERENCE Output Voltage Error ( V Mode) Full ±5 ±8 ±5 ±8 mv Load ma Full 7 7 mv INPUT-REFERRED NOISE VREF =.0 V 5 C LSB rms ANALOG INPUT Input Span, VREF =.0 V Full V p-p Input Capacitance Full 8 8 pf VREF INPUT RESISTANCE Full 6 6 kω POWER SUPPLIES Supply Voltage AVDD, DVDD Full V DRVDD (CMOS Mode) Full V DRVDD (LVDS Mode) Full V Supply Current IAVDD, 3 Full ma IDVDD, 3 Full ma IDRVDD (3.3 V CMOS) Full 6 8 ma IDRVDD (.8 V CMOS) Full 3 7 ma IDRVDD (.8 V LVDS) Full ma POWER CONSUMPTION DC Input Full mw Sine Wave Input (DRVDD =.8 V) Full mw Sine Wave Input (DRVDD = 3.3 V) Full mw Standby Power 4 Full mw Power-down Power Full mw Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure for the equivalent analog input structure. Measured with a 9.7 MHz, full-scale sine wave input, NCO enabled with a frequency of 3 MHz, FIR filter enabled and the fs/8 output mix enabled with approximately 5 pf loading on each output bit. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND). Rev. 0 Page 6 of 84

7 ADC AC SPECIFICATIONS AD6655BCPZ-80/AD6655BCPZ-05 AD6655 AVDD =.8 V, DVDD =.8 V, DRVDD =.8 V, maximum sample rate, VIN =.0 dbfs differential input,.0 V internal reference, DCS enabled, NCO enabled, half-band filter enabled, FIR filter enabled, unless otherwise noted. Table 3. AD6655BCPZ-80 AD6655BCPZ-05 Parameter Temperature Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR) fin =.4 MHz 5 C db fin = 70 MHz 5 C db Full db fin = 40 MHz 5 C db fin = 0 MHz 5 C db WORST SECOND OR THIRD HARMONIC fin =.4 MHz 5 C dbc fin = 70 MHz 5 C dbc Full dbc fin = 40 MHz 5 C dbc fin = 0 MHz 5 C dbc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fin =.4 MHz 5 C dbc fin = 70 MHz 5 C dbc Full dbc fin = 40 MHz 5 C dbc fin = 0 MHz 5 C dbc WORST OTHER HARMONIC OR SPUR fin =.4 MHz 5 C dbc fin = 70 MHz 5 C dbc Full 8 8 dbc fin = 40 MHz 5 C dbc fin = 0 MHz 5 C dbc TWO-TONE SFDR fin = 9. MHz, 3. MHz ( 7 dbfs) 5 C dbc fin = 69. MHz, 7. MHz ( 7 dbfs) 5 C 8 8 dbc CROSSTALK 3 Full db ANALOG INPUT BANDWIDTH 5 C MHz See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. See the Applications Information section for more information about the worst other specifications for the AD Crosstalk is measured at 00 MHz with dbfs on one channel and with no input on the alternate channel. Rev. 0 Page 7 of 84

8 ADC AC SPECIFICATIONS AD6655BCPZ-5/AD6655BCPZ-50 AVDD =.8 V, DVDD =.8 V, DRVDD =.8 V, maximum sample rate, VIN =.0 dbfs differential input,.0 V internal reference, DCS enabled, NCO enabled, half-band filter enabled, FIR filter enabled, unless otherwise noted. Table 4. AD6655BCPZ-5 AD6655BCPZ-50 Parameter Temperature Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR) fin =.4 MHz 5 C db fin = 70 MHz 5 C db Full db fin = 40 MHz 5 C db fin = 0 MHz 5 C db WORST SECOND OR THIRD HARMONIC fin =.4 MHz 5 C dbc fin = 70 MHz 5 C dbc Full dbc fin = 40 MHz 5 C dbc fin = 0 MHz 5 C dbc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fin =.4 MHz 5 C dbc fin = 70 MHz 5 C dbc Full dbc fin = 40 MHz 5 C dbc fin = 0 MHz 5 C dbc WORST OTHER HARMONIC OR SPUR fin =.4 MHz 5 C 9 87 dbc fin = 70 MHz 5 C dbc Full 8 80 dbc fin = 40 MHz 5 C dbc fin = 0 MHz 5 C dbc TWO-TONE SFDR fin = 9. MHz, 3. MHz ( 7 dbfs) 5 C dbc fin = 69. MHz, 7. MHz ( 7 dbfs) 5 C 8 8 dbc CROSSTALK 3 Full db ANALOG INPUT BANDWIDTH 5 C MHz See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. See the Applications Information section for more information about the worst other specifications for the AD Crosstalk is measured at 00 MHz with dbfs on one channel and with no input on the alternate channel. Rev. 0 Page 8 of 84

9 DIGITAL SPECIFICATIONS AD6655BCPZ-80/AD6655BCPZ-05 AVDD =.8 V, DVDD =.8 V, DRVDD =.8 V, maximum sample rate, VIN =.0 dbfs differential input,.0 V internal reference, DCS enabled, unless otherwise noted. AD6655 Table 5. AD6655BCPZ-80 AD6655BCPZ-05 Parameter Temp Min Typ Max Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK ) Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full.. V Differential Input Voltage Full V p-p Input Voltage Range Full AVDD 0.3 AVDD +.6 AVDD 0.3 AVDD +.6 V Input Common-Mode Range Full. AVDD. AVDD V High Level Input Voltage Full V Low Level Input Voltage Full V High Level Input Current Full μa Low Level Input Current Full μa Input Capacitance Full 4 4 pf Input Resistance Full kω SYNC INPUT Logic Compliance CMOS CMOS Internal Bias Full.. V Input Voltage Range Full AVDD 0.3 AVDD +.6 AVDD 0.3 AVDD +.6 V High Level Input Voltage Full V Low Level Input Voltage Full V High Level Input Current Full μa Low Level Input Current Full μa Input Capacitance Full 4 4 pf Input Resistance Full kω LOGIC INPUT (CSB) High Level Input Voltage Full V Low Level Input Voltage Full V High Level Input Current Full μa Low Level Input Current Full μa Input Resistance Full 6 6 kω Input Capacitance Full pf LOGIC INPUT (SCLK/DFS) High Level Input Voltage Full V Low Level Input Voltage Full V High Level Input Current Full μa Low Level Input Current Full μa Input Resistance Full 6 6 kω Input Capacitance Full pf LOGIC INPUTS (SDIO/DCS, SMI SDFS) High Level Input Voltage Full V Low Level Input Voltage Full V High Level Input Current Full μa Low Level Input Current Full μa Input Resistance Full 6 6 kω Input Capacitance Full 5 5 pf Rev. 0 Page 9 of 84

10 AD6655BCPZ-80 AD6655BCPZ-05 Parameter Temp Min Typ Max Min Typ Max Unit LOGIC INPUTS (SMI SDO/OEB, SMI SCLK/PDWN) High Level Input Voltage Full V Low Level Input Voltage Full V High Level Input Current Full μa Low Level Input Current Full μa Input Resistance Full 6 6 kω Input Capacitance Full 5 5 pf DIGITAL OUTPUTS CMOS Mode DRVDD = 3.3 V High Level Output Voltage IOH = 50 μa Full V IOH = 0.5 ma Full V Low Level Output Voltage IOL =.6 ma Full V IOL = 50 μa Full V CMOS Mode DRVDD =.8 V High Level Output Voltage IOH = 50 μa Full V IOH = 0.5 ma Full V Low Level Output Voltage IOL =.6 ma Full V IOL = 50 μa Full V LVDS Mode, DRVDD =.8 V Differential Output Voltage (VOD), Full mv ANSI Mode Output Offset Voltage (VOS), Full V ANSI Mode Differential Output Voltage (VOD), Full mv Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode Full V Pull up. Pull down. Rev. 0 Page 0 of 84

11 DIGITAL SPECIFICATIONS AD6655BCPZ-5/AD6655BCPZ-50 AD6655 AVDD =.8 V, DVDD =.8 V, DRVDD =.8 V, maximum sample rate, VIN =.0 dbfs differential input,.0 V internal reference, DCS enabled, unless otherwise noted. Table 6. AD6655BCPZ-5 AD6655BCPZ-50 Parameter Temp Min Typ Max Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK ) Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full.. V Differential Input Voltage Full V p-p Input Voltage Range Full AVDD 0.3 AVDD +.6 AVDD 0.3 AVDD +.6 V Input Common-Mode Range Full. V AVDD. V AVDD V High Level Input Voltage Full V Low Level Input Voltage Full V High Level Input Current Full μa Low Level Input Current Full μa Input Capacitance Full 4 4 pf Input Resistance Full kω SYNC INPUT Logic Compliance CMOS CMOS Internal Bias Full.. V Input Voltage Range Full AVDD 0.3 AVDD +.6 AVDD 0.3 AVDD +.6 V High Level Input Voltage Full V Low Level Input Voltage Full V High Level Input Current Full μa Low Level Input Current Full μa Input Capacitance Full 4 4 pf Input Resistance Full kω LOGIC INPUT (CSB) High Level Input Voltage Full V Low Level Input Voltage Full V High Level Input Current Full μa Low Level Input Current Full μa Input Resistance Full 6 6 kω Input Capacitance Full pf LOGIC INPUT (SCLK/DFS) High Level Input Voltage Full V Low Level Input Voltage Full V High Level Input Current Full μa Low Level Input Current Full μa Input Resistance Full 6 6 kω Input Capacitance Full pf LOGIC INPUTS (SDIO/DCS, SMI SDFS) High Level Input Voltage Full V Low Level Input Voltage Full V High Level Input Current Full μa Low Level Input Current Full μa Input Resistance Full 6 6 kω Input Capacitance Full 5 5 pf Rev. 0 Page of 84

12 AD6655BCPZ-5 AD6655BCPZ-50 Parameter Temp Min Typ Max Min Typ Max Unit LOGIC INPUTS (SMI SDO/OEB, SMI SCLK/PDWN) High Level Input Voltage Full V Low Level Input Voltage Full V High Level Input Current Full μa Low Level Input Current Full μa Input Resistance Full 6 6 kω Input Capacitance Full 5 5 pf DIGITAL OUTPUTS CMOS Mode DRVDD = 3.3 V High Level Output Voltage IOH = 50 μa Full V IOH = 0.5 ma Full V Low Level Output Voltage IOL =.6 ma Full V IOL = 50 μa Full V CMOS Mode DRVDD =.8 V High Level Output Voltage IOH = 50 μa Full V IOH = 0.5 ma Full V Low Level Output Voltage IOL =.6 ma Full V IOL = 50 μa Full V LVDS Mode DRVDD =.8 V Differential Output Voltage (VOD), Full mv ANSI Mode Output Offset Voltage (VOS), Full V ANSI Mode Differential Output Voltage (VOD), Full mv Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode Full V Pull up. Pull down. Rev. 0 Page of 84

13 SWITCHING SPECIFICATIONS AD6655BCPZ-80/AD6655BCPZ-05 AD6655 Table 7. AD6655BCPZ-80 AD6655BCPZ-05 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full MHz Conversion Rate DCS Enabled Full MSPS DCS Disabled Full MSPS CLK Period Divide-by- Mode (tclk) Full ns CLK Pulse Width High (tclkh) Divide-by- Mode, DCS Enabled Full ns Divide-by- Mode DCS Disabled Full ns Divide-by- Mode, DCS Enabled Full.6.6 ns Divide-by-3 Through Divide-by-8 Modes, DCS Enabled Full ns DATA OUTPUT PARAMETERS (DATA, FD) CMOS Noninterleaved Mode DRVDD =.8 V Data Propagation Delay (tpd) Full ns DCO Propagation Delay (tdco) Full ns Setup Time (ts) Full ns Hold Time (th) Full ns CMOS Noninterleaved Mode DRVDD = 3.3 V Data Propagation Delay (tpd) Full ns DCO Propagation Delay (tdco) Full ns Setup Time (ts) Full 4.. ns Hold Time (th) Full ns CMOS Interleaved and IQ Mode DRVDD =.8 V Data Propagation Delay (tpd) Full ns DCO Propagation Delay (tdco) Full ns Setup Time (ts) Full ns Hold Time (th) Full ns CMOS Interleaved and IQ Mode DRVDD = 3.3 V Data Propagation Delay (tpd) Full ns DCO Propagation Delay (tdco) Full ns Setup Time (ts) Full ns Hold Time (th) Full ns LVDS Mode DRVDD =.8 V Data Propagation Delay (tpd) Full ns DCO Propagation Delay (tdco) Full ns Pipeline Delay (Latency) NCO, FIR, fs/8 Mix Disabled Full Cycles Pipeline Delay (Latency) NCO Enabled, FIR and fs/8 Mix Disabled Full Cycles (Complex Output Mode) Pipeline Delay (Latency) NCO, FIR, and fs/8 Mix Enabled Full Cycles Aperture Delay (ta) Full.0.0 ns Aperture Uncertainty (Jitter, tj) Full ps rms Wake-Up Time 3 Full us OUT-OF-RANGE RECOVERY TIME Full Cycles Conversion rate is the clock rate after the divider. Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with a 5 pf load. 3 Wake-up time is dependent on the value of the decoupling capacitors. Rev. 0 Page 3 of 84

14 SWITCHING SPECIFICATIONS AD6655BCPZ-5/AD6655BCPZ-50 Table 8. AD6655BCPZ-5 AD6655BCPZ-50 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full MHz Conversion Rate DCS Enabled Full MSPS DCS Disabled Full MSPS CLK Period Divide-by- Mode (tclk) Full ns CLK Pulse Width High (tclkh) Divide-by- Mode, DCS Enabled Full ns Divide-by- Mode, DCS Disabled Full ns Divide-by- Mode, DCS Enabled Full.6.6 ns Divide-by-3 Through Divide-by-8 Modes, DCS Enabled Full ns DATA OUTPUT PARAMETERS (DATA, FD) CMOS Noninterleaved Mode DRVDD =.8 V Data Propagation Delay (tpd) Full ns DCO Propagation Delay (tdco) Full ns Setup Time (ts) Full ns Hold Time (th) Full ns CMOS Noninterleaved Mode DRVDD = 3.3 V Data Propagation Delay (tpd) Full ns DCO Propagation Delay (tdco) Full ns Setup Time (ts) Full ns Hold Time (th) Full ns CMOS Interleaved and IQ Mode DRVDD =.8 V Data Propagation Delay (tpd) Full ns DCO Propagation Delay (tdco) Full ns Setup Time (ts) Full ns Hold Time (th) Full ns CMOS Interleaved and IQ Mode DRVDD = 3.3 V Data Propagation Delay (tpd) Full ns DCO Propagation Delay (tdco) Full ns Setup Time (ts) Full ns Hold Time (th) Full.9.3 ns LVDS Mode DRVDD =.8 V Data Propagation Delay (tpd) Full ns DCO Propagation Delay (tdco) Full ns Pipeline Delay (Latency) NCO, FIR, fs/8 Mix Disabled Full Cycles Pipeline Delay (Latency) NCO Enabled; FIR and fs/8 Mix Disabled Full Cycles (Complex Output Mode) Pipeline Delay (Latency) NCO, FIR, and fs/8 Mix Enabled Full Cycles Aperture Delay (ta) Full.0.0 ns Aperture Uncertainty (Jitter, tj) Full ps rms Wake-Up Time 3 Full us OUT-OF-RANGE RECOVERY TIME Full 3 3 Cycles Conversion rate is the clock rate after the divider. Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with a 5 pf load. 3 Wake-up time is dependent on the value of the decoupling capacitors. Rev. 0 Page 4 of 84

15 TIMING SPECIFICATIONS Table 9. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS tssync SYNC to the rising edge of CLK setup time 0.4 ns thsync SYNC to the rising edge of CLK hold time 0.4 ns SPI TIMING REQUIREMENTS tds Setup time between the data and the rising edge of SCLK ns tdh Hold time between the data and the rising edge of SCLK ns tclk Period of the SCLK 40 ns ts Setup time between CSB and SCLK ns th Hold time between CSB and SCLK ns thigh Minimum period that SCLK should be in a logic high state 0 ns tlow Minimum period that SCLK should be in a logic low state 0 ns ten_sdio Time required for the SDIO pin to switch from an input to an output 0 ns relative to the SCLK falling edge tdis_sdio Time required for the SDIO pin to switch from an output to an input 0 ns relative to the SCLK rising edge SPORT TIMING REQUIREMENTS tcssclk Delay from rising edge of CLK+ to rising edge of SMI SCLK ns tsslksdo Delay from rising edge of SMI SCLK to SMI SDO ns tssclksdfs Delay from rising edge of SMI SCLK to SMI SDFS ns Timing Diagrams CLK+ t PD t DCO DECIMATED CMOS DATA CHANNEL A/B DATA BITS CHANNEL A/B DATA BITS CHANNEL A/B DATA BITS DECIMATED FD DATA CHANNEL A/B FD BITS CHANNEL A/B FD BITS CHANNEL A/B FD BITS CHANNEL A/B FD BITS CHANNEL A/B FD BITS CHANNEL A/B FD BITS t S DECIMATED DCOA/DCOB t H Figure. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000) CLK+ t PD t DCO DECIMATED CMOS DATA CHANNEL A/B DATA BITS CHANNEL A/B DATA BITS CHANNEL A/B DATA BITS DECIMATED FD DATA CHANNEL A/B FD BITS CHANNEL A/B FD BITS CHANNEL A/B FD BITS t S DECIMATED DCOA/DCOB t H Figure 3. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 00 Through Fast Detect Mode Select Bits = 00) Rev. 0 Page 5 of 84

16 CLK+ t PD t DCO DECIMATED INTERLEAVED CMOS DATA CHANNEL A: DATA CHANNEL B: DATA CHANNEL A: DATA CHANNEL B: DATA CHANNEL A: DATA CHANNEL B: DATA DECIMATED INTERLEAVED FD DATA CHANNEL A: FD BITS CHANNEL B: FD BITS CHANNEL A: FD BITS CHANNEL B: FD BITS CHANNEL A: FD BITS CHANNEL B: FD BITS t S DECIMATED DCO t H Figure 4. Decimated Interleaved CMOS Mode Data and Fast Detect Output Timing CLK+ t PD t DCO DECIMATED CMOS IQ OUTPUT DATA CHANNEL A/B: Q DATA CHANNEL A/B: I DATA CHANNEL A/B: Q DATA CHANNEL A/B: I DATA CHANNEL A/B: Q DATA CHANNEL A/B: I DATA CMOS FD DATA CHANNEL A/B: FD BITS CHANNEL A/B: FD BITS CHANNEL A/B: FD BITS CHANNEL A/B: FD BITS CHANNEL A/B: FD BITS CHANNEL A/B: FD BITS t S DECIMATED DCOA/DCOB t H Figure 5. Decimated IQ Mode CMOS Data and Fast Detect Output Timing CLK CLK+ t PD LVDS DATA CHANNEL A: DATA CHANNEL B: DATA CHANNEL A: DATA CHANNEL B: DATA CHANNEL A: DATA LVDS FAST DET CHANNEL A: FD CHANNEL B: FD CHANNEL A: FD CHANNEL B: FD CHANNEL A: FD DCO t DCO DCO+ Figure 6. Decimated Interleaved LVDS Mode Data and Fast Detect Output Timing CLK+ t SSYNC t HSYNC SYNC Figure 7. SYNC Timing Inputs Rev. 0 Page 6 of 84

17 CLK+ CLK t CSSCLK SMI SCLK t SSCLKSDFS t SSCLKSDFS SMI SDFS SMI SDO DATA DATA Figure 8. Signal Monitor SPORT Output Timing Rev. 0 Page 7 of 84

18 ABSOLUTE MAXIMUM RATINGS Table 0. Parameter ELECTRICAL AVDD, DVDD to AGND DRVDD to DRGND AGND to DRGND VIN+A/VIN+B, VIN-A/VIN B to AGND CLK+, CLK to AGND SYNC to AGND VREF to AGND SENSE to AGND CML to AGND RBIAS to AGND CSB to AGND SCLK/DFS to DRGND SDIO/DCS to DRGND SMI SDO/OEB to DRGND SMI SCLK/PDWN to DRGND SMI SDFS to DRGND D0A/D0B through D3A/D3B to DRGND FD0A/FD0B through FD3A/FD3B to DRGND DCOA/DCOB to DRGND ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating 0.3 V to +.0 V 0.3 V to +3.9 V 0.3 V to +0.3 V 0.3 V to AVDD + 0. V 0.3 V to +3.9 V 0.3 V to +3.9 V 0.3 V to AVDD + 0. V 0.3 V to AVDD + 0. V 0.3 V to AVDD + 0. V 0.3 V to AVDD + 0. V 0.3 V to +3.9 V 0.3 V to +3.9 V 0.3 V to DRVDD V 0.3 V to DRVDD V 0.3 V to DRVDD V 0.3 V to DRVDD V 0.3 V to DRVDD V 0.3 V to DRVDD V 0.3 V to DRVDD V 40 C to +85 C 50 C 65 C to +5 C THERMAL CHARACTERISTICS The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. Table. Thermal Resistance Package Type 64-Lead LFCSP 9 mm 9 mm (CP-64-3) Airflow Velocity (m/s) θja, θjc, 3 θjb, 4 Unit C/W C/W C/W Per JEDEC 5-7, plus JEDEC 5-5 SP test board. Per JEDEC JESD5- (still air) or JEDEC JESD5-6 (moving air). 3 Per MIL-Std 883, Method Per JEDEC JESD5-8 (still air). Typical θja is specified for a 4-layer PCB with solid ground plane. As shown, airflow increases heat dissipation, which reduces θja. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the θja. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 Page 8 of 84

19 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DRGND D5B D4B D3B DB DB D0B (LSB) DVDD FD3B FDB FDB FD0B SYNC CSB CLK CLK+ DRVDD D6B D7B 3 D8B 4 D9B 5 D0B 6 DB 7 DB 8 D3B (MSB) 9 DCOB 0 DCOA D0A (LSB) DA 3 DA 4 D3A 5 D4A 6 PIN INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD6655 PARALLEL CMOS TOP VIEW (Not to Scale) 48 SCLK/DFS 47 SDIO/DCS 46 AVDD 45 AVDD 44 VIN+B 43 VIN B 4 RBIAS 4 CML 40 SENSE 39 VREF 38 VIN A 37 VIN+A 36 AVDD 35 SMI SDFS 34 SMI SCLK/PDWN 33 SMI SDO/OEB D5A D6A D7A DRGND DRVDD D8A D9A DVDD D0A DA DA D3A (MSB) FD0A FDA FDA FD3A Figure 9. LFCSP Parallel CMOS Pin Configuration (Top View) Table. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 0, 64 DRGND Ground Digital Output Ground., DRVDD Supply Digital Output Driver Supply (.8 V to 3.3 V). 4, 57 DVDD Supply Digital Power Supply (.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (.8 V Nominal). 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. ADC Analog 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN A Input Differential Analog Input Pin ( ) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN B Input Differential Analog Input Pin ( ) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select. (See Table 5 for details.) 4 RBIAS Input/Output External Reference Bias Resistor. 4 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input True. 50 CLK Input ADC Clock Input Complement. ADC Fast Detect Outputs 9 FD0A Output Channel A Fast Detect Indicator. (See Table for details.) 30 FDA Output Channel A Fast Detect Indicator. (See Table for details.) 3 FDA Output Channel A Fast Detect Indicator. (See Table for details.) 3 FD3A Output Channel A Fast Detect Indicator. (See Table for details.) 53 FD0B Output Channel B Fast Detect Indicator. (See Table for details.) 54 FDB Output Channel B Fast Detect Indicator. (See Table for details.) 55 FDB Output Channel B Fast Detect Indicator. (See Table for details.) 56 FD3B Output Channel B Fast Detect Indicator. (See Table for details.) Digital Input 5 SYNC Input Digital Synchronization Pin. Slave mode only. Rev. 0 Page 9 of 84

20 Pin No. Mnemonic Type Description Digital Outputs D0A (LSB) Output Channel A CMOS Output Data. 3 DA Output Channel A CMOS Output Data. 4 DA Output Channel A CMOS Output Data. 5 D3A Output Channel A CMOS Output Data. 6 D4A Output Channel A CMOS Output Data. 7 D5A Output Channel A CMOS Output Data. 8 D6A Output Channel A CMOS Output Data. 9 D7A Output Channel A CMOS Output Data. D8A Output Channel A CMOS Output Data. 3 D9A Output Channel A CMOS Output Data. 5 D0A Output Channel A CMOS Output Data. 6 DA Output Channel A CMOS Output Data. 7 DA Output Channel A CMOS Output Data. 8 D3A (MSB) Output Channel A CMOS Output Data. 58 D0B (LSB) Output Channel B CMOS Output Data. 59 DB Output Channel B CMOS Output Data. 60 DB Output Channel B CMOS Output Data. 6 D3B Output Channel B CMOS Output Data. 6 D4B Output Channel B CMOS Output Data. 63 D5B Output Channel B CMOS Output Data. D6B Output Channel B CMOS Output Data. 3 D7B Output Channel B CMOS Output Data. 4 D8B Output Channel B CMOS Output Data. 5 D9B Output Channel B CMOS Output Data. 6 D0B Output Channel B CMOS Output Data. 7 DB Output Channel B CMOS Output Data. 8 DB Output Channel B CMOS Output Data. 9 D3B (MSB) Output Channel B CMOS Output Data. DCOA Output Channel A Data Clock Output. 0 DCOB Output Channel B Data Clock Output. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 5 CSB Input SPI Chip Select. Active low. Signal Monitor Port 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input (Active High) in External Pin Mode. Rev. 0 Page 0 of 84

21 PIN INDICATOR DRGND D0+ (LSB) D0 (LSB) FD3+ FD3 FD+ FD DVDD FD+ FD FD0+ FD0 SYNC CSB CLK CLK+ DRVDD D D+ 3 D 4 D+ 5 D3 6 D3+ 7 D4 8 D4+ 9 DCO 0 DCO+ D5 D5+ 3 D6 4 D6+ 5 D7 6 EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD6655 PARALLEL LVDS TOP VIEW (Not to Scale) 48 SCLK/DFS 47 SDIO/DCS 46 AVDD 45 AVDD 44 VIN+B 43 VIN B 4 RBIAS 4 CML 40 SENSE 39 VREF 38 VIN A 37 VIN+A 36 AVDD 35 SMI SDFS 34 SMI SCLK/PDWN 33 SMI SDO/OEB D7+ D8 D8+ DRGND DRVDD D9 D9+ DVDD D0 D0+ D D+ D D+ D3 (MSB) D3+ (MSB) Figure 0. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View) Table 3. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 0, 64 DRGND Ground Digital Output Ground., DRVDD Supply Digital Output Driver Supply (.8 V to 3.3 V). 4, 57 DVDD Supply Digital Power Supply (.8 V Nominal.) 36, 45, 46 AVDD Supply Analog Power Supply (.8 V Nominal.) 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. ADC Analog 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN A Input Differential Analog Input Pin ( ) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN B Input Differential Analog Input Pin ( ) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select. See Table 5 for details. 4 RBIAS Input/Output External Reference Bias Resistor. 4 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input True. 50 CLK Input ADC Clock Input Complement. ADC Fast Detect Outputs 54 FD0+ Output Channel A/Channel B LVDS Fast Detect Indicator 0 True. See Table for details. 53 FD0- Output Channel A/Channel B LVDS Fast Detect Indicator 0 Complement. See Table for details. 56 FD+ Output Channel A/Channel B LVDS Fast Detect Indicator True. See Table for details. 55 FD Output Channel A/Channel B LVDS Fast Detect Indicator Complement. See Table for details. 59 FD+ Output Channel A/Channel B LVDS Fast Detect Indicator True See Table for details. 58 FD Output Channel A/Channel B LVDS Fast Detect Indicator Complement. See Table for details. 6 FD3+ Output Channel A/Channel B LVDS Fast Detect Indicator 3 True. See Table for details. 60 FD3 Output Channel A/Channel B LVDS Fast Detect Indicator 3 Complement. See Table for details. Rev. 0 Page of 84

22 Pin No. Mnemonic Type Description Digital Input 5 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 63 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0 True. 6 D0 (LSB) Output Channel A/Channel B LVDS Output Data 0 Complement. 3 D+ Output Channel A/Channel B LVDS Output Data True. D Output Channel A/Channel B LVDS Output Data Complement. 5 D+ Output Channel A/Channel B LVDS Output Data True. 4 D Output Channel A/Channel B LVDS Output Data Complement. 7 D3+ Output Channel A/Channel B LVDS Output Data 3 True. 6 D3 Output Channel A/Channel B LVDS Output Data 3 Complement. 9 D4+ Output Channel A/Channel B LVDS Output Data 4 True. 8 D4 Output Channel A/Channel B LVDS Output Data 4 Complement. 3 D5+ Output Channel A/Channel B LVDS Output Data 5 True. D5 Output Channel A/Channel B LVDS Output Data 5 Complement. 5 D6+ Output Channel A/Channel B LVDS Output Data 6 True. 4 D6 Output Channel A/Channel B LVDS Output Data 6 Complement. 7 D7+ Output Channel A/Channel B LVDS Output Data 7 True. 6 D7 Output Channel A/Channel B LVDS Output Data 7 Complement. 9 D8+ Output Channel A/Channel B LVDS Output Data 8 True. 8 D8 Output Channel A/Channel B LVDS Output Data 8 Complement. 3 D9+ Output Channel A/Channel B LVDS Output Data 9 True. D9 Output Channel A/Channel B LVDS Output Data 9 Complement. 6 D0+ Output Channel A/Channel B LVDS Output Data 0 True. 5 D0 Output Channel A/Channel B LVDS Output Data 0 Complement. 8 D+ Output Channel A/Channel B LVDS Output Data True. 7 D Output Channel A/Channel B LVDS Output Data Complement. 30 D+ Output Channel A/Channel B LVDS Output Data True. 9 D Output Channel A/Channel B LVDS Output Data Complement. 3 D3+ (MSB) Output Channel A/Channel B LVDS Output Data 3 True. 3 D3 (MSB) Output Channel A/Channel B LVDS Output Data 3 Complement. DCO+ Output Channel A/Channel B LVDS Data Clock Output True. 0 DCO Output Channel A/Channel B LVDS Data Clock Output Complement. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode. 5 CSB Input SPI Chip Select (Active Low). Signal Monitor Port 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input (Active High) in External Pin Mode Rev. 0 Page of 84

23 EQUIVALENT CIRCUITS VIN SCLK/DFS 6kΩ kω Figure. Equivalent Analog Input Circuit AVDD CLK+ 0kΩ.V 0kΩ CLK Figure. Equivalent Clock lnput Circuit DRVDD DRGND Figure 3. Equivalent Digital Output Circuit DRVDD SDIO/DCS DRVDD 6kΩ kω Figure 5. Equivalent SCLK/DFS Input Circuit SENSE kω Figure 6. Equivalent SENSE Circuit CSB AVDD 6kΩ kω Figure 7. Equivalent CSB Input Circuit AVDD VREF 6kΩ Figure 4. Equivalent SDIO/DCS Circuit or SMI SDFS Circuit Figure 8. Equivalent VREF Circuit. Rev. 0 Page 3 of 84

24 TYPICAL PERFORMANCE CHARACTERISTICS AVDD =.8 V, DVDD =.8 V, DRVDD =.8 V, sample rate = 50 MSPS, DCS enabled,.0 V internal reference, V p-p differential input, VIN =.0 dbfs, 64k sample, TA = 5 C, NCO enabled, FIR filter enabled, unless otherwise noted. In the FFT plots that follow, the location of the second and third harmonics is noted when they fall in the pass band of the filter. AMPLITUDE (dbfs) SECOND HARMONIC THIRD HARMONIC dbfs SNR = 74.7dBc (75.7dBFS) SFDR = 86.5dBc f NCO = 8.75MHz AMPLITUDE (dbfs) MSPS dbfs SNR = 73.7dBc (74.7dBFS) SFDR = 8.8dBc f NCO = 6MHz THIRD HARMONIC SECOND HARMONIC FREQUENCY (MHz) Figure 9. AD Single-Tone FFT with fin =.4 MHz, fnco = 8.75 MHz FREQUENCY (MHz) Figure. AD Single-Tone FFT with fin = 40. MHz, fnco = 6 MHz AMPLITUDE (dbfs) MSPS dbfs SNR = 74.8dBc (75.8dBFS) SFDR = 00dBc f NCO = 4MHz AMPLITUDE (dbfs) MSPS dbfs SNR = 7.8dBc (7.8dBFS) SFDR = 8.4dBc f NCO = 05MHz THIRD HARMONIC FREQUENCY (MHz) Figure 0. AD Single-Tone FFT with fin = 30.3 MHz, fnco = 4 MHz FREQUENCY (MHz) Figure 3. AD Single-Tone FFT with fin = 0. MHz, fnco = 05 MHz AMPLITUDE (dbfs) MSPS dbfs SNR = 74.3dBc (75.3dBFS) SFDR = 83.3dBc f NCO = 56MHz THIRD HARMONIC AMPLITUDE (dbfs) MSPS dbfs SNR = 7.7dBc (7.7dBFS) SFDR = 95.0dBc f NCO = 3.5MHz FREQUENCY (MHz) Figure. AD Single-Tone FFT with fin = 70. MHz, fnco = 56 MHz FREQUENCY (MHz) Figure 4. AD Single-Tone FFT with fin = 33. MHz, fnco = 3.5 MHz Rev. 0 Page 4 of 84

25 AMPLITUDE (dbfs) MSPS dbfs SNR = 67.4dBc (65.4dBFS) SFDR = 74.dBc f NCO = 49MHz THIRD HARMONIC SECOND HARMONIC AMPLITUDE (dbfs) MSPS dbfs SNR = 74.6dBc (75.6dBFS) SFDR = 86.dBc f NCO = 78MHz THIRD HARMONIC FREQUENCY (MHz) Figure 5. AD Single-Tone FFT with fin = 445. MHz, fnco = 49 MHz FREQUENCY (MHz) Figure 8. AD Single-Tone FFT with fin = 70.3 MHz, fnco = 78 MHz AMPLITUDE (dbfs) SECOND HARMONIC THIRD HARMONIC dbfs SNR = 74.5dBc (75.5dBFS) SFDR = 87.8dBc f NCO = 5.75MHz AMPLITUDE (dbfs) MSPS dbfs SNR = 74.dBc (75.dBFS) SFDR = 90.3dBc f NCO = 4MHz THIRD HARMONIC FREQUENCY (MHz) Figure 6. AD Single-Tone FFT with fin =.4 MHz, fnco = 5.75 MHz FREQUENCY (MHz) Figure 9. AD Single-Tone FFT with fin = 40. MHz, fnco = 4 MHz AMPLITUDE (dbfs) MSPS dbfs SNR = 74.7dBc (75.7dBFS) SFDR = 89.6dBc f NCO = MHz THIRD HARMONIC AMPLITUDE (dbfs) MSPS dbfs SNR = 73.4dBc (74.4dBFS) SFDR = 90.dBc f NCO = 3MHz FREQUENCY (MHz) Figure 7. AD Single-Tone FFT with fin = 30.3 MHz, fnco = MHz FREQUENCY (MHz) Figure 30. AD Single-Tone FFT with fin = 0. MHz, fnco = 3 MHz Rev. 0 Page 5 of 84

26 SFDR (dbfs) 90 SFDR = +85 C SNR/SFDR (dbc AND dbfs) SNR (dbfs) SFDR (dbc) SNR (dbc) 85dB REFERENCE LINE SNR/SFDR (dbc) SFDR = 40 C SNR = +5 C SNR = +85 C SNR = 40 C SFDR = +5 C INPUT AMPLITUDE (dbfs) Figure 3. AD Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fin =.4 MHz, fnco = 8.75 MHz INPUT FREQUENCY (MHz) Figure 34. AD Single-Tone SNR/SFDR vs. Input Frequency (fin) and Temperature with DRVDD = 3.3 V SFDR (dbfs) SNR/SFDR (dbc AND dbfs) SNR (dbfs) SFDR (dbc) 85dB REFERENCE LINE GAIN ERROR (%FSR) OFFSET GAIN OFFSET ERROR (%FSR) SNR (dbc) INPUT AMPLITUDE (dbfs) Figure 3. AD Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fin = 98. MHz, fnco = MHz TEMPERATURE ( C) Figure 35. AD Gain and Offset vs. Temperature SNR/SFDR (dbc) SFDR = +85 C SFDR = 40 C SNR = +5 C SNR = +85 C SNR = 40 C SFDR = +5 C SFDR/IMD3 (dbc AND dbfs) SFDR (dbc) IMD3 (dbc) SFDR (dbfs) IMD3 (dbfs) INPUT FREQUENCY (MHz) Figure 33. AD Single-Tone SNR/SFDR vs. Input Frequency (fin) and Temperature with DRVDD =.8 V INPUT AMPLITUDE (dbfs) Figure 36. AD Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fin = 9. MHz, fin = 3. MHz, fs = 50 MSPS, fnco = MHz Rev. 0 Page 6 of 84

27 SFDR/IMD3 (dbc AND dbfs) SFDR (dbc) IMD3 (dbc) SFDR (dbfs) IMD3 (dbfs) AMPLITUDE (dbfs) MSPS 7dBFS 7dBFS SFDR = 85.5dBc (9.5dBFS) f NCO = 77MHz INPUT AMPLITUDE (dbfs) Figure 37. AD Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fin = 69. MHz, fin = 7. MHz, fs = 50 MSPS, fnco = 77 MHz FREQUENCY (MHz) Figure 40. AD Two Tone FFT with fin = 69. MHz, fin = 7. MHz, fs = 50 MSPS, fnco = 77 MHz NPR = 64.5dBc 8.5MHz NOTCH WIDTH = 3MHz AMPLITUDE (dbfs) AMPLITUDE (dbfs) FREQUENCY (MHz) Figure 38. AD6655-5, Two 64k WCDMA Carriers with fin = 70 MHz, fs =.88 MHz, fnco = MHz FREQUENCY (MHz) Figure 4. AD Noise Power Ratio (NPR) AMPLITUDE (dbfs) MSPS 7dBFS 7dBFS SFDR = 89.dBc (96.dBFS) f NCO = MHz SNR/SFDR (dbc) SFDR (dbc) SNR (dbc) FREQUENCY (MHz) Figure 39. AD Two-Tone FFT with fin = 9. MHz, fin = 3. MHz, fs = 50 MSPS, fnco = MHz SAMPLE RATE (MSPS) Figure 4. AD Single-Tone SNR/SFDR vs. Sample Rate (fs) with fin =.3 MHz Rev. 0 Page 7 of 84

28 0.85 LSB rms NUMBER OF HITS (M) SNR/SFDR (dbc) SFDR SNR N 3 N N N N + N + N + 3 OUTPUT CODE Figure 43. AD6655 Grounded Input Histogram INPUT COMMON-MODE VOLTAGE (V) Figure 45. AD SNR/SFDR vs. Input Common Mode (VCM) with fin = 30.3 MHz, fnco = 45 MHz SNR/SFDR (dbc) SFDR DCS ON SNR DCS ON SFDR DCS OFF SNR DCS OFF DUTY CYCLE (%) Figure 44. AD SNR/SFDR vs. Duty Cycle with fin = 30.3 MHz, fnco = 45 MHz Rev. 0 Page 8 of 84

29 THEORY OF OPERATION The AD6655 has two analog input channels, two decimating channels, and two digital output channels. The intermediate frequency (IF) input signal passes through several stages before appearing at the output port(s) as a filtered, decimated digital signal. The dual ADC design can be used for diversity reception of signals, where the ADCs operate identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fs/ frequency segment from dc to 50 MHz using appropriate lowpass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 450 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion. In nondiversity applications, the AD6655 can be used as a baseband receiver, where one ADC is used for I input data, and the other is used for Q input data. Synchronization capability is provided to allow synchronized timing between multiple channels or multiple devices. The NCO phase can be set to produce a known offset relative to another channel or device. Programming and control of the AD6655 are accomplished using a 3-bit SPI-compatible serial interface. ADC ARCHITECTURE AD6655 architecture consists of a front-end sample-and-hold amplifier (SHA) followed by a pipelined, switched-capacitor ADC. The quantized outputs from each stage are combined into a final 4-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage of each channel contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. ANALOG INPUT CONSIDERATIONS The analog input to the AD6655 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. The clock signal alternatively switches the SHA between sample mode and hold mode (see Figure 46). When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within / of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. In IF undersampling applications, any shunt capacitors should be reduced. In combination with the driving source impedance, the shunt capacitors limit the input bandwidth. Refer to Application Note AN-74, Frequency Domain Response of Switched- Capacitor ADCs; Application Note AN-87, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, Transformer-Coupled Front-End for Wideband A/D Converters, for more information on this subject (see In general, the precise values are dependent on the application. VIN+ C PIN, PAR VIN C PIN, PAR S S H C S C S S C H C H S Figure 46. Switched-Capacitor SHA Input For best dynamic performance, the source impedances driving VIN+ and VIN should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal differential reference buffer creates positive and negative reference voltages that define the input span of the ADC core. The output common mode of the reference buffer is set to VCMREF (approximately.6 V). Input Common Mode The analog inputs of the AD6655 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = 0.55 AVDD is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 45) Rev. 0 Page 9 of 84