Analysis and Compensation of Dead-Time Effect of a ZVT PWM Inverter Considering the Rise- and Fall-Times

Transcription

1 applied cience Article Analyi and Compenation of Dead-Time Effect of a ZVT PWM Inverter Conidering Rie- and Fall-Time Hailin Zhang, Baoquan Kou *, Lu Zhang and He Zhang Department of Electrical Engineering, Harbin Intitute of Technology, Harbin , China; zhanghailin0310@ina.com (Ha.Z.); zhanglu24@hit.edu.cn (L.Z.); antonyamanda@163.com (He.Z.) * Correpondence: koubq@hit.edu.cn; Tel.: Academic Editor: Wen-Hiang Hieh Received: 5 October 2016; Accepted: 4 November 2016; Publihed: 9 November 2016 Abtract: The dead-time, a an intrinic problem of converter baed on half-bridge unit, lead to ditortion in converter output. Although everal dead-time compenation or elimination method have been propoed, y cannot fully remove dead-time of blanking delay error, becaue output current polarity i difficult detect accurately. Thi paper utilize zero-voltage-witching (ZVT) technique to eliminate blanking delay error, which i main drawback of hard-witching inverter, although technique initially aim to improve efficiency. A typical ZVT inverter auxiliary reonant nubber inverter (ARSI) i analyzed. The blanking delay error i completely eliminated in ARSI. Anor error ource caued by finite rie- and fall-time of voltage i analyzed, which wa not conidered in hard-witching inverter. A compenation method baed on voltage error etimation i propoed to compenate rie- and fall-error. A prototype wa developed to verify ivene of propoed control. Both imulation and experimental reult demontrate that qualitie of output current and voltage in ARSI are better than that in hard-witching inverter due to elimination of blanking delay error. The total harmonic ditortion (THD) of output i furr reduced by uing propoed compenation method in ARSI. Keyword: dead-time ; zero-voltage-witching (ZVT); auxiliary reonant nubber inverter (ARSI) 1. Introduction The half-bridge, a a baic unit, employ two tacked emiconductor witche connected acro DC voltage to realize energy tranfer. In AC-DC or DC-AC application, mot of converter conit of half-bridge, uch a full-bridge converter and three-phae converter. The two witche in a half-bridge are complementarily conducted. Due to turn-on and turn-off delay and finite rie-time and fall-time during commutation, a dead-time i inerted between turn-on and turn-off of witche to avoid hort circuiting. Thi reult in a current-dependent witching node voltage during dead-time, which increae output ditortion. To date, extenive tudie have focued on problem of dead-time. Mot of compenation and elimination method can be divided into three categorie: pule-baed compenation [1,2], voltage feedforward compenation [3,4] and dead-time elimination [5 7]. For pule-baed compenation method, dead-time i modeled a a pule hift error. A dead-time width pule i added or reduced baed on hift error to compenate dead-time [1,2]. For voltage feedforward compenation, dead-time i modeled a an average voltage error, which i regarded a a diturbance to output voltage. The voltage error i added to Appl. Sci. 2016, 6, 344; doi: /app

2 Appl. Sci. 2016, 6, of 17 reference voltage directly to compenate dead-time [3,4]. For dead-time elimination method, driving ignal i only put on one witch, wherea driving ignal of or witch i removed. The body diode conduct current. Therefore, dead-time i not required in thi method [5 7]. Theoretically, e three method can fully compenate or eliminate dead-time. In practice, however, reult depend on detection preciion of output current polarity. Due to output current ripple and zero current clamping, output current polarity i difficult to detect accurately. Moreover, beyond three method, ome or method employing proper current control are propoed to olve problem of dead-time [8 11]. However, e technique are till not capable of completely removing dead-time. In half-bridge circuit, voltage and current tranition can be turn-off controlled or turn-on controlled, which i influenced by output current polarity. The turn-off controlled type refer to cae that commutation i triggered by turn-off of witche. Thu, body diode of next turn-on witche are conducted during dead-time, wherea turn-on controlled type refer to cae that commutation i triggered by turn-on of witche. Different commutation type lead to different voltage error caued by dead-time. Thi kind of dead-time i blanking delay error, which i main error in half-bridge-baed topology [12]. Eentially, commutation type, which i related to output current polarity, make dead-time difficult to remove completely. Zero-voltage-witching (ZVT) oft-witching technique can be ued to eliminate blanking delay error, although technique aim to reduce witching lo and improve efficiency. The tranition are all turn-off controlled in ZVT oft-witching converter with conduction of anti-parallel diode during dead-time, which i irrelevant to output current. Therefore, dead-time of blanking delay error can be completely removed by uing ZVT oft-witching technique. Until now, everal topologie of ZVT pule-width-modulation (PWM) inverter have been propoed. The auxiliary reonant commutated pole inverter (ARCPI) ha been propoed with two auxiliary witche per phae [13,14]. The ARCPI can meet demand for high efficiency, a well a low voltage and current tree. However, major drawback i exitence of plit capacitor, which caue capacitor charge unbalance. The auxiliary reonant nubber inverter (ARSI) ha been propoed to eliminate plit capacitor, but three-phae topology cannot utilize conventional pace-vector-pule-width modulation (SVPWM) [15,16]. Thu, y are more uitable for permanent magnet bruhle DC motor than all type of motor. The ingle-phae topology i very attractive with only two auxiliary witche well fit to conventional PWM. Meanwhile, ZVT inverter uing coupled magnetic ha been propoed to eliminate plit capacitor [17 19]. However, e topologie need coupled inductor and a large number of auxiliary witche, which unfortunately increae cot and difficulty of circuit realization. The ZVT PWM converter ha been ynized and ummarized in [20,21]. Without adding external reonant capacitor, ZVT inverter can completely remove dead-time. However, external reonant capacitor are alway required to reduce voltage changing rate of witche, o that turn-off lo and electromagnetic interference (EMI) can be reduced. Thi will lead to output voltage ditortion, which i caued by finite commutation time. Thi kind of dead-time i quite different from that in hard-witching inverter. Thu, thi paper analyze dead-time of a typical example of ZVT PWM oft-witching inverter ARSI. Then, a compenation method i propoed to remove dead-time. Finally, imulation and experiment are undertaken to verify ivene of propoed method. 2. Dead-Time Effect of Auxiliary Reonant Snubber Inverter (ARSI) 2.1. Principle 1 depict ingle-phae ARSI topology analyzed in thi paper, which conit of a tandard H-bridge inverter, reonant capacitor and an auxiliary circuit. With a proper operation of

3 Appl. Sci. 2016, 6, of 17 auxiliary witche, S r1 and S r2, zero-voltage-witching (ZVS) condition of main witche, S 1 -S 4, can be created. Meanwhile, auxiliary witche can realize zero-current witching (ZCS). Appl. Sci. 2016, 6, of Circuit of auxiliary reonant nubber inverter. In order to realize oft witching for entire load range and maintain low auxiliary current, In order to realize oft-witching for entire load range and maintain a low auxiliary current, ARSI operate in two mode of heavy load mode (HLM) and light load mode (), a ARSI operate in two mode of heavy load mode (HLM) and light load mode (), a determined determined by load condition [22]. In heavy load condition, auxiliary circuit i only by load condition [22]. In heavy load condition, auxiliary circuit i only operated once operated once in each witching period, thu achieving auxiliary ZVS (AZVS) of a et of witche. in each witching period, thu achieving auxiliary ZVS (AZVS) of a et of witche. The or et of The or et of witche can achieve natural ZVS (NZVS) without operation of auxiliary circuit. witche can achieve natural ZVS (NZVS) without operation of auxiliary circuit. In light load In light load condition, auxiliary circuit i operated twice in each witching period. Therefore, condition, auxiliary circuit i operated twice in each witching period. Therefore, all witche all witche achieve AZVS. achieve AZVS. The operating principle of ARSI i introduced in [22]. The detailed dead time of The operating principle of ARSI i introduced in [22]. The detailed dead-time of and HLM will be analyzed in cae of poitive load current a follow. When load current i and HLM will be analyzed in cae of poitive load current a follow. When load current i negative, operation i imilar. negative, operation i imilar. To analyze circuit, we aume that To analyze circuit, we aume that (1) All component and device are ideal; (1) (2) The All component gate ignal of and device MOSFET are ideal; are ideal quare wave; (2) (3) Theoutput gate ignal inductor of Lo MOSFET i high enough are ideal to be quare-wave; a contant current ource. (3) The output inductor L o i high enough to be a contant current ource Heavy Load Condition Heavy Load Condition In heavy load condition, AZVS + NZVS, namely achieving AZVS of a et of witche and NZVS Inof heavy or load et condition, of witche, AZVS i realized. + NZVS, One namely witching achieving cycle of AZVS operating of a et of waveform witche and are hown NZVS of in or 2, et where of witche, vd i idrain ource realized. One voltage witching of a cycle MOSFET, of id operating i drain waveform current of are a MOSFET, hown in vg i 2, actual wheregate v d i ignal drain-ource with dead time, voltage vg,id i of a MOSFET, ideal gate i d ignal, i drain ilr i current reonant of a inductor MOSFET, current, v g i vab actual i gate actual ignal pole with voltage dead-time, acro v g,id load i with ideal dead time, gate ignal, vab,id i Lr i i ideal reonant pole voltage inductoracro current, vload ab i and actual verr i pole voltage error acro between load vab with and vab,id. dead-time, v ab,id i ideal pole voltage During acro dead time load and vth1 th3, err i voltage reonant errorcapacitor between v ab firt andreonate v ab,id. with load inductor. Owing During to poitive dead-time load t H1 current, t H3, Cr2 reonant and Cr3 are capacitor dicharged firt reonate and Cr1 and withcr4 are loadcharged. inductor. After Owing Cr2 and to Cr3 poitive are dicharged load current, to zero voltage C r2 and Cat r3 th2, are dicharged body diode and D2 C r1 andd3 C r4 conduct are charged. current Afterand C r2 n and C r3 voltage are dicharged clamped to zero-voltage to zero. Thu, ats2 t H2 and, S3 body can be diode turned Don 2 and at D 3 ZVS conduct condition. current Regarding and n dead time voltageth1 th3, i clamped it conit to zero. of Thu, reonant S 2 and Stage 3 canand be turned diode on clamping at ZVS tage. condition. The dead time Regarding caue dead-time pole voltage t H1 t H3 error., it conit A for of ARSI, reonant voltage tage and error diode only clamping occur tage. reonant The dead-time tage, which caue i caued poleby voltage finite error. rie Aand forfall time ARSI, of voltage. error only occur in reonant tage, which i caued During by finite reonant rie- and tage fall-time th1 th2, of actual voltage. pole voltage can be obtained a follow: During reonant tage t H1 t H2, actual pole voltage can be obtained a follow: io v () t V ( t t ) ab H1 (1) C v r ab (t) = V i o (t t C H1 ) (1) r Converely, ideal pole voltage hould be a follow: v () t V ab, id (2) Thu, voltage error can be given a follow:

4 Appl. Sci. 2016, 6, of 17 Converely, ideal pole voltage hould be a follow: v ab,id (t) = V (2) Appl. Sci. 2016, 6, of 17 Thu, voltage error can be given a follow: io v v err (t) () = t v v ab (t) () t v () ab,id (t) t = 2 V 2V i ( ot, (t t ) err ab H1 C t C H1 ) (3) (3) r r Key waveformof of auxiliary reonant reonant nubber nubber inverter inverter (ARSI) (ARSI) in heavy in load heavy load condition. condition. For ForEquation (1) (1) vab(t) v = V, reonant time can be obtained: ab (t) = V, reonant time can be obtained: 2CV t t r t H12 H1 (4) H12 = t H2 t H1 = 2C rv i (4) o i o next commutation, Sr1 i turned on at th4 Regarding next commutation, S to charge reonant inductor, o that r1 i turned on at t H4 to charge reonant inductor, o witch current revere at th5. Therefore, after S2 and S3 that witch current revere at t are turned off at th6, reonant capacitor H5. Therefore, after S 2 and S 3 are turned off at t H6, reonant can reonate with reonant inductor, which dicharge Cr1 and Cr4 capacitor can reonate with reonant inductor, which dicharge C to zero voltage at th7. r1 and C r4 to zero-voltage at t H7. D1 D4 S1 and S4 Subequently, body diode D can be zero voltage 1 and D 4 conduct current. Thu, S 1 and S 4 can be zero-voltage turned on at th8. Regarding dead time th6 th8, it alo conit of reonant tage and diode clamping tage. Only reonant tage th6 th7 bring about dead time, which i caued by finite rie and fall time. Some equation can be given a follow during reonant tage. v t v t V (5) d1 d3

5 Appl. Sci. 2016, 6, of 17 turned on at t H8. Regarding dead-time t H6 t H8, it alo conit of reonant tage and diode clamping tage. Only reonant tage t H6 t H7 bring about dead-time, which i caued by finite rie- and fall-time. Some equation can be given a follow during reonant tage. v d1 (t) + v d3 (t) = V (5) i cr1 (t) = C r dv d1 (t) dt i cr3 (t) = C r dv d3 (t) dt i cr1 (t) + i Lr (t) = i o + i cr3 (t) (8) v d1 (t) v d3 (t) = L r di Lr (t) dt The initial reonant condition i given a follow: v d1 (t H6 ) = v d4 (t H6 ) = V (10) v d2 (t H6 ) = v d3 (t H6 ) = 0 (11) i Lr (t H6 ) = I Lrm (12) According to Equation (5) (12), inductor current and drain-ource voltage of main MOSFET can be obtained a follow: i Lr (t) = (I Lrm i o ) coω A (t t H6 ) + V Z A inω A (t t H6 ) + i o (13) (6) (7) (9) v d1 (t) = v d4 (t) = 1 2 V V coω A (t t H6 ) 1 2 Z A (I Lrm i o ) inω A (t t H6 ) (14) v d2 (t) = v d3 (t) = 1 2 V 1 2 V coω A (t t H6 ) Z A (I Lrm i o ) inω A (t t H6 ) (15) where ω A = 1 Lr C r, Z A = Lr C r, and I Lrm i initial reonant inductor current. The pole voltage can be obtained a follow: v ab (t) = v d3 (t) v d4 (t) = Z A I boot1 inω A (t t H6 ) V coω A (t t H6 ) (16) where I boot1 i witch current at initial reonant time I boot1 = I Lrm1 i o. The ideal pole voltage, on or hand, hould be a follow: v ab,id (t) = V (17) The voltage error during reonant tage t H6 t H7 can be calculated a follow: v err (t) = v ab (t) v ab,id (t) = Z A I boot1 inω A (t t H6 ) V coω A (t t H6 ) V (18) For Equation (16) v ab (t) = V, reonant time can be obtained: t H67 = t H7 t H6 = 2 arcin ω A V 2 + Z 2 A I2 boot1 V (19) According to analyi of dead-time in heavy load condition, voltage error in a witching cycle can be obtained from Equation (3) and (18):

6 Appl. Sci. 2016, 6, of 17 Appl. Sci. 2016, 6, of 17 io 2 V ( tt ) t t t H1 H1 H2 C r v coω in ω err V V t t Z I tt t t t 2V i A H 6 A boot1 A H 6 H 6 H 7 (20) o C r (t t H1 ) t H1 t H2 v err = 0 t t t or t t t or t t t H0 H1 H2 H6 H7 H10 V V coω A (t t H6 ) + Z A I boot1 inω A (t t H6 ) t H6 t t H7 (20) 0 t H0 t < t H1 or t H2 < t < t H6 or t H7 < t < t H10 Thu, average voltage error in a witching cycle can be calculated a follow: Thu, average voltage error in a witching cycle can be calculated a follow: 1 t H 10 t t V V err = 1 th10 v err dt = t H12 t H67 V = V 2C V V H H r 2C r V T t H0 T T i o arcin V v dt V err err T 2 V (21) th 0 T T i ω o A arcinv Z I ω A V 2 A boot + Z 2 1 (21) A I2 boot1 where T i witching period. where T i witching period Light Load Condition Light Load Condition When load current i low, reonant capacitor cannot be dicharged to zero voltage during When dead time. load current NZVS i low, of S2 and reonant S3 fail capacitor [22]. Therefore, cannot be dicharged auxiliary to circuit zero-voltage i operated during to achieve dead-time. AZVS of NZVS S2 and ofs3. S 2 One andwitching S 3 fail [22]. cycle Therefore, of operating auxiliary waveform circuitin i operated i to hown achieve in AZVS of 3. S 2 and S 3. One witching cycle of operating waveform in i hown in Key waveform of ARSI in light load condition. 3. Key waveform of ARSI in light load condition.

7 Appl. Sci. 2016, 6, of 17 Before t L2, S r2 i turned on to charge reonant inductor L r, thu increaing witch current. After S 1 and S 4 are turned off at t L2, reonant capacitor reonate with reonant inductor. Due to higher witch current, C r2 and C r3 can be dicharged to zero-voltage. Thu, S 2 and S 3 can be turned on at ZVS condition. The voltage error alo only occur in reonant tage t L2 t L3. Thi reonant tage i imilar to tage t H6 t H7 in 2. The ame equation can be obtained a Equation (5) (9). However, initial reonant condition are different a follow: v d1 (t L2 ) = v d4 (t L2 ) = 0 (22) v d2 (t L2 ) = v d3 (t L2 ) = V (23) i Lr (t L2 ) = I Lrm2 (24) Therefore, inductor current and drain-ource voltage of main MOSFET can be obtained a follow according to Equation (5) (9) and (22) (24): v d1 (t) = v d4 (t) = 1 2 V 1 2 V coω A (t t L2 ) Z AI boot2 inω A (t t L2 ) (25) v d2 (t) = v d3 (t) = 1 2 V V coω A (t t L2 ) 1 2 Z AI boot2 inω A (t t L2 ) (26) i Lr (t) = I boot2 coω A (t t L2 ) V Z A inω A (t t L2 ) + i o (27) where I boot2 i witch current at initial reonant time I boot2 = I Lrm2 + i o Thu, actual pole voltage can be calculated a follow, v ab (t) = v d3 (t) v d4 (t) = V coω A (t t L2 ) Z A I boot2 inω A (t t L2 ) (28) wherea ideal pole voltage i: v ab,id (t) = V (29) The voltage error caued by reonant tage can be calculated a follow: v err (t) = v ab (t) v ab,id (t) = V coω A (t t L2 ) Z A I boot2 inω A (t t L2 ) + V (30) For Equation (28) v ab (t) = V, reonant time can be obtained: t L23 = t L3 t L2 = 2 V arcin ω A V 2 + Z 2 A I2 boot2 (31) Regarding dead-time t L8 t L10, principle i ame a t H6 t H8 in heavy load condition, which i caued by rie- and fall-time of pole voltage. Therefore, voltage error and reonant time can be obtained: v err (t) = Z A I boot3 inω A (t t L8 ) V coω A (t t L8 ) V (32) t L89 = t L9 t L8 = 2 arcin ω A V 2 + Z 2 A I2 boot3 V (33) where I boot3 i witch current at initial reonant time I boot3 = I Lrm3 i o The voltage error in a witching cycle can be obtained from Equation (30) and (32) in light load condition:

8 Appl. Sci. 2016, 6, of 17 Appl. Sci. 2016, 6, of 17 V coω V coω A (t t t t L2 ) Z Z A I I boot2 inω in ω (t t t L2 ) + V V t t t L2 t A L2 A 2 A L2 L2 L 3 t L3 v err = v V V coω coω A (t t L8 ) + A I boot3 inω ω err V V tt Z I 8 3 (t t t L8 8) t 8t L8 t A L A A L L tl 9 t L9 (34) 0 0 t L0 tt < t L2 torort L3 t < t t< t or or t t L9 t< t< t L0 L2 L3 L8 L9 L12 L12 Thu, average voltage error in a witching cycle can be calculated a follow: ( V err = T 1 tl12 1 tl12 t v L0 err dt = t t t L23 t L89 T V = V V V V T V 2 +Z 2 A I2 2 V L L arcin arcin 2 V v dt V err err ω arcin T tl0 T T ω ω A A V Z I A boot A V Z I boot2 A boot V V 2 +Z A I2 boot3 ) (35) (35) 2.2. Compared with Hard-Switching Inverter 2.2. Compared with Hard Switching Inverter According to analyi in Section 2.1, eential principle of ZVS both in light and heavy load According condition i to that analyi reonant in Section capacitor 2.1, that eential are parallelly principle connected of ZVS to both in next turn-on light and witche heavy load are dicharged condition to i zero-voltage that reonant and n capacitor body that diode are conduct parallelly connected current. Thu, to next witche turn on can witche be turned are on dicharged with zero-voltage. to zero voltage The dead-time and n conit body of diode reonant conduct tage and current. diode Thu, clamping witche tage. However, can be turned dead-time on with zero voltage. only exit The in dead time reonant conit tage, of which reonant i caued tage by and diode finite clamping rie- and fall-time tage. However, of voltage. dead time 4 how only exit dead-time in reonant of a ingle tage, pole, which S i 1 and caued S 3, both by in finite HLM rieand and fall time where v of a i voltage. actual pole voltage 4 how and v dead time a,id i ideal pole voltage. of a ingle In order pole, S1 to and ummarize S3, both in dead-time HLM and both where va in i HLM actual and, pole all voltage rieand va,id and fall-time i ideal are pole conidered voltage. In to order be linearly to ummarize changed in dead time 4. both in HLM and, all rie and fall time are conidered to be linearly changed in Dead time Dead-time of of ARSI. ARSI. A for hard witching inverter, dead time i different from that of ARSI. To A for hard-witching inverter, dead-time i different from that of ARSI. analyze dead time, aumption i ame a that of ARSI. 5 how To analyze dead-time, aumption i ame a that of ARSI. 5 how operating tage and key waveform of hard witching inverter with a ingle pole. operating tage and key waveform of hard-witching inverter with a ingle pole. Regarding dead time t1 t3, body diode D3 conduct current after S1 i turned off at t1. Regarding dead-time t The actual pole voltage i clamped 1 t 3, body diode D to zero, which equal 3 conduct current after S ideal pole voltage. A 1 i turned off at t for dead time 1. The actual pole voltage i clamped to zero, which equal ideal pole voltage. A for dead-time t4 t6, current i diverted from S3 to it body diode D3 rar than D1 after S3 i turned off, t becaue 4 t 6, current i diverted from S of poitive load current. 3 to it body diode D The pole voltage i 3 rar than D clamped to zero, 1 after S wherea 3 i turned off, ideal pole becaue of poitive load current. The pole voltage i clamped to zero, wherea ideal pole voltage i V. Therefore, voltage lo occur during dead time t4 t6. Only after S1 i turned on voltage i V can current. Therefore, voltage lo occur during dead-time t be diverted to S1. The dead time caue voltage lo when 4 t 6. Only after S output 1 i turned current i on can current be diverted to S poitive. However, when output 1. The dead-time caue voltage lo when output current i current i negative, dead time lead to voltage gain. poitive. However, when output current i negative, dead-time lead to voltage gain. The dead time of hard witching inverter i related to output current polarity, The dead-time of hard-witching inverter i related to output current polarity, which caue blanking delay error, wherea dead time of ARSI ha no relation to which current caue polarity. blanking Only delay rieerror, and fall error wherea occur dead-time in ARSI, rar of than ARSI ha blanking no relation delay to error. current Eentially, polarity. Only voltage error riecaued and fall-error by occur finite commutation in ARSI, time rar of than voltage blanking alo occur delay in error. hard witching Eentially, voltage inverter error due to caued junction by finite capacitance commutation of witche. time of However, voltage alo compared occur with blanking delay error, thi error can be neglected. Regarding ARSI, lower reonant

9 Appl. Sci. 2016, 6, of 17 in hard-witching inverter due to junction capacitance of witche. However, compared Appl. withsci. blanking 2016, 6, 344 delay error, thi error can be neglected. Regarding ARSI, lower reonant 9 of 17 capacitance, maller voltage error. The dead-time can be fully eliminated if reonant capacitance, aremaller zero and voltage junction error. capacitance The dead time are not conidered. can be fully eliminated if reonant capacitance are zero and junction capacitance are not conidered. (b) (c) Dead time Dead-time of of hard witching hard-witching inverter inverter with with ingle ingle pole pole operating operating tage tage when when io > 0; (b) key waveform when io > 0; (c) key waveform when io i < 0. o > 0; (b) key waveform when i o > 0; (c) key waveform when i o < Compenation Method 3. Compenation Method In HLM, ZVS realization of main witche i AZVS NZVS. In, ZVS In HLM, ZVS realization of main witche i AZVS + NZVS. In, ZVS realization i AZVS + AZVS. To ditinguih HLM and, threhold current Ith i ued, realization i AZVS + AZVS. To ditinguih HLM and, threhold current I th i ued, which i given a follow. which i given a follow. 2CV I th = r rv (36) th (36) t t dead dead When magnitude of load current i lower than I th, load current cannot dicharge reonant When capacitor magnitude to zero-voltage. of load Thu, current i ARSI lower operate than Ith, in. load When current magnitude cannot dicharge of load reonant current i capacitor higher than to zero voltage. I Thu, ARSI operate in. When magnitude of load th, HLM i adopted. Table 1 how realization type of ZVS from zero current load to i full higher load. than Ith, HLM i adopted. Table 1 how realization type of ZVS from zero load to full load. Table 1. Realization type of ZVS from zero load to full load. Table 1. Realization type of ZVS from zero load to full load. Type i o < I th I th i o I th i o > I th Type io Ith Ith io Ith io > Ith S 2 and S S2 and 3 AZVS (S S3 AZVS (Sr2) ) AZVS (S AZVS (Sr2) r2 ) NZVS NZVS S 1 and S 4 NZVS AZVS (S r1 ) AZVS (S r1 ) LoadS1 Condition and S4 Heavy NZVS Load AZVS Light(Sr1) Load AZVS Heavy (Sr1) Load Load Condition Heavy Load Light Load Heavy Load The ARSI can reduce witching lo, wherea conduction lo i increaed due to auxiliary current. To maintain a low conduction lo, auxiliary current hould be a low a poible. Thu, initial reonant current Iboot i controlled to be contant from zero load to full load a follow.

10 Appl. Sci. 2016, 6, of 17 Appl. Sci. 2016, 6, of 17 I I I I boot1 boot2 boot 3 boot (37) Appl. Sci. 2016, 6, of 17 The dead time in cae of poitive output current i introduced in Section 2.1. When The ARSI can reduce witching lo, wherea conduction lo i increaed due to output auxiliary current current. i negative, To maintain dead time a low conduction lo, i imilar. auxiliary Therefore, current hould voltage be a error low a caued poible. by dead time Thu, can initial be obtained reonant current baed on I boot Equation I I boot1 boot i controlled (21), I 2 to (35) boot 3 be contant and Iboot (37): from zero load to full load a follow. (37) The dead time in cae of poitive output current i introduced in Section 2.1. When output current i negative, V dead time 2CI boot1 V = 2I boot2 i = imilar. I boot3 Therefore, = VI boot (37) r arcin voltage i I error caued by o th dead time can be obtained baed T on i Equation ω o A (21), (35) The dead-time in cae of poitive output Vand current Z(37): i I A boot introduced in Section 2.1. When output current i negative, V 0 dead-time i imilar. Therefore, voltage error caued by V 2C V 2 V err I i I th o th (38) dead-time can be obtained baed r on Equation arcin (21), (35) and (37): i I o th V T i ω o A V Z I ( 2 V 2C V A boot ) arcin r i I o th V T0V 2C r V T i o 2 V ω arcin err ω A V Z I ii o i A i I th o V 2 +Z 2 A I2 o th > I (38) A boot th boot V 2 V 2C V V err = 0 ( arcin r I The voltage error i related to ) i o i I th I (38) o th T reonant time. Due to ω A V Z I i ame Iboot, voltage error i zero V 2 V A boot T ω arcin A V 2 +Z 2 A I2 o in. A for HLM, voltage error occur becaue 2C r V reonant i o i o < Itime i adaptively related th to output boot The voltage current error to achieve i related NZVS, to wherea reonant time. commutation Due to ame time Iboot, to achieve voltage AZVS error i i contant. zero in Due to The. dead time voltage A for error i HLM,, related a voltage to reonant error occur time. Due becaue between to ame reonant actual I boot, time pole voltage i voltage adaptively and error irelated ideal pole zero in voltage. to. The output ARSI A for current can HLM, be to modeled achieve voltage NZVS, a a error proportional wherea occur becaue commutation gain Kpwm reonant without time to time conideration achieve i adaptively AZVS i of contant. related delay. Kpwm to i ratio output Due between to current dead time to achieve DC, voltage NZVS, a voltage wherea and error peak occur value commutation between of time carrier actual to achieve in pole voltage AZVS PWM i and modulator. contant. ideal pole The reference voltage. Due voltage The to ARSI vc dead-time i can amplified be modeled, Kpwm, a voltage a a thu proportional error obtaining occur gain Kpwm between ideal without pole actual conideration voltage pole voltage vab,id. of and The delay. Kpwm ideal actual pole pole voltage i voltage. can ratio The be obtained between ARSI can be by modeled adding DC voltage a a proportional voltage and peak error value gain verr. Kof pwm without carrier 6 how conideration in PWM tranfer of modulator. delay. function K pwm The i of reference ratio between voltage vc ARSI. i DCamplified voltage and Kpwm, peak thu value obtaining of carrier ideal in pole PWM voltage modulator. vab,id. The The actual reference pole voltage vcan c i be amplified obtained K pwm by, adding thu obtaining voltage ideal error pole verr. voltage6 vhow ab,id. The actual tranfer polefunction voltage can of be ARSI. obtained by adding voltage error v err. 6 how tranfer function of ARSI. 6. Tranfer function of ARSI. 6. Tranfer function of ARSI. The output current can be calculated a follow. The output current can be calculated a follow. 1 1 i 1 v 1 v o ab, id err (39) i L1R v L1 Rv i o ab, id err (39) o = o o L v L LR o o+ R o ab,id + o o v o o err (39) o L o + R o where actual voltage v K v. where actual voltage ab vv, id pwm vc. ab,id, id = K pwm cv c. The The voltage voltage error error caued caued by by by dead time dead time dead-time i i i conidered conidered a aa a diturbance in in in ARSI. ARSI. ARSI. To To compenate To compenate voltage voltage error, error, error, feedforward feedforward method method can can can be be be utilized, which i i i hown in in in Tranfer function of ARSI with feedforward compenation. 7. Tranfer function of ARSI with feedforward compenation. 7. Tranfer function of ARSI with feedforward compenation. After feedforward compenation i utilized, output current can be calculated a follow. After feedforward compenation i utilized, output current can be calculated a follow. 1 v 1 i [( v ) K v ] v (40) i v K v v (40) err o c pwm err ab, id L o1r K o v LR err pwm o 1 o [( ) ] o c pwm err ab, id LR K LR o o pwm o o

11 Appl. Sci. 2016, 6, of 17 After feedforward compenation i utilized, output current can be calculated a follow. Appl. Sci. 2016, 6, i o = [(v c v err 1 11 of 17 )K pwm + v err ] = v L o + R o K pwm L o + R ab,id (40) o According to Equation (39) and (40), dead time can be eliminated by uing propoed According compenation to Equation method (39) and oretically. (40), dead-time can be eliminated by uing propoed compenation method oretically. 4. Simulation and Experiment 4. Simulation and Experiment The propoed compenation method wa implemented in Altera Cyclone IV FPGA of a digitally The controlled propoed compenation ARSI prototype method uing wa implemented parameter lited in in Altera Table Cyclone 2. IV8 FPGA how of a photograph digitally controlled of prototype, ARSI prototype which uing conit of parameter a FPGA (Altera lited incorporation Table 2. EP4CE22E22C7N) 8 how control photograph board, of a witching prototype, power whichupply, conita ofmosfet a FPGA (Altera driver Corporation and a power EP4CE22E22C7N) circuit. In addition, control method board, ai witching alo verified power in upply, imulation a MOSFET uing driver Saber. and a power circuit. In addition, method i alo verified in imulation uing Saber. Table 2. Parameter of circuit. Table 2. Parameter of circuit. Parameter Value DC Parameter voltage V Value 80 V Switching frequency f 200 khz DC voltage V 80 V Switching Dead time tdead frequency f khz μ Dead-time Load t dead Ω, µ 4.87 mh Reonant Load inductor Lr 3.7 Ω, μH mh Reonant capacitor inductor L r 4.4 µh Cr 4.7 nf Reonant capacitor C r 4.7 nf Threhold current Ith 3 A Threhold current I th 3 A Iboot 4 4 AA I boot Photograph Photograph of of prototype. prototype. 9 how open-loop open loop control diagram of ARSI with propoed dead-time dead time compenation. FPGA ample output current in in each witching cycle. Then mode judgement i i completed according to to Table Table 1. The 1. The voltage error error can can be calculated be from from Equation (38). (38). Therefore, voltage voltage error error can can be compenated be in in reference reference voltage. voltage. A for A for auxiliary auxiliary current current control, control, on-time on time of of auxiliary auxiliary witche witche can be can calculated be calculated after after mode mode judgement. judgement. Finally, Finally, gate ignal gate ignal of witche of witche can becan generated be generated from from compenated compenated reference reference voltage voltage and and on-time on time of of auxiliary auxiliary witche. witche. The compenation method i baed on model of voltage error. The more accurate model, more precie compenation reult. 10 how calculated voltage error v. output current according to Equation (38). The voltage error only occur in HLM. A voltage error about 1.2 V occur at threhold current 3A. A output current increae, voltage error decreae firt before increaing.

12 Appl. Sci. 2016, 6, of 17 Appl. Sci. 2016, 6, of Open loop Open-loop control diagram of ARSI with propoed dead time dead-time compenation Voltage Error (V) Output Current (A) 10. Average voltage error v. output current in in calculation how how reonant reonant time time v. v. witching witching current current both in both calculation in calculation and imulation, and imulation, where witching current of AZVS i Iboot where witching current of AZVS i I and witching current of NZVS i io. The boot and witching current of NZVS i i o. The reonant reonant time of AZVS time i of nonlinear AZVS i related nonlinear to related witching to current. witching When current. witching When current witching i high current enough, i high reonant enough, time reonant of AZVS time i cloe of AZVS to that i cloe of NZVS. to that The of NZVS. calculation The calculation of reonant of time reonant i in good time i agreement in good agreement with imulation with imulation reult, which reult, i related which to i related voltage to error. voltage error how how output output voltage voltage and and current current of of hard-witching hard witching inverter inverter when when modulation modulation index index i i in in an an open loop open-loop configuration. configuration. To To meaure meaure output output voltage voltage vo, v a filter i o, a filter added i added to to attenuate attenuate carrier carrier harmonic harmonic of of pole pole voltage voltage vab. v eriou ditortion occur both in ab. A eriou ditortion occur both in output output current current and and voltage voltage due due to to long long dead-time dead time of of µ. μ.

13 Appl. Sci. 2016, 6, 344 Appl. Sci. 2016, 6, of of 17 Appl. Sci. 2016, 6, of 17 Reonant Time tr (n) Reonant Time tr (n) NZVS(Simulation) NZVS(Calculation) NZVS(Simulation) NZVS(Calculation) AZVS(Simulation) AZVS(Simulation) AZVS(Calculation) AZVS(Calculation) (A) Switching Current (A) 11. Reonant time v. in and imulation. 11. Reonant time v. witching current both in calculation and imulation. vo (20V/div) vo (20V/div) io (4A/div) io (4A/div) Time Bae: 2m/div vo (10V/div) io (2A/div) vo (10V/div) io (2A/div) Time Bae: (b) 2m/div 12. Output voltage and current of hard witching inverter when modulation index i 0.4 in an open loop configuration. imulation reult; (b) experimental reult. (b) 13 and 14 how imulation and experimental reult of ARSI without dead time compenation, Output Output repectively, voltage voltage and and when current current of of modulation hard-witching hard witching index i inverter 0.4 inverter an when when open loop modulation modulation configuration. index index ithe 0.4 in 0.4 auxiliary an in open-loop an open loop circuit configuration. i configuration. operated twice imulation with imulation bidirectional reult; reult; (b) current experimental (b) experimental in a witching reult. reult. cycle in. An obviou ditortion occur in output voltage at mode witching point. However, ditortion of output 13 and current 14 how and voltage imulation i le than and that of experimental hard witching reult inverter of ARSI in without 12, owing dead time 13 and 14 how imulation and experimental reult of ARSI without dead-time compenation, to abence repectively, of blanking when delay error modulation in ARSI. index i 13b 0.4 how in an open loop voltage error configuration. between The compenation, auxiliary actual circuit output repectively, i voltage operated and twice ideal when output modulation with bidirectional voltage. The imulation index i current in reult 0.4 in a witching are an in open-loop good cycle agreement configuration. in. with An The auxiliary circuit i operated twice with bidirectional current in a witching cycle in. obviou ditortion occur in output voltage at mode witching point. However, ditortion An obviou ditortion occur in output voltage at mode witching point. However, of output current and voltage i le than that of hard witching inverter in 12, owing ditortion of output current and voltage i le than that of hard-witching inverter in 12, to abence of blanking delay error in ARSI. 13b how voltage error between owing to abence of blanking delay error in ARSI. 13b how voltage error between actual output voltage and ideal output voltage. The imulation reult are in good agreement with actual output voltage and ideal output voltage. The imulation reult are in good agreement with

14 Appl. Sci. 2016, 6, of 17 Appl. Sci. 2016, 6, of 17 calculation Appl. Sci. 2016, reult 6, 344 in 10 without conideration of ripple. The maximum voltage 14 of error 17 i about 2 Vcalculation and occur reult at in mode witching 10 without point. conideration of ripple. The maximum voltage error i Appl. about calculation Sci , V and 6, 344 reult occur in at mode 10 without witching conideration point. of ripple. The maximum voltage error 14 of 17 i about 2 V and occur at mode witching point. vo (20V/div) ilr (5A/div) vo calculation reult in 10 without conideration of ripple. (20V/div) The maximum voltage error vo (20V/div) ilr io (5A/div) (5A/div) vo i about 2 V and occur at mode witching point. (20V/div) io (5A/div) vo (20V/div) ilr (5A/div) vo (20V/div) vo,id (20V/div) io (5A/div) vo,id (20V/div) verr (2V/div) verr (2V/div) vo,id (20V/div) verr (2V/div) Time Bae: 2m/div Time(b) Bae: 2m/div (b) 13. Simulation waveform of ARSI without dead time compenation when modulation 13. SimulationTime waveform Bae: 2m/div of ARSI without dead-time compenation when modulation index i Simulation in an open loop waveform configuration. of ARSI without imulation dead time reult; compenation (b) voltage error. when modulation index i 0.4 in an open-loop configuration. imulation reult; (b) voltage (b) error. index i 0.4 in an open loop configuration. imulation reult; (b) voltage error. 13. Simulation waveform of ARSI without dead time compenation when modulation index i 0.4 in an open loop configuration. vo (10V/div) imulation reult; (b) ilr (2A/div) voltage error. io (2.5A/div) vo (10V/div) ilr (2A/div) io (2.5A/div) vo (10V/div) ilr (2A/div) io (2.5A/div) 14. Experimental waveform of ARSI without dead time compenation when modulation index i Experimental in an open loop waveform configuration. of ARSI without dead time compenation when modulation 14. Experimental waveform of ARSI without dead-time compenation when modulation index i 0.4 in an open loop configuration. index i 0.4 in 15 an and open-loop 16 how configuration. 14. Experimental waveform imulation of ARSI without and experimental dead time compenation reult, repectively, when modulation when propoed index compenation i in and open loop 16 method how configuration. i ued imulation in and ARSI. experimental The output voltage reult, ditortion repectively, i reduced when in propoed 15a compenation and 16 how without method increaing imulation i ued in and auxiliary experimental ARSI. current The output reult, ilr. voltage repectively, 15b ditortion demontrate when i reduced that propoed in compenation voltage error 15a method and i 15 reduced. 16 and i without ued 16 how increaing ARSI. imulation The auxiliary output and current experimental voltage ilr. ditortion reult, 15b i repectively, demontrate reduced inwhen that 15a voltage propoed error compenation i reduced. method i ued in ARSI. The output voltage ditortion i reduced in and 16 without increaing auxiliary current i vo (20V/div) ilr (5A/div) Lr. 15b demontrate that voltage error 15a and 16 without increaing auxiliary current ilr. 15b demontrate that i reduced. (20V/div) io (5A/div) ilr (5A/div) vo (20V/div) voltage error i reduced. io (5A/div) vo (20V/div) vo (20V/div) ilr (5A/div) io (5A/div) vo (20V/div) vo,id (20V/div) vo,id (20V/div) verr (1V/div) verr (1V/div) vo,id (20V/div) verr (1V/div) Time Bae: 2m/div Time Bae: (b) 2m/div (b) 15. Simulation waveform of ARSI with dead time compenation when modulation index i 0.4 in 15. an Simulation open loop configuration. waveform of ARSI imulation with dead time reult; compenation (b) voltage error. when modulation index (b) i 0.4 in an open loop configuration. imulation reult; (b) voltage error. 15. Simulation waveform of ARSI with dead time compenation when modulation index 15. Simulation waveform of ARSI with dead-time compenation when modulation index i 0.4 in an open loop configuration. imulation reult; (b) voltage error. i 0.4 in an open-loop configuration. imulation reult; (b) voltage error.

15 Appl. Sci. 2016, 6, of 17 Appl. Sci. 2016, 6, of 17 vo (10V/div) io (2.5A/div) ilr (2A/div) Appl. Sci. 2016, 6, of 17 vo (10V/div) io (2.5A/div) ilr (2A/div) Experimental Experimental waveform waveform of of ARSI ARSI with with dead-time dead time compenation compenation when when modulation modulation index i index 0.4 ini an 0.4 open-loop in an open loop configuration. configuration. 16. Experimental waveform of ARSI with dead time compenation when modulation index 17 i how 0.4 in an open loop magnitude configuration. of 2nd 10th harmonic component with repect to 17 how magnitude of 2nd 10th harmonic component with repect to fundamental component in output voltage and current. The power analyi module DPO4PWR fundamental component 17 how in magnitude output voltage of and 2nd 10th current. harmonic The power component analyi with module repect DPO4PWR to i ued to analyze total harmonic ditortion (THD) of current and voltage. 17a i ued fundamental to analyze component totalin harmonic output ditortion voltage and (THD) current. The of power current analyi andmodule voltage. DPO4PWR 17a demontrate that THD of output voltage with compenation method i 3.48% which i le demontrate i ued to that analyze THD of total output harmonic voltage ditortion with (THD) compenation of current method and voltage. i 3.48% which17a i le than 6.29% than without dead time compenation. The magnitude of 2nd 10th harmonic than 6.29% demontrate than without that THD dead-time of output voltage compenation. with compenation The magnitude method of i 3.48% 2nd 10th which harmonic i le are reduced, than 6.29% except than without for dead time 8th harmonic. compenation. 17b indicate The magnitude that THD of of 2nd 10th output harmonic current i are reduced, except for 8th harmonic. 17b indicate that THD of output current i reduced are from reduced, 1.57% except to 0.712% for by 8th uing harmonic. propoed 17b compenation indicate that method. THD of output current i reduced from 1.57% to 0.712% by uing propoed compenation method. reduced from 1.57% to 0.712% by uing propoed compenation method % % without compenation without compenation with compenation 10.00% with compenation 10.00% Mag ( of Fundamental) Mag ( of Fundamental) Mag ( of Fundamental) 1.00% 1.00% 0.10% 0.10% 0.01% 0.01% % % Mag ( of Fundamental) 10.00% 10.00% 1.00% 1.00% 0.10% 0.10% 0.01% Harmonic Number Harmonic Number without compenation with without compenation compenation with compenation % Harmonic Number (b) Harmonic Number 17. Magnitude of 2nd 10th harmonic component in repect to fundamental 17. Magnitude of 2nd 10th harmonic component (b) in repect to fundamental component component output voltage; (b) output current. output voltage; (b) output current. 17. Magnitude of 2nd 10th harmonic component in repect to fundamental component output voltage; (b) output current.

16 Appl. Sci. 2016, 6, of 17 Appl. Sci. 2016, 6, of how experimental voltage and current THD under different load condition. 18 how experimental voltage and current THD under different load condition. A A modulation index increae, THD of output voltage and current both decreae. modulation index increae, THD of output voltage and current both decreae. Through Through uing dead-time compenation trategy, THD of output voltage and current are uing dead time compenation trategy, THD of output voltage and current are clearly clearly reduced. reduced. Voltage THD (%) without compenation with compenation 2 Current THD (%) Modulation Index Modulation Index (b) without compenation with compenation 18. Experimental voltage and current THD under different load condition voltage THD; 18. Experimental voltage and current THD under different load condition voltage THD; (b) current THD. (b) current THD. 5. Concluion 5. Concluion In thi paper, dead time of a typical zero voltage witching (ZVT) inverter In auxiliary thi paper, reonant dead-time nubber inverter (ARSI) i of a typicalanalyzed. zero-voltage-witching The ARSI can fully (ZVT) eliminate inverter blanking auxiliary reonant delay nubber error which inverter i (ARSI) i main drawback analyzed. of The hard witching ARSI can fully inverter. eliminate Only rie blanking and fall error delay error whichcaued i by main reonant drawback capacitor of hard-witching occur in ARSI, inverter. which Only i not conidered rie- andin fall-error hard witching caued by inverter. In imulation and experiment, quality of output in ARSI i ignificantly better reonant capacitor occur in ARSI, which i not conidered in hard-witching inverter. In than that in hard witching inverter, even if dead time compenation trategy i not ued. imulation and experiment, quality of output in ARSI i ignificantly better than that in Furrmore, a feed forward compenation method baed on voltage error etimation i hard-witching inverter, even if dead-time compenation trategy i not ued. propoed to compenate rie and fall error of dead time. Both imulation and Furrmore, experimental reult a feed-forward how that compenation compenation method trategy baed can ively on voltage reduce error THD etimation of i propoed output. to compenate rie- and fall-error of dead-time. Both imulation and experimental reult how that compenation trategy can ively reduce THD of output. Acknowledgment: Thi work wa upported by State Key Program of National Natural Science of China Acknowledgment: under Grant Thi work and wa National upported Natural byscience State Foundation Key Program of China ofunder National Grant Natural Science of China under Grant and National Natural Science Foundation of China under Grant Author Contribution: Hailin Zhang conceived propoed method and wrote paper; Baoquan Kou Author provided Contribution: technical guidance Hailin Zhang and good conceived advice for propoed manucript; method Lu Zhang and and wrote He Zhang paper; performed Baoquan Kou provided experiment technical and guidance reviewed andmanucript. good advice for manucript; Lu Zhang and He Zhang performed experiment and reviewed manucript. Conflict of Interet: The author declare no conflict of interet. Conflict of Interet: The author declare no conflict of interet. Reference Reference 1. Leggate, D.; Kerkman, R. Pule-baed dead-time compenator for PWM voltage inverter. IEEE Tran. Ind. Electron. 1997, 38, [CroRef]

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