Lossless, Passive Soft Switching Methods for Inverters and Amplifiers

Transcription

1 ole, Paive Soft Switching Method for Inverter and Amplifier K. Mark Smith Jr. and K. M. Smedley Department of Electrical and Computer Engineering Univerity of California, Irvine Irvine, CA 9697 USA Abtract Thi paper propoe new lole paive oft witching method for inverter developed from a ynthei procedure applicable to all PWM converter. The lole paive oft-witching converter propertie and ynthei procedure are decribed and extended here for inverter. Promiing half-bridge and full-bridge oft-witching inverter example are hown from the ynthei reult. The voltage tre acro the main witche can be eaily maintained below 5% of bu. No tranformer are ued for energy recovery, eliminating their aociated diode tre and leakage inductance problem. The oft turn-on full bridge contain only ix component. The oft turn-on/turn-off half-bridge contain component. The theoretical and experimental waveform and analyi are given. I. INTRODUCTION Soft witching of PWM converter lower witching loe allowing higher frequency operation and reduced electromagnetic interference (EMI). A higher witching frequency i advantageou becaue it enable ize reduction of the magnetic component and increae the ytem bandwidth. Overall, thee feature increae the power denity of the converter and improve dynamic performance. For PWM converter, oft witching can be broadly claified into two group: paive oft witching and active oft witching. Paive oft witching i performed with paive component (i.e., C, R, and D) only, where active oft witching incorporate additional witche to achieve the reult. Although active method have received a lot of attention in recent year, paive oft witching ha been given renewed notice a a better price/performance ratio alternative to their active counterpart [,3]. Of the witching lo mechanim (voltage and current overlap, diode revere recovery, and the internal witch capacitance diipated at turn-on), paive oft witching method lower all the loe except the internal capacitance lo. Hitorically, thee paive oft witching method have been loy, diipating the recovered energy in reiter [4], however recently, many lole and partially lole technique have been propoed [,5-9]. The two neceary component that mut be added to the circuit to achieve paive zero-current turn on and zerovoltage turn off are a mall inductor and capacitor. The inductor provide zero-current turn on of the active witche and limit the revere recovery of the diode while the capacitor provide zero-voltage turn off of the active witche. Typically, an inductor and capacitor have been place in erie and parallel with each active witch. However, many other location are poible and may yield lower component count, implify the circuit, and improve performance. Furthermore, the additional circuitry accompanying the capacitor and inductor are ued to lolely recover their energy to either the load or the input. There are many different propoed circuit to accomplih thi. However, general topological and electrical propertie can be derived that decribe all poible circuit. By defining thee topological and electrical propertie, new paive oft witching circuit can be yntheized. Thi paper propoe new lole paive oft witching method for inverter developed from a ynthei procedure applicable to all PWM converter. The lole paive oftwitching propertie and ynthei procedure derived in [] i decribed and extended here for inverter in Section II. The ynthei procedure ue the propertie to find all poible location of the capacitor and inductor added to achieve oft witching. Then a et of circuit cell i contructed that can eaily attach to the converter to recover the energy tored in thee element. Promiing half-bridge and full-bridge oftwitching inverter example are hown from the ynthei reult. The voltage tre acro the main witche can be eaily maintained below 5% of bu. No tranformer are ued for energy recovery, eliminating their aociated diode tre and leakage inductance problem. The oft turn-on full bridge contain only ix component, half the component of a previouly propoed oft turn-on circuit [7]. The oft turnon/turn-off half-bridge contain component, le than the lole inverter propoed in []. The theoretical waveform and analyi of the oft witching full-bridge are decribed in Section III and I and an experimental example of a oft turn-on full-bridge circuit i hown in Section. A concluion i given in Section I. II. PROPERTIES AND SYNTHESIS OF OSSESS PASSIE SOFT SWITCHING INERTERS Propertie of lole oft witching converter were derived in [] where complete decription and example are given applicable to all PWM converter. The propertie below are labeled identically with []. However, propertie, and 8 from [] are not hown here becaue they do not apply to inverter. A. Definition of ole Paive Soft-Switching PWM Converter. The definition below firt lit the component that decribe the hard-witched PWM converter and then follow with IEEE PESC Proceeding, 997

2 additional component that are added to allow lole paive oft witching. Hard witched PWM converter:. A et of DC voltage ource, ( i, i,..., n g ). A ingle linear time invariant (TI) reitor R. 3. A et of TI inductor (i, i,..., nl) 4. A et of TI capacitor C (Ci, i,..., nc) 5. A et of active witche S (Si, i,..., n), n ³ 6. A et of diode D (Di, i,..., nd) Paive element for lole oft witching:. A et of zero-current inductor r (ri, i,..., nlr) r provide zero-current turn on of active witche S.. A et of nubber inductor: (i, i,..., nl) 3. A et of zero-voltage capacitor Cr (Cri, i,..., ncr) Cr provide zero-voltage turn off of the active witche S 4. A et of nubber capacitor (i, i,..., nc) 5. A et of nubber tranformer T (T i, i,...,n t ) 6. A et of nubber diode D (Di, i,..., n d ) oltage torage device (SD): A SD i a device or ubcircuit that tore energy in the form of voltage. (e.g. capacitor, voltage upply, etc.) Paive turn-on and turn-off nubber: Set of paive element for oft witching that are added to the hard witched converter to limit the witch current and voltage during witch turn-on and turn-off interval repectively. B. Zero-Current Turn On of Active Switche: Thi ubection decribe the number and placement of the zero-current inductor (ZC) to allow zero-current turn on of all active witche. Property. Zero-current Inductor placement for Multiple Active Switch PWM converter: From a hard witched converter topology, a ufficient condition for the zerocurrent turn on of S i i a zero-current inductor, r i, i placed in all loop compried of S i, a nonempty ubet of (C È {} È D) and a ubet (maybe empty) of S (excluding S i ). Property 3. Maximum number of zero-current inductor: To provide zero-current turn on of X active witche, a imum number of X zero-current inductor i needed. C. Energy Management for Zero-Current Inductor. At each witching interval, additional circuitry mut manage the energy in the ZC for lole operation and avoidance of large voltage pike acro the witche. There are many poible way to control thi energy tranition, however all method have imilar topological and electrical propertie. Property 4. Management of inductor energy at either witch or diode turn off. To control the energy in r i regardle of whether a active witch or diode turn off, r i mut be in a loop compried of a nonempty ubet of D and a SD. The voltage polarity of SD and the conduction direction of D i mut be uch that the inductor energy will tranfer to and/or will charge from the SD when a witch S i turn off or a diode D i recover. Reference [] alo derive a pecial cae of property 4 where more than one management loop can be ued. The SD for property 4 may be a relatively tiff voltage device where the voltage doe not change much from cycle to cycle. In the pat, for inverter ytem, thi SD i mot often realized by a forward tranformer coupling [9-7] a conceptually hown in Fig. a. One magnetic core can be aved by coupling directly to the ZC inductor a mentioned in [4]. Although the ZC energy i tranferred directly to the bu voltage, it ha everal drawback. Uing thi tranformer coupling in an inverter, the ideal voltage tre acro the witch and diode are a follow: Si æ + ö buç ( ) D bu n è nø +. () Equation () how that to maintain a reaonable voltage tre acro the main witch at turn off (i.e..5 bu ) the diode D will have a voltage tre larger than 5 bu when the witch i turned back on. Thi tre can be cut in half by increaing the circuit complexity [6,7]. Furthermore, the tranformer leakage inductance can caue large voltage pike when the witch i turned off. Therefore, all propoed circuit alo ue ome additional voltage clamping action (either loy or lole) to control thi leakage inductance energy. An alternative realization of the SD, which ignificantly reduce the circuit component count and diode voltage tre, i to ue a relatively large capacitor a hown in Fig. b. The energy in the capacitor i accumulated from the management of the ZC energy. It i recovered by inerting a econd inductor and diode o that an -C-D circuit i in parallel with the active witch. With thi arrangement, when the active witch i conducting the capacitor i tranferring the energy to the inductor a hown in Fig. b with the energy path. When the active witch turn off the inductor will tranfer thi energy to the input ource. The voltage of the capacitor will adjut automatically o that at teady tate the energy flowing into the capacitor equal the energy flowing out of the capacitor. In thi cae, the diode have the ame voltage tre a the main witch ( bu + c for an inverter). D. Zero-oltage Turn Off of Active Switche Capacitor may be ued to turn off the main witche with zero voltage, called zero-voltage capacitor (ZC). Thee can ubtantially reduce the turn-off lo of lower device uch a IGBT. Property 5. Zero-voltage capacitor Placement: For zerovoltage turn off of the active witch S i, S i mut be in a loop with a nonempty ubet Cr, a ubet of (C È {} È ) and a nonempty ubet of D. The diode D in the loop mut be in the direction to conduct the witch current when S i turn off. The electrical requirement of thi loop to enure zero-

3 I r S S r D T i D n r D SD SD bu voltage turn off i that when the witch S i i opened and ha zero paraitic capacitance, the voltage around the loop the moment after turn off mut till be zero volt. The nubber component (Cr,, and D) that make up the loop atifying property 5 are defined a the ZC ubcircuit. The other element in the loop are part of the original hard witching topology. Property 6: Zero-voltage capacitor ubcircuit placement (Uing term in graph theory [4]) Every zero-voltage capacitor ubcircuit repreent a chord that create a loop from the larget connected ubgraph that contain witch Si and a ubet of (C È {}). Thi ubgraph i taken from the hard-witched converter topology unle a zero-current inductor ha been inerted into the topology. Then the ubgraph i taken from the hard-witched topology with the zero-current inductor r. Property 7. Maximum number of zero-voltage capacitor: To provide zero-voltage turn off of X active witche, a imum number of X zero-voltage capacitor Cr i needed. E. Synthei of ole Paive Soft Switching Inverter The propertie lited above allow the ynthei of lole paive oft witching inverter. The ynthei proce wa decribed in [] for DC/DC converter. It i extended here for voltage ource inverter. Circuit realized with different location of the ZC, and the ZC ubcircuit, are decribed a the baic oft-witching topologie for a given hardwitched converter. All new and previouly propoed lole paive oft-witching PWM converter can be decribed by one of thee baic oft-witching topologie. Often, everal propoed circuit have ued the ame baic oft-witching topology. What make the circuit different from one another i the paive element added to recover and manage the energy trapped in the ZC and ZC. The number of additional component and their interconnection are virtually limitle. However, by uing elected circuit cell preented in [] with each baic oft-witching topology a lole oftwitching inverter can be found. The tep in the ynthei procedure are a follow: I r S S C i + D Energy Flow Path Fig.. Realization of SD : forward tranformer coupling, arge Capacitor i Step : Find the number and placement of the zero-current inductor. Thi involve a two tep optimization proce a follow: a. For each witch, find all loop atifying property. Take the interection of the element of thee loop to form a et of element, called i_loc. Thi et determine where a ingle inductor can be inerted in erie for zero-current turn on of that witch. b. With the n et obtained from tep a, take the element interection. If thi reulting et i non-empty, then only one ZC i needed to provide zero-current turn-on of all witche. Otherwie more than one inductor i needed and can be found by interecting the et with common element. The reulting number of left over et ignifie the number of ZC. However, to find the optimum number of ZC, order and et interection grouping do matter. For power electronic ytem, the optimum number of inductor can uually be found by inpection. c. The et from b determine the number of ZC and which element the ZC may be inerted on either ide. For example, applying tep a to the full-bridge inverter reult in i_loc et for witche S, S,, S 4 of {S,S, }, { S,S, }, {,S 4, }, {,S 4, } repectively. The element interection of the loop et reult in { }. Only one inductor i needed to provide zero-current turn on of all witche and there are two placement of thi inductor a hown in Table. Similarly, the half-bridge inverter require only one inductor and it ix location are alo hown in Table. Step : For each inductor location obtained in tep, identify the location of the ZC ubcircuit. a. For each witch obtain the ubgraph decribed by property 6. The ZC ubcircuit location are the loop created by a ingle cord around the witch S i. b. The number of ZC ubcircuit location for each witch can be found by defining the number of element in the ubgraph on either ide of the S i a E, and E. The number of capacitor ubcircuit location for a given witch TABE BASIC SOFT-SWITCHING TOPOOGIES FOR HAF AND FU-BRIDGE INERTERS r location Half Bridge S S 3 Full Bridge I0 6 + I0 Cr ocation -3, -9, 3-9, 4- -4, -4 3, 5-4, 6-4 Total 3 8 S 3

4 CS S CS 3 r D CS b CS 4b I o D C C r S D 3 C D C r CS a S CS 4a S 4 S D 3 r D i a follow: Fig.. Capacitor ubcircuit location for each witch ( )( ) CSi _ loc + E + E () c. The total number of ZC ubcircuit combination for a given inductor location i a follow: ( )( ) ( ) C C C K C (3) total _ loc S _ loc S _ loc Sn _ loc Inerting one ZC and ZC ubcircuit combination into a hard-witched topology make up one baic oft-witching topology. Together, all of the ZC and ZC ubcircuit location form all poible baic oft-witching topologie. Table how the number of ZC ubcircuit location for each inductor location. For example, with the ZC in location of the full-bridge, the poible number of ZC ubcircuit combination i 4, lited a -4. Thee combination can be een in Fig.. Switche S and each have one poible ZC ubcircuit location, C and C repectively. Switche S and S 4 each have two location, CSa,b and Ca,b. Uing (3) obtain the four combination of ZC ubcircuit that can be ued when the inductor i in location. From table, uing one ZC, there are a total of 3 baic oft-witching topologie for the half-bridge inverter and 8 baic oft-witching topologie for the full-bridge inverter. Step 3: For each baic oft-witching topology match one or more circuit cell to the ZC and ZC ubcircuit location to enure the ret of the topological and electrical propertie are atified. Once a baic oft-witching topology i identified, circuit cell hown in [] are ued to provide the additional circuitry to control the inductor energy (property 4) and reet the ZC (property 5). For hard witched converter with no paive witche (i.e. diode), only circuit cell, and I from [] need to be ued and are diplayed for convenience in Fig 3. For thee two cell, i a relatively large capacitor, which tore the inductor r and capacitor Cr energy from cycle to cycle. Element Cr,, and D comprie the ZC ubcircuit for witch S. i relatively large and tranfer the energy in to a ubet of (C È ). The cell in Fig 3 become jut turn-on nubber by removing the capacitor Cr Fig. 3. Circuit cell uing a capacitor SD; Cell ; Cell I. and a diode D. They alo become jut turn-off nubber by not placing inductor r into a loop atifying property. An example of thi ynthei procedure i hown in Fig. 4 for the full-bridge inverter with the ZC placed in location. Fig. 4a how the choen tarting baic oft-witching full-bridge topology. The circuit cell in Fig. 3a i then ued to create the oft witching inverter hown in Fig. 4b. Thi inverter will provide oft turn on and turn off of all witche, and maintain lole operation, but it ha many component. Fortunately, many repeatable function can be combined with one et of component, allowing the deign to be implified to Fig. 4c. Fig. 5 and 6 how everal promiing ynthei example for a full-bridge and half-bridge inverter repectively. Each inverter ha an extra winding on the core and the half bridge ha two capacitor that are ued to maintain the voltage below 5% of bu. Alo hown in Fig. 5b and 6b are jut the turn-on nubber verion of the circuit. To the author knowledge, thee are the firt propoed lole paive nubber inverter that do not ue tranformer coupling to realize the SD. Reference [0] how a diipative nubber that alo doe not ue a tranformer. Furthermore, for the half-bridge inverter, the voltage tre acro all diode i the ame or le than the main witche ( bu + c ). CSb Cb C S D D r C r C D C r D S C D S5 S (c) Fig. 4. Synthei Example: baic full-bridge topology; Synthei reult; (c) Simplification S I o CSb C S 4 S Cb C 4

5 r D D C r D DS Cr S D r DS D S i - 0 (4) c () t ( t t ) Thi current add to the witch current giving c i ( t) + ( t- t0 ). (5) Fig. 5. Synthei example full-bridge inverter: Soft Turn-on/Turn-off; Soft Turn-on; D S5 S D S Cr Cr D C D S D S r S I o (c) (d) Fig 6. Synthei example half-bridge inverter: Soft Turn-on/Turn-off; Soft Turn-on; Thi i the ame for the full-bridge inverter when and are on eparate core. However, when uing one core with the full-bridge inverter, the diode in erie with and (D 5 and D 6 in Fig. 5a) can reach ( bu ). The full-bridge turn-on nubber contain only ix component, The halfbridge turn-on/turn-off nubber contain component. III. OPERATION OF THE EXAMPE OSSESS PASSIE FU-BRIDGE INERTER In thi ection, the operation of the example paive oft witching full-bridge inverter from Fig. 5a will be detailed. The operation of oft turn-on full bridge, Fig. 5b, and the half-bridge inverter hown in Fig. 6a and 6b are very imilar and undertanding hould not be difficult once Fig. 5a i undertood. A dicued in the lat ection, r provide zero-current turn on of all witche and C r and C r provide zero-voltage turn off of witche S, S, and, S 4 repectively. C i the SD that control the ZC and ZC energy. The inductor and hare the ame magnetic core and are much larger than r. They are ued to tranfer the energy in C to the bu upply. The operation will be decribed with the load current in the direction hown and the duty ratio, D, defined for the on time of witche S and S 4. Operation for the oppoite current direction ha ymmetrical characteritic. Stage (t o -t ): At time t o, witche S and S 4 are on and will be conducting the load current direction hown in Fig. 7a. The energy in C i being partially tranferred to through witch S with the current in defined a: D D S DS S D r S Stage (t -t ): At time t, S and S 4 are turned off. The ZC and load current, I o, will charge and dicharge C r and C r repectively a hown in Fig. 7b. C r i charged through path C, D and C r i dicharged through D 3. The d/dt of and are ds dt 4 I C o r d dt ( ) I + i t -t C o 0 At time t, Cr bu and Cr - c and the anti-parallel diode of S and tart conducting. The off voltage of S and S 4 i clamped to bu +. Stage 3 (t -t 4 ):The load current and i path i hown in Fig. 7c where C i being charged. The energy in tranfer to the input upply and C control the ZC current until it reache -I o. At time t 3, i reache zero amp. At thi time, due to the coupling of and S, the voltage acro D S6 will drop from bu - to zero and become forward biaed. then tart conducting. At time t 4, the current in r reache I o and diode D,,3,4 top conducting. Thi complete the witch tranition and the voltage acro S and S 4 return to bu. If the time duration of tage i much maller than tage 3, then the witch tranition time can be approximated a follow: I o ttp t4 - t» The energy tranferred to the capacitor during thi tage i c r r (6) (7) W_ in r ( ) r. (8) Stage 4 (t 4 -t 5 ): Fig. 7d how the current conduction path. The energy in i being partially tranferred to whoe current during thi tage i defined by i - 3. (9) c () t ( t t ) Thi current ubtract from the load current though the antiparallel diode of : c i ( t) - + ( t- t3 ) (0) The approximate energy flowing out of the capacitor during thi tage and tage i found by auming and are not coupled and are equal. The energy flowing out i the um of 5

6 r D D r D D T urn-off: t tp Turn-on D Cr Cr DS D S5 D S6 S D C r Cr D S S - bu+ bu D r S r S I 0 I I r D D D D C D C r S D Cr S -I0 Cr DS C r DS I I S (c) S (d) S bu Cr r r (e) D D Cr D Cr DS S the energy in and at the end of tage and 4. Thi energy can be found by replacing time with DT and (-D)T in (4) and (9) repectively. From thi, the total energy taken from C can be found. W D S5 D S6 S _ out» Fig. 7. Operating Stage of Soft Switching Full Bridge: tage (to-t); tage (t-t), (c) tage 3 (t-t4); (d) tage 4 (t4-t5); (e) tage 5 (t5-t7); (6) tage 6 (t7-to). (f) ( - ) + ) c T D D () Stage 5 (t 5 -t 7 ): At time t 5, and are turned on with zero current. The current rie of and i dis dt 4, bu, () r Equation () aume that the current in r plit equally between path S -S and -S 4 a hown in Fig. 7e. The current r will ramp up until it reache I o at time t 6 and antiparallel diode of S and will tart to recover. In addition, during thi tage both and are conducting. Becaue the core are coupled, a voltage of i impoed acro the leakage inductance, kg, of the - coupling. Thi will caue the current in witch S to have an additional di/dt current of di _ dt D D C r D Cr DS C S extra S (3) kg S - Cr t t t 3 t 4 Fig. 8. Theoretical waveform By deigning and coupling o that kg i much greater than r, and becaue c i much maller than bu it will have little effect and can be neglected. At time t 7 the diode recover and the tage end. Stage 6 (t 7 -t 0 ): Once the anti-parallel diode of S and recover at t 7, capacitor C r and C r will reonant with r until their voltage are reet to c and bu repectively. The current in will top and will tranfer it energy to the output. C r reonate with r through D and S. C r reonate with r through C and D 4. Thee two loop are effectively conducting in parallel providing an equivalent reonating frequency and impedance of: w n r C + C ( r r ) r z n C r + C r The capacitor voltage and inductor r current during thi period are defined a follow: () ( ) Cr t bu co w nt () () t - - t Cr bu c Cr bu i () r t + in( w nt) (4) z Once the cr - c and cr bu the voltage will be clamped and the added energy in r will be tranferred to C through D,,3,4 At time t 8, the added energy in r ha completely tranferred to C and the current I r equal I o completing the tage. The approximate energy that wa tranferred into C from C r and C r equal n t 5 t 6 t 7 t 8 t 0 [ ( ) ( )] Wc_ in Cr bu + + Cr bu -.(5) 6

7 The current in reache zero at time t 0 and will tart conducting. I. ANAYSIS AND DESIGN The advantage of the propoed oft witching method for inverter i that they are paive o that no additional witche or control circuitry need to be ued. However, thi paive nature mean that the operation of the auxiliary circuit i dependent on the main witch operation and load current value. The component value therefore need to be deigned to enure oft witching and minimize the voltage tre acro the witche under all circuit tate. To ummarize the deign procedure, r and C r, are choen to often the witch turn on and turn off., are choen large enough to enure oft witching over the complete load range but mall enough to limit the witch voltage tre below the deigned value. C i relatively large to tore energy from cycle to cycle and control the ZC energy, but mall enough to provide oft witching under dynamic condition. The deign conideration apply to the full-bridge turn-on nubber inverter with current in the direction hown in fig. 7 and duty ratio D for witche S and S 4. The operation of the half bridge can be imilarly derived with little modification. Additionally, the deign conideration for an added turn-off nubber are given later. The operation in the oppoite current direction ha ymmetrical equation and value. A. Capacitor voltage The capacitor voltage i dependent on the ize of the ZC and ZC and the output current level. For the turn-on nubber only, the capacitor voltage can be determined by examining the energy flowing into the capacitor from the ZC and out of the capacitor by and. Equating (8) and () reult in a quai-tatic expreion of capacitor voltage: c r T ( - D) + D (6) Here it i aumed that the output current frequency, Fo, i much lower than the witching frequency (i.e. F/Fo > 00). ater dicuion will focu on the value of C and what happen at higher output current frequencie. B. Minimum Capacitor voltage The capacitor voltage in (6) mut be large enough to enure oft witching over the complete load range. In order for oft witching to be maintained the witch tranition period after S and S 4 are turn off, t tp, mut be maller than the off time of the witche. t tp ( ) - D T (7) Otherwie, D,,3,4 will till be conducting when S and S 4 are turned on again and zero-current turn on will no longer be atified. Subtituting (7) in (7) give a minimum value for the capacitor C. A ymmetrical minimum capacitor voltage i found when current i negative. c_min c_min I o r > 0 ( - DT ) I o r - < 0 DT (8) C. Minimum, value Setting (6) greater than (8) and etting D D reult in a value for the nubber inductor with. r ³ + D ( - D ) (9) Equation (9) i a very important reult. With a proper / r ratio, oft witching i enured regardle of the load or upply voltage. D. Maximum Capacitor voltage The inductor wa added to the yntheized reult to create an automatic elf-limiting feature on the capacitor C voltage. Thi can be een by auming and are uncoupled, and viewing the recovery circuitry a two interleaved buck-boot converter with a the input ource, bu a the output, and S and a the witche. Under mot condition, they will operate in dicontinuou inductor operation a wa aumed with (6). However, when duty ratio i at either extreme (i.e. mall or large), and the capacitor voltage i above a certain value, one of the inductor will enter continuo conduction mode of operation. In thi mode, the inductor current will increae until the capacitor voltage reache a value o that the inductor are voltage econd balanced. Thi place a imum capacitor voltage level on the converter: æ - D D D D _ min ç, è - c bu bu ö ø (0) Therefore, both (0) and (6) mut be larger than the minimum capacitor voltage level, (8), for oft witching. E. Maximum ZC r value for oft witching Setting (0) greater than (8) define the larget value of r that can be ued and till enure oft witching. r _ ( - D ) D I bu T () Where I i the peak output current. F. Determining The analyi aumed that although C wa relatively large, it value wa till mall enough o that change in output current would to allow the capacitor voltage to tay above 7

8 30 c (t) 0 c_min (t) 0 0 c_min. However, thi place requirement on the value for C. What i needed, i to undertand how the capacitor voltage will change in a dynamic condition or when the output current frequency increae with repect to the witching frequency. Circuit average modeling a explained in [] provide a powerful and eay method. Auming that the witching frequency i till more that 0 time the output current frequency, the average capacitor C voltage can be approximated from the average capacitor C current during each witching cycle. () () t C ò I t dt () Where I i defined for the turn-on full-bridge nubber a W_ in -W _ out I () t T. (3) I r o T - ( ( ) ) T D + - D With I o (t), c (t), and D(t) all function of time. Equation () i ued to find C for the wort cae condition when I o (t) i in phae with D(t) and it frequency and power are imized for a given ytem. Fig. 9 how the theoretical dynamic of c(t) for a tep change in load at an output frequency of 5kHz uing the parameter from the 00kHz experimental ytem. In the figure, c (t) i alway greater than c_min (t) maintaining oft witching. G. Deign with Turn-off nubber Any oft turn-on full-bridge deign that maintain oft witching over the complete operating range will alo maintain oft witching with an added turn-off nubber a hown in Fig. 5a. Equation (5) how that C r, add a contant amount of energy into C each witching cycle. Therefore, the only deign concern are the added voltage tre acro the main witche and the peak current through the witche when the capacitor i reet. The elf-limiting feature of the circuit, even with a large turn-off nubber, till maintain a low C voltage. Quantitatively, the quai-tatic capacitor voltage can be found by equating input and output p time (rad) Fig. 9. c(t) for a tep change in output power and frequency p 3 Fig. 0. Experimental waveform: : I, 0amp/div; : I r, 0amp/div; 3: d: 00volt/div; Horizontal cale: 0uec/div Efficiency (%) 89,0 88,0 87,0 86,0 85,0 84, Output Power (W att) Fig.. Efficiency Tet at Fo 40Hz; () Hard Switching; () Turn-on Snubber; energy flow of the capacitor (i.e.win _in + Win _in Win _out ) by uing (8),(5), and (). For higher frequency dynamic, (3) can be modified a follow: W_ in+ W _ in-w _ out I () t (4) T The peak witch current at turn on are found from (4) and equal: i S I + bu o z (5). EXPERIMENTA RESUTS FOR SOFT TURN-ON FU-BRIDGE EXAMPE CIRCUIT A 500-Watt experimental oft turn-on inverter wa built to verify operation. IRFP460 MOSFET were ued a the main witche. Becaue MOSFET do not have the current tail characteritic of minority carrier device, the major loe are caued by the anti-parallel diode at turn on. For thi reaon, the turn-off nubber verion of the circuit wa not ued. The ytem parameter included: F 00kHz, r.7uh, C uf, 40uH, and kg 30uH. Fig. 0 how the experimental waveform for the voltage and current through witch S. At turn off, notice how the voltage acro the witch i clamped below 50volt until the n 8

9 ZC inductor change polarity and finihe the witch tranition period. At turn on, the voltage acro the witch can drop well before the current increae, providing zerocurrent turn on. The current pike acro the witch i caued by the revere recovery of S anti-parallel diode and the charging of it drain to ource capacitance. Fig. how the improved performance the turn-on nubber provide over the hard-witched converter. It maintain more than % improvement over a wide power range at an output frequency of 40Hz. I. CONCUSION Promiing lole oft-witching full-bridge inverter were decribed that lower witch and diode tre and lower component count compared to other previouly propoed lole inverter. A imilar oft witching half-bridge wa alo hown. Thee inverter were example from the reult of a ynthei procedure for the creation of lole paive oft witching converter. The ynthei procedure ue a et of propertie to find all the baic oft witching topologie for a given converter. The baic oft-witching topologie decribed where the ZC and ZC are needed for oft witching. Then, a et of circuit cell i added to recover the energy in the ZC and ZC for lole operation. Uing a ingle ZC, There are a total of 8 and 3 baic oft-witching topologie for the full-bridge and half-bridge inverter repectively. With the given circuit cell, everal oftwitching inverter can be realized for each baic oftwitching topology. Other circuit cell are alo poible, reulting in virtually limitle number of lole paive oft-witching converter that can be created and thi paper how how. REFERENCES [] K. M. Smith Jr. and K. M. Smedley, Propertie and Synthei of ole, Paive Soft Switching Converter, IEEE Energy, Power, and Motion Control Conference Rec., 997. [] A. Pietkiewicz and D. Tollik, "Snubber circuit and MOSFET paralleling conideration for high power boot-baed power-factor corrector, Intelec Conf. Rec., 995, pp [3], Snubber circuit and MOSFET paralleling conideration for high power boot baed power factor correction, Intelec conf. preentation, 995. [4] W. McMurray, Selection of nubber and clamp to optimize the deign of tranitor witching converter IEEE Tran. on Ind. Applicat., vol. IA-6, no. 4., pp , Jul./Aug [5] I. Jitaru, Soft Tranition Power Factor Correction Circuit, HFPC Conf. Rec., 993. [6] N. Machin and T. ecovi, ery high efficiency technique and their elective application to the deign of a 70A rectifier, INTEEC Conf. Rec., 993, pp [7] M. ilela, E. Coelho, J. ieira Jr., de Freita, and. Faria, PWM oft-witched converter uing a ingle active witch IEEE APEC Conf Rec., 996, vol. pp [8] S. Ben-Yakov, analyi of nubber circuit IEEE APEC Conf. Rec., 997, pp. [9] E. Calkin and B. Hamilton, Circuit Technique for Improving the Switching oci of tranitor witche in witching regulator, IEEE Tran. on Ind. Applicat., vol A-, no. 4, pp , July/Augut, 976. [0] T. Undeland, F. Jenet, A. Steinbakk, T. Rogne, M. Herne, A nubber configuration for both power tranitor and GTO PWM inverter, IEEE PESC Conf. Rec., 984, pp [] J. Holtz, S. Salma, and K. H. Werner, A nondiipative nubber circuit for high-power GTO Inverter, IEEE Tran. on Ind. Applicat., vol. 5, no. 4, pp , July/Augut 989 [] W. McMurray, Efficiency Snubber for voltage-ource GTO inverter, IEEE Tran. on Power Electron., vol. PE-, no. 3, pp. 64-7, July. 99 [3] X. He, S. Finney, B. William and T. Green, An improved paive lole turn-on and turn-off nubber, IEEE APEC Conf. Rec., 993, pp [4], Paive ole turn-on nubber energy recovery in high frequency power converter, IEEE IECON Conf Rec., 993, vol. pp [5] A. Brambilla and E. Dallago, Analyi and Deign of Snubber Circuit for High-Power GTO DC-DC converter, IEEE Tran. on Power Electron., vol. 9, no., pp. 7-7, Jan 994 [6] X. He, S. Finney, B. William, and Z. Qian, Bridge eg nubber for GTO thyritor inverter, IEEE IAS Conf. Rec., 995, vol.. pp [7], Novel paive lole oft-clamped nubber for voltage ource inverter, IEEE APEC Conf. Rec., 996, vol., pp [8]. Barboa, J. ieira Jr., de Freita, M. ilela, and. Faria, A buck quadratic PWM oft-witching converter uing a ingle active witch. IEEE PESC Conf. Rec., 996, pp [9] C. Braz, J. andelac, and P. Zioga, Some deign apect of fully and partially regenerative active nubber network, Intern. Conf. on Indut. Electron., Cont., Intrumen. and Autom. Power Electron. and Motion Cont. Conf. Rec., 99, pp [0] D. Makimovic, Synthei of PWM and Quai-Reonant DC-to-DC Power Converter, Ph.D. Thei, California Intitute of Technology, 989. [] D. Makimovic and C. Cuk, General propertie and ynthei of PWM DC-to-DC converter, IEEE PESC Conf Rec., 989. [] J. Kaakian, M. Schlecht, and G. erghee, Principle of Power Electronic, Reading, MA: Addion-Weley Pub. Co., 99. [3] S. Cuk and R. Middlebrook, Advance in Switched Mode Power converion, vol I,II,III..TESAco 98 and 983. [4] S. Sehu, and M. B. Reed, inear Graph and Electrical Network, Reading, MA, Addion-Weley Pub. Co., 96. 9