Preliminary Datasheet

Transcription

1 Product Description Figure 2. Package Type The is a digitally controlled variable gain amplifier (DVGA) in a 6x6mm LGA package, with a frequency range of 4400 to 5000 MHz and an operating Vcc of 5.0V. is high performance and high dynamic range makes it ideally suited for use in 5G/LTE wireless infrastructure and other high performance wireless RF applications. The is an integration of a high performance digital 7- step attenuator (DSA) that provides a 3.75 db attenuation range in 0.25 db steps, and high linearity broadband gain block amplifiers featuring high ACP and PdB. The digital control interface supports serial programming of the attenuator, and includes the reference gain (max gain, bypass) state on the Parallel programing. The is integrated of two gain block (AMP, AMP2), a digital step attenuator (DSA) and high linearity amplifier (AMP3). Implementation requires only a few external components, such as matching capacitors on the Input and Output pins. (Don t need DC Blocking Capacitor) Figure. Functional Block Diagram Device Features 28-lead 6 x 6 x 0.95mm LGA 28-Pin 6 x 6 x 0.95mm LGA Package Integrated Amp + DSA + Amp2 + Amp3 A Single +5.0V supply MHz Frequency Range 36.3dB Gain at 4.65GHz 4.0dB Noise Figure at max gain setting at 4.65GHz 26.2dBm Output PdB at 4.65GHz 4dBm Output IP3 at 4.65GHz ACP at 4.65GHz, 50dBc - Pre5G 00MBW (±00MHz offset ) 4.5dBm - LTE 20MBW(FDD E-TM3., 00RB, ±20MHz offset ) 6.0dBm Attenuation: 0.25 db step up to 3.75 db Glitch-less attenuation state transitions High attenuation accuracy ±(0.5dB + 6% x GHz Programming Interface - Serial / Parallel (Bypass Mode) Application 5G/4G/3G wireless Infrastructure Small Cells Repeaters

2 Table. Electrical Specifications Typical Performance 25 and Vcc = 5.0V, ATT=0dB state (Max. gain) unless otherwise noted. ( De-embedded PCB and connector Loss) Parameter Condition Min Typ Max Unit Operational Frequency Range MHz Gain Attenuation = 0dB, at 4650MHz 36.3 db Attenuation Control range 0.25dB step 3.75 db Attenuation Step 0.25 db Attenuation Accuracy 4.4GHz 5GHz Any bit or bit combination -(0.5 +6% of atten. setting) +(0.5 +6% of atten. setting) db Return loss Input Return Loss 0 Attenuation = 0dB Output Return Loss 5 db Output Power for db Compression Attenuation = 0dB, at 4650MHz 26 dbm Output Third Order Intercept Point Attenuation = 0dB, at 4650MHz Pout= +5dBm/tone f = MHz. 4 dbm Noise Figure Attenuation = 0dB, at 4650MHz 4.0 db Switching time 50% CTRL to 90% or 0% RF 275 ns Supply voltage DSA V AMP V Supply Current AMP+DSA+AMP2+AMP3 30 ma Control Interface Serial mode 8 Bit Control Voltage Digital input high V Digital input low V Impedance 50 Ω Device performance _ measured on a BeRex Evaluation board at 25 C, 50 Ω system, Vcc=+5.0V, measure on Evaluation Board 2

3 Table 2. Typical RF Performance Parameter Frequency Unit Frequency MHz Gain db S db S db OIP dbm PdB dbm LTE20M ACP dbc Pre5G 00M ACP dbc N.F db Device performance _ measured on a BeRex evaluation board at 25 C, Vcc=+5.0V, 50 Ω system. measure on Evaluation Board De-embedded PCB and Connector Loss. 2 OIP3 _ measured with two tones at an output of +5 dbm per tone separated by MHz. 3 LTE set-up: 3GPP LTE, FDD E-TM3., 20MHz BW, ±20MHz offset, PAR 9.8 at 0.0% Prob. Output power 0dBm. Applied the Noise correlation function of Instrument. 4 5G set-up: 3GPP Pre5G, 00MHz BW, ±00MHz offset. Output Power 0dBm. Applied the Noise correlation function of Instrument. Table 3. Absolute Maximum Ratings Parameter Min Typ Max Unit Supply Voltage(VCC) V Supply Current 580 ma Digital input voltage V Maximum input power 20 dbm Storage Temperature Junction Temperature 50 Operation of this device above any of these parameters may result in permanent damage. Table 4. Recommended Operating Conditions Parameter Min Typ Max Unit Bandwidth MHz Supply Voltage(VCC) V Operating Temperature C R TH 50 C/W 3

4 Programming mode Table 5. Serial Attenuation word Truth Table Serial / Parallel (Bypass) Selection Either a Serial or Parallel interface can be used to control the P/S Pin. The P/S bit provides the selection, with P/S = HIGH or floating selecting the Serial interface and P/S = LOW selecting the Parallel interface (Bypass Mode, Max Gain State). Serial Interface The Serial interface is an 8-bit Serial-In, Parallel-Out shift register buffered by a transparent latch. The 8-bits make up the Attenuation Word that controls the DSA. Figure 4 illustrates an example timing diagram for programming a state. The Serial interface is controlled using three CMOS compatible signals: SI, Clock (CLK) and LE. The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. The Attenuation Word truth table is listed in Table 5. A programming example of the serial register is illustrated in Figure 3. The Serial timing diagram is illustrated in Figure 4. D7 (MSB) Attenuation Word D6 D5 D4 D3 D2 D D0 (LSB) Attenuation setting L L L L L L L L Max. Gain L L L L L L L H 0.25 db L L L L L L H L 0.5 db L L L L L H L L db L L L L H L L L 2 db L L L H L L L L 4 db L L H L L L L L 8 db L H L L L L L L 6 db L H H H H H H H 3.75 db Figure 3. Serial Register Map MSB (last in) LSB (first in) Q7 Q6 Q5 Q4 Q3 Q2 Q Q0 D7 D6 D5 D4 D3 D2 D D0 Bit must be set to logic low Attenuation Word The attenuation word is derived directly from the value of the attenuation state. To find the attenuation word, multiply the value of the state by four, then convert to binary. For example, to program the 2.5dB state; 4 x 2.5 = Serial Input :

5 Figure 4. Serial Interface Timing Diagram Bits can either be set to logic high or logic low D[7] must be set to logic low DI[6:0] P/S SI TDISU TPSSU D[0] D[] [D2] D[3] D[4] D[5] D[6] D[7] TDIH TPSIH CLK TSISU TSIH TCLKL TCLKH LE DO[6:0] TLESU TLEPW TPD Valid Table 6. Serial Interface AC Characteristics Vcc= 5.0V with DSA only, -40 C < TA < 85 C, unless otherwise specified Symbol Parameter Min Max Unit FCLK Serial data clock frequency 0 MHz TCLKH Serial clock HIGH time 30 ns TCLKL Serial clock LOW time 30 ns TLESU Last Serial clock rising edge setup time to Latch Enable rising edge 0 ns TLEPW Latch Enable minimum pulse width 30 ns TSISU Serial data setup time 0 ns TSIH Serial data hold time 0 ns TDISU Parallel data setup time 00 ns TDIH Parallel data hold time 00 ns TPSSU Parallel / Serial setup time 00 ns TPSIH Parallel / Serial hold time 00 ns TASU Address setup time 00 ns TAH Address hold time 00 ns TPD Digital register delay (internal) 0 ns 5

6 Figure 5. Pin Configuration Vcc_SPI NC SPI_LE AMP2 2 SPI_DATA 2 SPI DSA 20 SPI_CLK 3 9 P/S 4 AMP3 8 5 AMP 7 RF_IN 6 6 RF_OUT 7 DC Bias DC Bias Vcc_AMP/ AMP2 Vcc_AMP3 Table 7. Pin Description Pin Pin name Description LE Serial Latch Enable Input. When LE is high, latch is clear and content of SPI control the attenuator. When LE is low, data in SPI is latched. 2 DATA 3 CLK Serial Clock Input. 4 P/S Serial Data Input. The data and clock pins allow the data to be entered serially into SPI and is independent of Latch state. The P/S bit provides this selection, P/S=Low selecting the Parallel Interface which is the Max. Gain state (Bypass Mode, ATT=0dB) and either P/S=High selecting or floating for the Serial Interface. 6 RF IN RF Input, matched to 50 ohm. Internally DC blocked. 8 VCC_AMP/AMP2 Supply Voltage to AMP and AMP2. This pin is connected internally to bypass capacitors followed by inductor inside the module. 4 VCC_AMP3 Supply Voltage to AMP3. This pin is connected internally to bypass capacitors followed by inductor inside the module. 6 RF OUT RF output, matched to 50 ohm. Internally DC blocked. 22 N/C No connect or open. This pin is not connected. 28 VCC_SPI SPI and DSA DC supply. This pin is connected to bypass capacitor internally. 5, 7, 9-3, 5 7-2,23-27 RF/DC Ground Backside Pad RF/DC Ground Note:. LE must be Pulled-up to.7v 3.6V to use the Bypass Mode when P/S = Low (Bypass mode, ATT=0dB) 6

7 Figure 6. Internal Function Block Diagram The is integrated of two gain block (AMP, AMP2), a digital step attenuator (DSA) and high linearity amplifier (AMP3). The internal structure of the Package is shown below. Vcc_Amp3 (Pin 4) Vcc_SPI (Pin 28) P/S (Pin 4) CLK (Pin 3) DATA (Pin 2) LE (Pin ) Vcc_Amp/Amp2 (Pin 8) DC Bias DC Bias DC Bias DC Bias SPI RF Input (Pin 6) DC Block Matching Block AMP DC Block Matching Matching DSA AMP2 AMP3 Block Block DC Block DC Block Matching Block DC Block RF Output (Pin 6) 7

8 Typical RF Performance Plot - EVK - PCB Typical Performance 25 and Vcc = 5.0V unless otherwise noted and RF Circuit Table 8. Application Circuit Vcc 5V RF Input SPI_LE SPI_DATA SPI_CLK SMA P/S C5 R8 C3 C4 SPI_LE SPI_DATA SPI_CLK P/S RF_IN Schematic Diagram C Vcc_SPI NC U 28Pin 6x6 LGA RF_OUT C4 SMA RF Output BOM Ref Size Value C uf C pf C uf C pf C uf C pf C pf C pf C pF R Ω R Ω R Ω Remark Vcc_AMP2 Vcc_AMP3 C8 C9 C7 R6 R7 C0 Vcc 5V 3 2 NOTE. C, C2, C3, C5, R are NC 2. R2 = 00 KΩ, R3=200 KΩ 3. R4, R5 = 0 Ω 4. C = 00pF, C2=uF 5. J2 Information - Not connected (Floating) : Serial Mode - Connected -2 : Serial Mode - Connected 2-3 : Bypass mode (Max Gain State) 6. J9 Information - Pin, 2 : 5Vdc - Pin 3, 4 : Ground

9 Typical RF Performance Plot - EVK Typical Performance 25 and Vcc = 5.0V unless otherwise noted. (All data de-embedded PCB and Connector Loss) Table 9. Typical Performance : 4650MHz parameter Typical Values Units Frequency MHz Vcc Vdc Current ma Gain db S db S db OIP dbm PdB dbm Noise Figure db LTE20MHz ACP dbc Pre5G 00MHz ACP dbc OIP3 _ measured with two tones at an output of 5 dbm per tone separated by MHz. 2 LTE set-up: 3GPP LTE, FDD E-TM3., 20MHz BW, ±20MHz offset, PAR 9.8 at 0.0% Prob. Output Power 0dBm. Applied the Noise correlation function of Instrument. 3 Pre5G set-up: 3GPP Pre5G, 00MHz BW, ±00MHz offset. Output Power 7dBm. Applied the Noise correlation function of Instrument. Figure 7. Gain vs Gain state Figure 8. Gain vs Gain state Figure 9. Gain vs Gain state Figure 0. Gain vs Gain state 9

10 Typical RF Performance Plot - EVK Typical Performance 25 and Vcc = 5.0V unless otherwise noted. (All data de-embedded PCB and Connector Loss) Figure. Input Return Loss vs Frequency Figure 2. Output Return Loss vs Frequency Figure 3. Gain vs Attenuation Settings Figure 4. Attenuation Error vs Frequency Figure 5. Attenuation Error vs Temp vs Attenuation 4650MHz Figure 6. Attenuation Error vs Frequency vs Attenuation Settings 0

11 Typical RF Performance Plot - EVK Typical Performance 25 and Vcc = 5.0V unless otherwise noted. (All data de-embedded PCB and Connector Loss) Figure 7. OIP3 vs Frequency vs Output Power ATT=0dB (Max. Gain), MHz interval Figure 8. OIP3 vs Frequency vs Output Power ATT = 5dB, MHz interval Figure 9. OIP3 vs Vcc vs Output Power Fo = 4650MHz, ATT=0dB (Max. Gain), MHz interval Figure 20. OIP3 vs Vcc vs Output Power Fo = 4650MHz, ATT=5dB, MHz interval Figure 2. OIP3 vs Temp. vs Output Power Fo = 4650MHz, ATT=0dB (Max. Gain), MHz interval Figure 22. Pin-Pout-Gain 4650MHz

12 Typical RF Performance Plot - EVK Typical Performance 25 and Vcc = 5.0V unless otherwise noted. (All data de-embedded PCB and Connector Loss) Figure 23. OPdB vs Temp vs Frequency Figure 24. OPdB vs Vcc vs Frequency Figure 25. ACP vs Frequency vs Pout ATT=0dB (Max. Gain), Pre5G 00MBW Figure 26. ACP vs Frequency vs Pout ATT=5dB, Pre5G 00MBW Figure 27. ACP vs Vcc vs Pout F0=4650MHz, ATT=0dB (Max. Gain), Pre5G 00MBW Figure 28. ACP vs Vcc vs Pout F0=4650MHz, ATT=5dB, Pre5G 00MBW 2

13 Typical RF Performance Plot - EVK Typical Performance 25 and Vcc = 5.0V unless otherwise noted. (All data de-embedded PCB and Connector Loss) Figure 29. ACP vs Temp. vs Pout Fo = 4650MHz, ATT=0dB (Max. Gain), Pre5G 00MBW Figure 30. ACP 4650MHz, 7dBm, Pre5G 00MBW Figure 3. ACP 4650MHz, 50dBc, Pre5G 00MBW Figure 32. ACP 4650MHz, 50dBc, LTE20MHz (E-TM. 00RB) Figure 33. Noise Figure vs Temp vs Frequency 3

14 Figure 34. Evaluation Board Schematic Vcc 5V 2 R R2 R3 J2 Vcc 5V R8 C4 C6 Vcc_SPI NC C3 TP TP2 TP3 TP4 C5 C C2 P/S SPI_LE SPI_CLK SPI_DATA RF Input SPI_LE SPI_DATA SPI_CLK SMA P/S C5 C3 SPI_LE SPI_DATA SPI_CLK P/S RF_IN U 28Pin 6x6 LGA RF_OUT C4 SMA2 RF Output J Vcc_AMP2 Vcc_AMP3 C8 C9 C7 R6 R7 C0 Vcc 5V C C2 J9 Table 0. Bill of material No. Ref. Number Value Description Manufacturer R2 00KΩ Resistor, 0603, Chip, 5% KOA Speer 2 R3 200KΩ Resistor, 0603, Chip, 5% KOA Speer 3 R6 0Ω Jumper Resistor, 0603, Chip KOA Speer 4 R7 0Ω Jumper Resistor, 0603, Chip KOA Speer 5 R8 0Ω Jumper Resistor, 0603, Chip KOA Speer 6 C4 00nF Capacitor, 0402, Chip, 5% Murata 7 C6 00pF Capacitor, 0402, Chip, 5% Murata 8 C7 00nF Capacitor, 0402, Chip, 5% Murata 9 C8 00pF Capacitor, 0402, Chip, 5% Murata 0 C9 00pF Capacitor, 0402, Chip, 5% Murata C0 00nF Capacitor, 0402, Chip, 5% Murata 2 C uf Capacitor, 0603, Chip, 5% Murata 3 C2 nf Capacitor, 0603, Chip, 5% Murata 4 C3 0.3pF Capacitor, 0402, Chip, ±0.pF Murata 5 C4 0.5pF Capacitor, 0402, Chip, ±0.pF Murata 6 C5.2pF Capacitor, 0402, Chip, ±0.2pF Murata 7 SMA SMA SMA(F) Connector, PCB Mount, PSF-S0-007 Gigalane 8 SAM2 SMA SMA(F) Connector, PCB Mount, PSF-S0-007 Gigalane 9 J 20pin Receptacle Connector, , Female,RT/A Dual AMP Connectors 20 J2 3pin 2.54mm Breakaway Male Header, Straight, Black 2 J9 4pin 2.54mm Breakaway Male Header, Straight, Black 22 R,C,C2,C3,C5 NC Not connected 4

15 Figure 35. Evaluation Board Layout [Top View] [Bottom View] Figure 36. Evaluation Board PCB Layer Information COPPER : oz (0.035mm), Top Layer RO4003C Er : 3.38 RO4003C / 0.305mm COPPER : oz (0.035mm), Inner Layer FR-4 Er : 4.5~4.8 FR-4 / 0.36mm FINISH THICKNESS :.55T COPPER : oz (0.035mm), Inner Layer FR-4 Er : 4.5~4.8 FR-4 / 0.73mm COPPER : oz (0.035mm), Bottom Layer 5

16 Figure 37. Suggested PCB Land Pattern and PAD Layout 6

17 Figure 38. Packing Outline Dimension 0.0 C 2X PIN # IDENTIFIER 6.00± x 0.70 Pitch PIN # IDENTIFIER (28 x) 0.45 x Ø 0.0 M C A B ± x C 2X TOP VIEW BOTTOM VIEW 0.95± ± C 0.08 C 0.25±0.04 SIDE VIEW C Notes. All dimensions are in millimeters. Angles are in degrees 2. Dimension and tolerancing conform to ASME Y4.5M-994. Figure 39. Package Marking Information 7

18 Figure 40. Tape and Reel 0.30± MAX 2.00± ±0.0 ø ± ±0.0.75± ±0.30 ø.50 Min.0± ± ±0.0 Package information : Tape Width : 6mm / Reel Size : 7 inches Device Cavity Pitch : 2mm / Devices Per Reel :,000 EA Lead Plating Finish 00% Tin Matte finish (All BeRex products undergoes a hour, 50 degree C, Anneal bake to eliminate thin whisker growth concerns.) MSL / ESD Rating ESD Rating : Value : Test : Standard : ESD Rating : Value : Test : Standard : MSL Rating : Standard : ClassC Passes > 000V Human Body Model (HBM) JEDEC Standard JESD22-A4B ClassC3 Passes > 000V Charged Device Model (CDM) JEDEC Standard JESD22-C0F MSL3 at +265 C convection reflow JEDEC Standard J-STD-020 Caution : ESD Sensitive Appropriate precautions in handling, packaging and testing devices must be observed. Proper ESD procedures should be followed when handling the device. NATO GAGE Code : 2 N 9 6 F 8