Preliminary Datasheet

Transcription

1 BVAB -4 MHz Product Description Figure. Package Type The BVAB is a digitally controlled variable gain amplifier (DVGA) is featuring high linearity using the voltage V supply with a broadband frequency range of to 4 MHz. The BVAB integrates a high performance digital step attenuator and a high linearity, broadband gain block. using the small package(4x4mm QFN package) and operating VDD V voltage. and designed for use in G/4G wireless infrastructure and other high performance RF applications. Both stages are internally matched to Ohms and It is easy to use with no external matching components required. A serial output port enables cascading with other serial controlled devices. An integrated digital control interface supports both serial and parallel programming of the attenuation, including the capability to program an initial attenuation state at power-up. Covering a. db attenuation range in. db steps. The BVAB is targeted for use in wireless infrastructure, point-topoint, or can be used for any general purpose wireless application. Figure. Functional Block Diagram D 4 D D4 RF P/S VSS/ 9 8 Device Features 4-lead 4x4 mm QFN Small 4-Pin 4 x 4 mm QFN Package Integrate DSA to Amp Functionality Wide Power supply range of +.7 to +.V(DSA) Single Fixed +V supply(amp) -4MHz Broadband Performance.dB Gain at.4ghz.9db Noise Figure at max gain setting at.4ghz.6dbm PdB at.4ghz 9.dBm OIP at.4ghz No matching circuit needed Attenuation:. db steps to. db Safe attenuation state transitions Monotonicity:. db up to 4 GHz High attenuation accuracy (DSA to Amp) ±(. + % x GHz.8V control logic compatible Programming modes - Direct Parallel - Latched Parallel - Serial Unique power-up state selection D 7 D 6-Bit Digital Step Attenuator 6 VDD D 4 PUP AMPOUT 6 Gain Block AMPLIFIER 4 PUP LE Application AMPIN RF SERIN CLOCK G/4G Wireless infrastructure and other high performance RF application Microwave and Satellite Radio General purpose Wireless All other trademarks are the property of their respective owners. 8 BeRex Rev..

2 BVAB -4 MHz Table. Electrical Specifications Parameter Condition Min Typ Max Unit Operational Frequency Range 4 MHz Gain Attenuation = db, at 9MHz db Attenuation Control range.db Step. db Attenuation Step. db MHz GHz ±(. + % of atten setting) Attenuation Accuracy >GHz.GHz >.GHz GHz Any bit or bit combination ±(. + % of atten setting) ±(. + 8% of atten setting) db >GHz 4GHz ±(. + % of atten setting) Return loss GHz.GHz Attenuation = db (input or output port) >.GHz 4GHz 6 db Output Power for db Compression Attenuation = db, at 9MHz 6. dbm Output Third Order Intercept Point Attenuation = db, at 9MHz two tones at an output of dbm per tone separated by MHz. 9.8 dbm Noise Figure Attenuation = db, at 9MHz.7 db Switching time % CTRL to 9% or % RF 8 ns Supply voltage DSA.7. V AMP V Supply Current 48 6 ma Control Interface Serial / parallel mode 6 Bit Control Voltage Digital input high.7.6 V Digital input low -..6 V Impedance Ω Device performance _ measured on a BeRex Evaluation board at C, Ω system, VDD=+V, measure on Evaluation Board (DSA to AMP) Gain data has PCB & Connectors insertion loss de-embedded OIP _ measured with two tones at an output of dbm per tone separated by MHz. All other trademarks are the property of their respective owners. 8 BeRex Rev..

3 BVAB -4 MHz Table. Typical RF Performance Parameter Frequency Unit MHz Gain db S db S db OIP dbm PdB dbm Noise Figure db Device performance _ measured on a BeRex evaluation board at C, VDD=+V, Ω system. measure on Evaluation Board. (DSA to AMP) 7MHz measured with application circuit refer to table. Gain data has PCB & Connectors insertion loss de-embedded. 4 OIP _ measured with two tones at an output of dbm per tone separated by MHz. Table. Absolute Maximum Ratings Parameter Condition Min Typ Max Unit Supply Voltage(VDD) Amp/DSA.6/. V Supply Current Amp ma Digital input voltage -..6 V Maximum input power Amp/DSA +/+ dbm Operating Temperature Amp/DSA -4 8/ Storage Temperature - Junction Temperature Operation of this device above any of these parameters may result in permanent damage. All other trademarks are the property of their respective owners. 8 BeRex Rev..

4 BVAB -4 MHz Figure. Pin Configuration(Top View) D D D 4 Exposed Pad AMPOUT 6 AMPIN RF SERIN Clock D D D4 RF P/S 9 VSS/ VDD PUP PUP LE Table 4. Pin Description Pin Pin name Description,,7,9,7,8 Ground, These pins must be connected to ground D Parallel Control Voltage Inputs, Attenuation control bit db D Parallel Control Voltage Inputs, Attenuation control bit.db 4 D Parallel Control Voltage Inputs, Attenuation control bit 6dB 6 AMPOUT RF Gain block Amplifier output Port 8 AMPIN RF Gain block Amplifier input Port RF RF port (Digital Step Attenuator RF Input) This pin can also be used as an output because the design is bidirectional. RF is dc-coupled and matched to Ω SERIN Serial interface data input Clock Serial interface clock input LE Latch Enable input 4 PUP Power-Up State Selection Bits. These pins set the attenuation value at power-up (see Table ). There is no internal pull-up or pull- down PUP resistor on these pins; therefore, they must always be kept at a valid logic level (VCTLH or VCTLL) and not be left floating 6 VDD DSA Power Supply (nominal.v) 9 VSS/ External VSS negative voltage control or ground Do not want to use negative voltage supply, These pins must be connected to ground (, Default setting is ) P/S Parallel/Serial Mode Select. For parallel mode operation, set this pin to low. For serial mode operation, set this pin to High. RF RF port (Attenuator RF Output.) This pin can also be used as an input because the design is bidirectional. RF is dc-coupled and matched to Ω. D4 Parallel Control Voltage Inputs, Attenuation control bit 8dB D Parallel Control Voltage Inputs, Attenuation control bit 4dB 4 D Parallel Control Voltage Inputs, Attenuation control bit db EXPOSE PAD Exposed pad: The exposed pad must be connected to ground for proper operation Note:. RF pins and must be at V DC. The RF pins do not require DC blocking capacitors for proper Operation if the V DC requirement is met. Connect VssEXT (pin 9, VssEXT = ) to enable internal negative voltage generator All other trademarks are the property of their respective owners. 8 BeRex 4 Rev..

5 BVAB -4 MHz Programming Options Table. 6-Bit Serial Word Sequence BVAB can be programmed using either the parallel or serial interface, which is selectable via P/S pin(pin). Serial mode is selected by floating P/S or pulling it to a voltage logic LOW and parallel mode is selected by setting P/S to logic low Serial Control Mode The serial interface is a 6 bit shift register to shift in the data MSB (D) first. When serial programming is used, all the parallel control input pins (,,4,,,4) must be grounded. It is controlled by three CMOS-compatible signals: SERIN, Clock, and Latch Enable (LE). D D4 D D D D Attenuation 6dB Control Bit Attenuation 8dB Control Bit Attenuation 4dB Control Bit Attenuation db Control Bit Attenuation db Control Bit Attenuation.dB Control Bit Figure 4. Serial Mode Resister Timing Diagram P/S X LE tles CLK tln tlew SERIAL IN X D D4 D D D D X D[:] NEXT WORD X tsh tss MSB [FIRST IN] tsck LSB [LAST IN] The BVAB has a -wire serial peripheral interface (SPI): serial data input (Data), clock (CLK), and latch enable (LE). The serial control interface is activated when P/S is set to HIGH. In serial mode, the 6-bit Data is clocked MSB first on the rising CLK edges into the shift register and then LE must be toggled High to latch the new attenuation state into the device. LE must be set to low to clock new 6-bit data into the shift register because CLK is masked to prevent the attenuator value from changing if LE is kept High (see Figure 4 and Table 8). Table 6. Mode Selection Table 8. Truth Table for Serial Control Word P/S LOW HIGH Control Mode Parallel Serial Digital Control Input D D4 D D D D Attenuation (MSB) (LSB) (db) LOW LOW LOW LOW LOW LOW (Reference) Table 7. Serial Interface Timing Specifications Symbol Parameter Min Typ Max Unit fclk Serial data clock frequency MHz tsck Minimum serial period 7 tss Serial Data setup time tsh Serial Data hold time tln LE setup time tlew Minimum LE pulse width tles Minimum LE pulse spacing 6 LOW LOW LOW LOW LOW HIGH. LOW LOW LOW LOW HIGH LOW LOW LOW LOW HIGH LOW LOW LOW LOW HIGH LOW LOW LOW 4 LOW HIGH LOW LOW LOW LOW 8 HIGH LOW LOW LOW LOW LOW 6 HIGH HIGH HIGH HIGH HIGH HIGH. All other trademarks are the property of their respective owners. 8 BeRex Rev..

6 BVAB -4 MHz Parallel Control Mode The BVAB has six digital control inputs, D (LSB) to D (MSB), to select the desired attenuation state in parallel mode, as shown in Table 9. The parallel control interface is activated when P/S is set to low. There are two modes of parallel operation: direct parallel and latched parallel Direct Parallel Mode The LE pin must be kept LOW. The attenuation state is changed by the control voltage inputs (D to D) directly. This mode is ideal for manual control of the attenuator. In this mode the device will immediately react to any voltage changes to the parallel control pins [pins,, 4,,, 4]. Use direct parallel mode for the fastest settling time. Latched Parallel Mode The LE pin must be kept low when changing the control voltage inputs (D to D) to set the attenuation state. When the desired state is set, LE must be toggled LOW to transfer the 6-bit data to the bypass switches of the attenuator array, and then toggled low to latch the change into the device until the next desired attenuation change (see Figure and Table 9). Power-UP Interface The BVAB uses the PUP and PUP control voltage inputs to set the attenuation value to a known value at power-up before the initial control data word is provided in either serial or parallel mode. When the attenuator powers up with LE set to low, the state of PUP and PUP determines the power-up state of the device per the truth table shown in Table. The attenuator latches in the desired power-up state approximately ms after power-up. Table. PUP Truth Table Attenuation state P/S LE PUP PUP. db LOW LOW HIGH HIGH 6 db LOW LOW HIGH LOW 8 db LOW LOW LOW HIGH Reference Loss LOW LOW LOW LOW Defined by C.-C6 LOW HIGH Don t Care Don t Care Figure. Latched Parallel Mode Timing Diagram P/S X t PS t PH Parallel IN X D[:] PARALLEL CONTROL X t LEW LE Table 9. Truth Table for the Parallel Control Word D D D D D4 D P/S LE Attenuation State LOW LOW LOW LOW LOW LOW LOW HIGH HIGH LOW LOW LOW LOW LOW LOW HIGH LOW HIGH LOW LOW LOW LOW LOW HIGH LOW LOW HIGH LOW LOW LOW LOW HIGH LOW LOW LOW HIGH LOW LOW LOW HIGH LOW LOW LOW LOW HIGH LOW LOW HIGH LOW LOW LOW LOW LOW HIGH LOW HIGH HIGH HIGH HIGH HIGH HIGH HIGH LOW HIGH Reference Loss.dB db db 4dB 8dB 6dB.dB Table. Parallel Interface Timing Specifications Symbol Parameter Min Typ Max Unit tlew Minimum LE pulse width ns tph Data hold time from LE ns tps Data setup time to LE ns 6 All other trademarks are the property of their respective owners. 8 BeRex Rev..

7 Input Return Loss [db] Input Return Loss [db] Preliminary Datasheet Gain [db] Gain [db] BVAB -4 MHz Typical RF Performance Plot - BVAB EVK - PCB (Application Circuit:~4MHz) Typical Performance and VDD = V unless otherwise noted and Application Circuit refer to Table Table. Typical RF Performance(~4MHz) Table. ~4MHz RF Application Circuit Frequency Unit parameter MHz Gain db L C C C S db S db U_DSA C6 U_Amp C4 OIP dbm PdB dbm N.F db Gain data has PCB & Connectors insertion loss de-embedded OIP _ measured with two tones at an output of dbm per tone separated by MHz. Application Circuit Values Freq. RF Circuit MHz ~ 4MHz C6/C4 pf L( Chip Ind) nh Figure 6. Gain vs. Frequency over Temperature (Max Gain State) Figure 7. Gain vs. Frequency over Major Attenuation States -4 C,,,,,, 4, - db.db - db db 4dB 8dB 6dB.dB -,,,,,, 4, Figure 8. Input Return Loss vs. Frequency over Major Attenuation States Figure 9. Input Return Loss vs. Frequency over Temperature (Min,Max Gain State) db.db -4 db db 4dB 8dB 6dB.dB -,,,,,, 4, Gain -4 Gain Gain -,,,,,, 4, * Min Gain was measured in the state is set with attenuation.db. All other trademarks are the property of their respective owners. 8 BeRex 7 Rev..

8 PdB [dbm] NF [db] Preliminary Datasheet OIP [dbm] OIP [dbm] Output Return Loss [db] Output Return Loss [db] BVAB -4 MHz Typical RF Performance Plot - BVAB EVK - PCB (Application Circuit:~4MHz) Typical Performance and VDD = V unless otherwise noted and Application Circuit refer to Table Figure. Output Return Loss vs. Frequency over Major Attenuation States Figure. Output Return Loss vs. Frequency over Temperature (Min, Max Gain State) db.db -4 db db 4dB 8dB 6dB.dB -,,,,,, 4, - -4,,,,,, Gain -4 Gain -4 Gain Figure. OIP vs. Frequency Over Temperature (Max Gain State) * Min Gain was measured in the state is set with attenuation.db. Figure. OIP vs. Frequency Over Temperature (.db Atteuation State) -4 C,,,,,, 4, -4 C,,,,,, 4, Figure 4. PdB vs. Frequency Over Temperature (Max Gain State) Figure. Noise Figure vs. Frequency Over Temperature (Max Gain State) C,,,,,, 4, -4 C,,,,,, 4, All other trademarks are the property of their respective owners. 8 BeRex 8 Rev..

9 Preliminary Datasheet BVAB -4 MHz Typical RF Performance Plot - BVAB EVK - PCB (Application Circuit:~4MHz) Typical Performance and VDD = V unless otherwise noted and Application Circuit refer to Table Figure 6. Attenuation Error vs Frequency over Major Attenuation Steps Figure 7. Attenuation Error vs Attenuation Setting over Major Frequency (Max Gain State) db db -. db 4dB 8dB 6dB -.db -.,,,,,, 4, -. MHz 9MHz -.9GHz.4GHz.6GHz -. Figure 8..dB Step Attenuation vs Attenuation Setting over Major Frequency (Max Gain State) Figure 9. Attenuation Error at 9MHz vs Temperature MHz 9MHz.9GHz.4GHz.6GHz C Figure. Attenuation Error at.9ghz vs Temperature Figure. Attenuation Error at.4ghz vs Temperature - -4 C C All other trademarks are the property of their respective owners. 8 BeRex Rev..

10 BVAB -4 MHz Typical RF Performance Plot - BVAB EVK - PCB (Application Circuit:~4MHz) Typical Performance and VDD = V unless otherwise noted and Application Circuit refer to Table Figure. Attenuation Error at.6ghz vs Temperature Figure. Attenuation Error at.9ghz vs Temperature C C - -4 All other trademarks are the property of their respective owners. 8 BeRex Rev..

11 Input Return Loss [db] Input Return Loss [db] Preliminary Datasheet Gain [db] Gain [db] BVAB -4 MHz Typical RF Performance Plot - BVAB EVK - PCB (Application Circuit:~MHz) Typical Performance and VDD = V unless otherwise noted and Application Circuit refer to Table Table 4. Typical RF Performance(~MHz) Table. ~MHz IF Application Circuit Frequency Unit parameter 7 MHz Gain db L C C C S db S db U_DSA C6 U_Amp C4 OIP.. dbm PdB dbm N.F.4.6 db Gain data has PCB & Connectors insertion loss de-embedded OIP _ measured with two tones at an output of dbm per tone separated by MHz. Application Circuit Values Freq. IF Circuit MHz ~ MHz C6/C4 nf L( Chip Ind) 8nH Figure 4. Gain vs. Frequency over Temperature 4 Figure. Gain vs. Frequency over Major Attenuation States -4 C 4 - db.db db db - 4dB 8dB 6dB.dB - 4 Figure 6. Input Return Loss vs. Frequency over Major Attenuation States Figure 7. Input Return Loss vs. Frequency over Temperature (Min,Max Gain State) db.db db db - 4dB 8dB 6dB.dB -6 Gain Gain -4 Gain Gain -6 4 All other trademarks are the property of their respective owners. 8 BeRex Rev..

12 PdB [dbm] NF [db] Preliminary Datasheet OIP [dbm] OIP [dbm] Output Return Loss [db] Output Return Loss [db] BVAB -4 MHz Typical RF Performance Plot - BVAB EVK - PCB (Application Circuit:~MHz) Typical Performance and VDD = V unless otherwise noted and Application Circuit refer to Table Figure 8. Output Return Loss vs. Frequency over Major Attenuation States Figure 9. Output Return Loss vs. Frequency over Temperature (Min, Max Gain State) db.db db db - 4dB 8dB 6dB.dB -6 4 Gain Gain -4 Gain -4 Gain Gain -6 4 Figure. OIP vs. Frequency Over Temperature (Max Gain State) * Min Gain was measured in the state is set with attenuation.db. Figure. OIP vs. Frequency Over Temperature (.db Atteuation State) -4 C -4 C 4 4 Figure. PdB vs. Frequency Over Temperature (Max Gain State) Figure. Noise Figure vs. Frequency Over Temperature (Max Gain State) C -4 C 4 4 All other trademarks are the property of their respective owners. 8 BeRex Rev..

13 Preliminary Datasheet BVAB -4 MHz Typical RF Performance Plot - BVAB EVK - PCB (Application Circuit:~MHz) Typical Performance and VDD = V unless otherwise noted and Application Circuit refer to Table Figure 4. Attenuation Error vs Frequency over Major Attenuation Steps Figure. Attenuation Error vs Attenuation Setting over Major Frequency (Max Gain State) db db db 4dB -. 8dB 6dB.dB MHz 7MHz MHz MHz MHz 4MHz - Figure 6..dB Step Attenuation vs Attenuation Setting over Major Frequency. Figure 7. Attenuation Error at MHz vs Temperature MHz 7MHz MHz -. MHz MHz 4MHz C -. - Figure 8. Attenuation Error at 7MHz vs Temperature. Figure 9. Attenuation Error at MHz vs Temperature C C -. - All other trademarks are the property of their respective owners. 8 BeRex Rev..

14 BVAB -4 MHz Typical RF Performance Plot - BVAB EVK - PCB (Application Circuit:~MHz) Typical Performance and VDD = V unless otherwise noted and Application Circuit refer to Table Figure 4. Attenuation Error at MHz vs Temperature. Figure 4. Attenuation Error at MHz vs Temperature C C -. - Figure 4. Attenuation Error at 4MHz vs Temperature C -. - All other trademarks are the property of their respective owners. 8 BeRex 4 Rev..

15 BVAB -4 MHz Figure 4. Evaluation Board Schematic Figure 44. Evaluation Board PCB Table 6. Application Circuit Application Circuit Values Example Freq. IF Circuit ~MHz RF Circuit MHz ~ 4GHz C6/C4 nf pf L( Chip Ind) 8nH nh Table 7. Bill of Material - Evaluation Board No. Ref Des Part Qty Part Number REMARK C4,C6 CAP 4 pf J V IF circuit refer to table 6 C CAP 4 pf J V C TANTAL 6 UF 6V 4 C TANTAL 6.uF V L IND 68 nh IF circuit refer to table 6 6 C CAP 4 pf J V 7 R,R RES J K 8 R,R4,R,R7 RES 68 J ohm 9 J Receptacle connector U QFN4X4_4L_BVAB J,J SMA_END_LAUNCH Notice: Evaluation Board for Marketing Release was set to MHz to 4GHz application circuit (Refer to Table ) All other trademarks are the property of their respective owners. 8 BeRex Rev..

16 BVAB -4 MHz Figure 4. Application Circuit schematic* (Use only Serial mode) * notice. The serial mode PUP state of this Figure 4. is setting in Reference Loss (Refer to Table.) and each combinations of C.-C6 are shown in the Table 8. Truth Table. 6 All other trademarks are the property of their respective owners. 8 BeRex Rev..

17 BVAB -4 MHz Figure 46. Package Outline Dimension Figure 47. Evaluation Board PCB Layer Information Figure 48. Recommend Land Pattern COPPER :oz +.oz (plating), Top Layer EM8B ER: 4.6~4.8 P.P : ( ) TOTAL =.mm COPPER :oz (), Inner Layer MTC Er:4.6 CORE :.7mm COPPER :oz, Inner Layer FINISH TICKNESS :.T EM8B Er:4.6~4.8 P.P : ( ) TOTAL =.mm COPPER :oz +.oz (plating), Bottom Layer All other trademarks are the property of their respective owners. 8 BeRex 7 Rev..

18 BVAB -4 MHz Figure 49. Tape & Reel Figure. Package Marking Marking information: Packaging information: Tape Width mm Reel Size 7 Device Cavity Pitch 8mm Devices Per Reel K BVAB YYWWXX BVAB YY WW XX Device Name Year Work Week LOT Number Lead plating finish % Tin Matte finish MSL / ESD Rating ESD Rating: Value: Test: Standard: Class C Passes V Human Body Model(HBM) JEDEC Standard JESD-A4B MSL Rating: Standard: Level at +6 C convection reflow JEDEC Standard J-STD- C a u t i o n : ESD Sensitive Appropriate precautions in handling, packaging and testing devices must be observed. Proper ESD procedures should be followed when handling this device. NATO CAGE code: N 9 6 F All other trademarks are the property of their respective owners. 8 BeRex 8 Rev..