OBSOLETE REPLACE WITH PE43711 PE Product Specification. Product Description

Transcription

1 Product Description he PE6 is a HaRP -enhanced, high linearity, 6-bit RF Digital Step Attenuator (DSA) covering a. db attenuation range in. db steps. his Peregrine Ω RF DSA provides both a serial and parallel CMOS control interface. It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. Performance does not change with V DD due to on-board regulator. his next generation Peregrine DSA is available in a x mm lead QFN footprint. he PE6 is manufactured on Peregrine s UltraCMOS process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure. Functional Schematic Diagram Document No PE6 Ω RF Digital Attenuator 6-bit,. db, 9 khz -. GHz Features HaRP -enhanced UltraCMOS device Attenuation:. db steps to. db High inearity: ypical +8 dbm IIP Excellent low-frequency performance. V or. V Power Supply Voltage Fast switch settling time Programming Modes: Direct Parallel atched Parallel Serial High-attenuation power-up (PUP) CMOS Compatible No DC blocking capacitors required Packaged in a -lead xx.8 mm QFN Figure. Package ype -lead xx.8 mm QFN REPACE WIH PE7 Peregrine Semiconductor Corp. All rights reserved. Page of

2 PE6 able. Electrical + C, V DD =. V or. V Parameter est Conditions Frequency Min ypical Max Units Frequency Range 9 khz GHz Attenuation Range. db Step. db Step Error (db) Insertion oss 9 khz GHz..7 db Attenuation Error Bit Error (db) Peregrine Semiconductor Corp. All rights reserved. Page of db -. db Attenuation settings db -. db Attenuation settings db -. db Attenuation settings MHz 9MHz 8MHz MHz MHz MHz MHz Attenuation Setting (db).db State db State db State db State 8dB State 6dB State.dB State Frequency (MHz) 9 khz < GHz GHz GHz GHz GHz Figure. db Attenuation vs. Attenuation State PE6 Attenuation Attenuation (db) Attenuation Error (db) MHz 8 MHz MHz 8 MHz MHz MHz 9MHz 8MHz MHz MHz MHz MHz Document No Attenuation State Attenuation Setting (db) ±(. + )% +. + % -. - % Return oss 9 khz - GHz 8 db Relative Phase All States 9 khz - GHz deg PdB (note ) Input MHz - GHz dbm IIP wo tones at +8 dbm, MHz spacing MHz - GHz 8 dbm ypical Spurious Value MHz - dbm Video Feed hrough mvpp Switching ime % DC CR to % / 9% RF 6 ns RF rise/fall % / 9% RF ns Settling ime RF settled to within. db of final value RBW = MHz, Averaging ON µs Note. Please note Maximum Operating Pin ( Ω) of + dbm as shown in able Performance Plots Figure.. db Step Error vs. Frequency * * Monotonicity is held so long as Step-Error does not cross below -. Figure.. db Major State Bit Error db db db Figure 6.. db Attenuation Error vs. Frequency REPACE WIH PE7 UltraCMOS RFIC Solutions

3 PE6 Figure 7. Insertion oss vs. emperature Figure 8. Input Return oss vs. = + C Insertion oss (db) Return oss (db) Attenuation Error (db) C +C +8C Frequency (GHz) Figure 9. Output Return oss vs. = + C db.db db db db 8dB 6dB.dB Frequency (GHz) Figure. Attenuation Error vs. GHz -C +C +8C Attenuation Setting (db) Document No Input Return oss (db) Relative Phase Error (Deg) Input IP (dbm) db.db db db db 8dB 6dB.dB Frequency (GHz) Figure. Relative Phase vs. Frequency db.db db db db 8dB 6dB.dB Frequency (GHz) Figure. Input IP vs. Frequency db.db db db db 8dB 6dB.dB Frequency (MHz) REPACE WIH PE7 Peregrine Semiconductor Corp. All rights reserved. Page of

4 PE6 Figure. Pin Configuration (op View) able. Operating Ranges NC VDD P/S RF 6 Peregrine Semiconductor Corp. All rights reserved. Document No UltraCMOS RFIC Solutions Page of C. 7 C 8 C C Exposed Solder Pad 9 C8 C6 9 able. Pin Descriptions SI CK E RF Pin No. Pin Name Description Ground V DD Power supply pin P /S Serial/Parallel mode select Ground RF RF port 6 - Ground RF RF port Ground 6 E Serial interface atch Enable input 7 CK Serial interface Clock input 8 SI Serial interface Data input 9 C6 (D6) Parallel control bit, 6 db C8 (D) Parallel control bit, 8 db C (D) Parallel control bit, db C (D) Parallel control bit, db C (D) Parallel control bit, db C. (D) Parallel control bit,. db Paddle Ground for proper operation Note: Ground C., C, C, C, C8, C6 if not in use Exposed Solder Pad Connection he exposed solder pad on the bottom of the package must be grounded for proper device operation. Moisture Sensitivity evel he Moisture Sensitivity evel rating for the PE6 in the -lead x QFN package is MS. Switching Frequency he PE6 has a maximum khz switching rate. Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states. atch-up Avoidance Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. able. Absolute Maximum Ratings Symbol Parameter/Conditions Min Max Units V DD Power supply voltage V V I Voltage on any Digital input -..8 V S Storage temperature range -6 C Input power ( Ω) P IN 9 khz MHz Fig. dbm MHz GHz + dbm V ESD ESD voltage (HBM) V ESD voltage (Machine Model) V Note:. Human Body Model (HBM, MI_SD 88 Method.7) Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Figure. Maximum Power Handling Capability Pin dbm Parameter Min yp Max Units V DD Power Supply Voltage.. V V DD Power Supply Voltage.. V I DD Power Supply Current 7 μa Digital Input High.6. V P IN Input power ( Ω): 9 khz MHz MHz GHz Fig. + dbm dbm OP Operating temperature range - 8 C Digital Input ow V Digital Input eakage μa Note. Input leakage current per Control pin.e+.e+.e+.e+6.e+7.e+8.e+9 Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. REPACE WIH PE7 Hz

5 PE6 able. Control Voltage State ow High Document No Bias Condition to +. Vdc at µa (typ) +.6 to + Vdc at µa (typ) able 6. atch and Clock Specifications atch Enable X Shift Clock able 7. Parallel ruth able D6 H able 9. Serial Register Map MSB (last in) X Parallel Control Setting D D D D D Function Shift Register Clocked Contents of shift register transferred to attenuator core Q7 Q6 Q Q Q Q Q Q D7 D6 D D D D D D Attenuation Word Attenuation Setting RF-RF Reference I.. H. db H db H db H db H 8 db 6 db H H H H H H. db SB (first in) able 8. Serial Attenuation Word ruth able Attenuation Word D7 D6 D D D D D D (SB) Attenuation Setting RF-RF Reference I.. H. db H db H db H db H 8 db H 6 db H H H H H H. db Bits must be set to logic low Attenuation Word is derived directly from the attenuation value. For example, to program the. db state: Attenuation Word: Multiply by and convert to binary *. db Serial Input: REPACE WIH PE7 Peregrine Semiconductor Corp. All rights reserved. Page of

6 PE6 Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE6. he P /S bit provides this selection, with P /S=OW selecting the parallel interface and P /S=HIGH selecting the serial interface. Parallel Mode Interface he parallel interface consists of six CMOScompatible control lines that select the desired attenuation state, as shown in able 7. he parallel interface timing requirements are defined by Fig. 6 (Parallel Interface iming Diagram), able (Parallel Interface AC Characteristics), and switching speed (able ). For latched-parallel programming the atch Enable (E) should be held OW while changing attenuation state control values, then pulse E HIGH to OW (per Fig. 6) to latch new attenuation state into device. For direct parallel programming, the atch Enable (E) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial Interface he serial interface is a 8-bit serial-in, parallel-out shift register buffered by a transparent latch. he 8- bits make up the Attenuation Word that controls the DSA. Fig. illustrates a example timing diagram for programming a state. he serial-interface is controlled using three CMOScompatible signals: Serial-In (SI), Clock (CK), and atch Enable (E). he SI and CK inputs allow data to be serially entered into the shift register. Serial data is clocked in SB first. Peregrine Semiconductor Corp. All rights reserved. Document No UltraCMOS RFIC Solutions Page 6 of he shift register must be loaded while E is held OW to prevent the attenuator value from changing as data is entered. he E input should then be toggled HIGH and brought OW again, latching the new data into the DSA. Attenuation Word truth table is listed in able 8. A programming example of the serial register is illustrated in able 9. he serial timing diagram is illustrated in Fig.. It is required that all parallel pins be grounded when the DSA is used in serial mode. Power-up Control Settings he PE6 will always initialize to the maximum attenuation setting (. db) on power-up for both the serial and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. In direct-parallel mode, the DSA can be preset to any state within the. db range by pre-setting the parallel control pins prior to power-up. In this mode, there is a -µs delay between the time the DSA is powered-up to the time the desired state is set. During this powerup delay, the device attenuates to the maximum attenuation setting (. db) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). Dynamic operation between serial and parallel programming modes is possible. If the DSA powers up in serial mode (P /S = HIGH), all the parallel control inputs DI[6:] must be set to logic low. Prior to toggling to parallel mode, the DSA must be programmed serially to ensure D[7] is set to logic low. If the DSA powers up in either latched or directparallel mode, all parallel pins DI[6:] must be set to logic low prior to toggling to serial mode (P /S = HIGH), and held low until the DSA has been programmed serially to ensure bit D[7] is set to logic low. he sequencing is only required once on powerup. Once completed, the DSA may be toggled between serial and parallel programming modes at will. REPACE WIH PE7

7 PE6 Figure. Serial iming Diagram Bits can either be set to logic high or logic low D[] and D[7] must be set to logic low DI[6:] P/S SI CK E DO[6:] SISU DISU PSSU SIH Figure 6. atched-parallel/direct-parallel iming Diagram P/S PSSU PSIH VAID DI[6:] E DO[6:] D[] D[] D[] D[] D[] D[] D[6] D[7] Document No DIPD CK DISU EPW VAID PD DIH able. Serial Interface AC Characteristics V DD =. or. V, - C < A < 8 C, unless otherwise specified able. Parallel and Direct Interface AC Characteristics Symbol Parameter Min. Max. Unit V DD =. or. V, - C < A < 8 C, unless otherwise specified F CK Serial clock frequency - MHz CKH Serial clock HIGH time - ns Symbol Parameter Min Max Unit CK Serial clock OW time - ns atch Enable minimum pulse EPW width ast serial clock rising edge - ns ESU setup time to atch Enable - ns rising edge DISU Parallel data setup time - ns EPW atch Enable minimum pulse width - ns DIH Parallel data hold time - ns SISU Serial data setup time - ns PSSU Parallel/Serial setup time - ns SIH Serial data hold time - ns PSIH Parallel/Serial hold time - ns DISU Parallel data setup time - ns DIH Parallel data hold time - ns PD Digital register delay (internal) - ns ASU Address setup time - ns AH Address hold time - ns PSSU Parallel/Serial setup time - ns PSH Parallel/Serial hold time - ns PD Digital register delay (internal) - ns CKH DIPD ESU EPW DIH PSIH VAID PD Digital register delay (internal, - ns direct mode only) Peregrine Semiconductor Corp. All rights reserved. REPACE WIH PE7 Page 7 of

8 PE6 Evaluation Kit he Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE6 Digital Step Attenuator. Direct-Parallel Programming Procedure For automated direct-parallel programming, connect the test harness provided with the EVK from the parallel port of the PC to the J & Serial header pin and set the D-D6 SP switches to the MIDDE toggle position. Position the Parallel/Serial (P /S) select switch to the Parallel (or left) position. he evaluation software is written to operate the DSA in either Parallel or Serial-Addressable Mode. Ensure that the software is set to program in Direct-Parallel mode. Using the software, enable or disable each setting to the desired attenuation state. he software automatically programs the DSA each time an attenuation state is enabled or disabled. For manual direct-parallel programming, disconnect the test harness provided with the EVK from the J and Serial header pins. Position the Parallel/Serial (P /S) select switch to the Parallel (or left) position. he E pin on the Serial header must be tied to V DD. Switches D-D6 are SP switches which enable the user to manually program the parallel bits. When any input D-D6 is toggled UP, logic high is presented to the parallel input. When toggled DOWN, logic low is presented to the parallel input. Setting D-D6 to the MIDDE toggle position presents an OPEN, which forces an on-chip logic low. able 9 depicts the parallel programming truth table and Fig. 6 illustrates the parallel programming timing diagram. atched-parallel Programming Procedure For automated latched-parallel programming, the procedure is identical to the direct-parallel method. he user only must ensure that atched- Parallel is selected in the software. For manual latched-parallel programming, the procedure is identical to direct-parallel except now the E pin on the Serial header must be logic low Peregrine Semiconductor Corp. All rights reserved. Document No UltraCMOS RFIC Solutions Page 8 of Figure 7. Evaluation Board ayout Peregrine Specification - Note: Reference Figure 8 for Evaluation Board Schematic as the parallel bits are applied. he user must then pulse E from V to V DD and back to V to latch the programming word into the DSA. E must be logic low prior to programming the next word. Serial Programming Procedure Position the Parallel/Serial (P /S) select switch to the Serial (or right) position. he evaluation software is written to operate the DSA in either Parallel or Serial Mode. Ensure that the software is set to program in Serial mode. Using the software, enable or disable each setting to the desired attenuation state. he software automatically programs the DSA each time an attenuation state is enabled or disabled. REPACE WIH PE7

9 6 PE6 Figure 8. Evaluation Board Schematic Peregrine Specification -79 VDD P/S 6 8 J CON J6 SMA P/ S 6 8 D J HEADER C9.µF 7 9 D 7 9 De-embeding trace Z= Ohm VDD C pf D D D D D D D D6 Document No J7 SMA D C pf D C D pf C8 C pf pf D C6 D pf C pf C pf D C C7 pf J SMA D pf C pf D D Z= Ohm D6 D6 D VDD P/S CP VDD S/ P RF 6 D CP 7 D C XX DSA Ohm x MP 8 D C 9 D C U D C8 REPACE WIH PE7 D6 9 C6 SI CK E RF CK DAA E Z= Ohm SERIA HEADER COCK DAA E J SMA Peregrine Semiconductor Corp. All rights reserved. Page 9 of

10 PE6 Figure 9. Package Drawing Figure. Marking Specifications Peregrine Semiconductor Corp. All rights reserved. Document No UltraCMOS RFIC Solutions Page of 6 YYWW ZZZZZ 9- YYWW = Date Code ZZZZZ = ast five digits of ot Number REPACE WIH PE7

11 PE6 Figure. ape and Reel Drawing able. Ordering Information Order Code Part Marking Description Package Shipping Method PE6 MI 6 PE6G-QFN xmm-7a Green -lead xmm QFN Bulk or tape cut from reel PE6 MI-Z 6 PE6G-QFN xmm-c Green -lead xmm QFN units / &R EK6- PE6 -EK PE6-QFN xmm-ek Evaluation Kit / Box Document No ape Feed Direction A =. B =. K =. Device Orientation in ape Sales Contact and Information For sales and contact information please visit Advance Information: he product is in a formative or design stage. he datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification: he datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. : he datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). he information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user s own risk. op of Device No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. Peregrine s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. he Peregrine name, logo, and USi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. REPACE WIH PE7 Peregrine Semiconductor Corp. All rights reserved. Pin Page of