Product Specification PE42540

Transcription

1 PE4540 Product Description The PE4540 is a HaRP technology-enhanced absorptive SP4T RF switch developed on UltraCMOS process technology. This switch is designed specifically to support the requirements of the test equipment and ATE market. It comprises four symmetric RF ports and has very high isolation. An on-chip CMOS decode logic facilitates a two-pin low voltage CMOS control interface and an optional external V SS feature. High ESD tolerance and no blocking capacitor requirements make this the ultimate in integration and ruggedness. The PE4540 is manufactured on Peregrine s UltraCMOS process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. UltraCMOS SP4T RF Switch 0 Hz 8 GHz Features HaRP technology enhanced Fast settling time Eliminates gate and phase lag No drift in insertion loss and phase High linearity: 58 m IIP3 Low insertion loss: 3 6 GHz 8 GHz High isolation: 3 GHz, 6 GHz and 8 GHz Maximum power handling: 8 GHz High ESD tolerance of kv HBM on RFC and kv HBM on all other pins Figure. Functional Diagram RFC Figure. Package Type 3-lead 5 5 mm LGA ESD RF RF ESD ESD RF3 RF4 ESD ESD 50 CMOS Control/ Driver and ESD V DD V V Vss EXT Document No. DOC Page of

2 PE4540 Table. Electrical +5 C, V DD = 3.3V, V SS_EXT = 0V (Z S = Z L = 50Ω) Parameter Condition Min Typ Max Unit Operating frequency 0 Hz 8 GHz RFC RFX insertion loss 0 Hz 9 khz 00 MHz 6000 MHz 7500 MHz 8000 MHz RFX RFX isolation 0 Hz 9 khz 00 MHz 6000 MHz 7500 MHz 8000 MHz RFC RFX isolation 0 Hz 9 khz 00 MHz 6000 MHz 7500 MHz 8000 MHz Return loss (RFC to active port) 0 Hz 9 khz 00 MHz 6000 MHz 7500 MHz 8000 MHz Return loss (terminated port) 0 Hz 9 khz 00 MHz 6000 MHz 7500 MHz 8000 MHz Settling time 50% CTRL to 0.05 final value ( 40 to +85 C) rising edge 50% CTRL to 0.05 final value ( 40 to +85 C) falling edge Switching time (T SW ) 50% CTRL to 90% or 0% RF 5 8 μs P input compression point RFX RFC All : VSWR, 00% duty cycle 3 33 m Input IP MHz 58 m Input IP 8000 MHz 00 m Note : Maximum operating P IN (50Ω) is shown in Table 3. Please refer to Figure 4, Figure 5 and Figure 6 when operating the part at low frequency μs μs Page of Document No. DOC UltraCMOS RFIC Solutions

3 PE4540 Figure 3. Pin Configuration (Top View) Pin Dot Marking RF4 RF Pin # Pin Name Description, 3-6, 8, 9-, 4-7, 9-, 4-6, 8, Table. Pin Descriptions 9 VSS_EXT 0 V Exposed Pad Ground RF4 RF I/O 7 RF RF I/O 3 RFC RF common V 8 RF RF I/O 3 RF3 RF I/O 7 V DD Supply 3 RFC 9 V Switch control input, CMOS logic level V Switch control input, CMOS logic level VDD RF3 RF Table 3. Operating Ranges Parameter Min Typ Max Unit Supply voltage, V DD V Negative power supply voltage, V SS_EXT V Negative supply current, I ss 0 40 µa Power supply current, I DD V DD = 3.3V, V SS_EXT = 0V, Temp = +85 C Power supply current, I DD V DD = 3.6V, V SS_EXT used µa 50 µa Control voltage high (V, V)..5 V DD V Control voltage low (V, V) V Control current, I CTRL µa P IN thru path (50Ω, RF power in) 9 khz GHz GHz 8 GHz (85 C, V SS_EXT = 3.0V) (85 C, V SS_EXT = 0.0V) (85 C, V SS_EXT = 3.5V) Fig Max power into termination (50Ω) 9 khz 6 MHz,3 Fig MHz 8 GHz,3 0 Max power, hot switching (50Ω) 9 khz 6 MHz,3 Fig MHz 8 GHz,3 0 m m m Operating temperature range, T OP C Notes:. Applies only when external V SS power supply is used. Otherwise, V SS_EXT = % duty cycle ( 40 to +85 C, : VSWR). 3. Do not exceed 0 m. 3 V SS_EXT External V SS negative voltage Paddle Exposed solder pad: Ground for proper operation Notes:. Use V SS_EXT (pin 3, V SS_EXT = V DD) to bypass and disable internal negative voltage generator. Connect V SS_EXT (pin 3) to (V SS_EXT = 0V) to enable internal negative voltage generator.. All RF pins must be DC blocked with an external series capacitor or held at 0 VDC. Document No. DOC Page 3 of

4 PE4540 Table 4. Absolute Maximum Ratings Parameter Min Max Unit Maximum junction temperature +50 C Storage temperature range, T ST C Supply voltage, V DD V Control voltage (V, V) 4 V P IN thru path (50Ω, RF power in) 9 khz GHz GHz 8 GHz (85 C, V SS_EXT = 3.0V) (85 C, V SS_EXT = 0.0V) (85 C, V SS_EXT = 3.5V) Max power into termination (50Ω) 9 khz 6 MHz 6 MHz 8 GHz ESD voltage HBM RFC All pins Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Latch-Up Immunity Fig Fig ESD voltage CDM 3, all pins 450 V ESD voltage MM 4, all pins 00 V Notes:. Do not exceed 0 m.. Human body model (MIL-STD 883 Method 5). 3. Charged device model (JEDEC JESD C0). 4. Machine model (JEDEC JESD-A5-A). m m Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. V V Switching Frequency The PE4540 has a maximum 5 khz switching rate when the internal negative voltage generator is used (pin 3 = ). The rate at which the PE4540 can be switched is only limited to the switching time (Table ) if an external negative supply is provided at (pin 3 = V SS_EXT ). Optional External Vss For proper operation, the V SS_EXT pin must be grounded or tied to the Vss voltage specified in Table 3. When the V SS_EXT pin is grounded, FETs in the switch are biased with an internal voltage generator. For applications that require the lowest possible spur performance, V SS_EXT can be applied externally to bypass the internal negative voltage generator. Spurious Performance The typical spurious performance of the PE4540 is 44 m when V SS_EXT = 0V (pin 3 = ). If further improvement is desired, the internal negative voltage generator can be disabled by setting V SS_EXT = V DD. Table 5. Truth Table State V V RF on 0 0 RF on 0 RF3 on 0 RF4 on Moisture Sensitivity Level The moisture sensitivity level rating for the PE4540 in the 3-lead 5 5 mm LGA package is MSL3. Page 4 of Document No. DOC UltraCMOS RFIC Solutions

5 PE4540 Low Frequency Operation Table 6 shows the minimum and maximum voltage limits when operating the device under various V DD and V SS_EXT voltage conditions below 9 khz. Refer to Figures 4, 5 and 6 to determine the maximum operating power over the frequency range of the device. Table 6. Instantaneous RF Voltage Limits for Operation Below 9 khz V DD V SS_EXT Minimum Peak Voltage at RF Port Maximum Peak Voltage at RF Port Thermal Data Psi-JT ( JT ), junction top-of-package, is a thermal metric to estimate junction temperature of a device on the customer application PCB (JEDEC JESD5 ). JT = (T J T T )/P where JT = junction-to-top of package characterization parameter, C/W T J = die junction temperature, C T T = package temperature (top surface, in the center), C P = power dissipated by device, Watts Maximum Operating Power vs Frequency Figures 4, 5 and 6 show the power limit of the device will increase with frequency. As the frequency increases, the contours and maximum power limit will increase as shown in the curves. Table 7. Thermal Data for PE4540 JT Parameter Typ Unit 79 C/W 8 C/W JA, junction-to-ambient thermal resistance Document No. DOC Page 5 of

6 Input Power (m) Input Power (m) Input Power (m) PE4540 Figure 4. Maximum Operating Power vs Frequency (T ambient = +5 o C) VssEXT = -3.0V, VDD = +3.0V VssEXT = 0.0V, VDD +3.0V VssEXT= -3.5V, VDD=+3.5V ,000 0,000 00,000,000,000 Frequency (khz) Figure 5. Maximum Operating Power vs Frequency (T ambient = +50 o C) VssEXT = -3.0V, VDD = +3.0V VssEXT = 0.0V, VDD +3.0V VssEXT= -3.5V, VDD=+3.5V ,000 0,000 00,000,000,000 Frequency (khz) Figure 6. Maximum Operating Power vs Frequency (T ambient = +85 o C) VssEXT = -3.0V, VDD = +3.0V VssEXT = 0.0V, VDD +3.0V VssEXT= -3.5V, VDD=+3.5V ,000 0,000 00,000,000,000 Frequency (khz) Document No. DOC UltraCMOS RFIC Solutions Page 6 of

7 PE4540 Figure 7. Insertion Loss vs V DD (Temp = +5 C, V SS_EXT = 0) Figure 8. Insertion Loss vs Temp (V DD = 3.3V, V SS_EXT = 0) Figure 9. Insertion Loss (Temp = +5 C, V DD = 3.3V, V SS_EXT = 0) Figure 0. Isolation: RFX RFX vs V DD (Temp = +5 C, V SS_EXT = 0) Figure. Isolation: RFX RFX vs Temp (V DD = 3.3V, V SS_EXT = 0) Figure. Isolation: RFX RFC vs V DD (Temp = +5 C, V SS_EXT = 0) Document No. DOC Page 7 of

8 PE4540 Figure 3. Isolation: RFX RFC vs Temp (V DD = 3.3V, V SS_EXT = 0) Figure 4. Active Port Return Loss vs V DD (Temp = +5 C, V SS_EXT = 0) Figure 5. Active Port Return Loss vs Temp (V DD = 3.3V, V SS_EXT = 0) Figure 6. Terminated Port Return Loss vs V DD (Temp = +5 C, V SS_EXT = 0) Figure 7. Terminated Port Return Loss vs Temp (V DD = 3.3V, V SS_EXT = 0) Figure 8. RFC Port Return Loss vs V DD (Temp = +5 C, V SS_EXT = 0) Page 8 of Document No. DOC UltraCMOS RFIC Solutions

9 Linearity (m) [m] PE4540 Figure 9. RFC Port Return Loss vs Temp (V DD = 3.3V, V SS_EXT = 0) Figure 0. Linearity Performance (Temp = +5 C, V DD = 3.3V, V SS_EXT = 0) Nominal IIP3 [m] Nominal IIP [m] 0 0.0E E+3.0E+6 0.0E E+6.0E+9 0.0E+ [Hz].0E+0 Document No. DOC Page 9 of

10 V V 9 PE4540 Evaluation Kit The SP4T switch evaluation board was designed to ease customer evaluation of Peregrine s PE4540. The RF common port is connected through a 50Ω transmission line via the top SMA connector, J. RF, RF, RF3 and RF4 are connected through 50Ω transmission lines via SMA connectors J, J4, J3 and J5, respectively. A through 50Ω transmission is available via SMA connectors J6 and J7. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. Figure. Evaluation Board Layout PRT-8605 Figure. Evaluation Board Schematic J C4 pf 040 C pf 040 C pf 040 R R R R C3 pf 040 R R M 0603 M 0603 C6 0. µf 040 J8 PZC36DABN HEADER C5 0. µf 040 U PE4540 RFC 3 VDD 7 VSS 3 J RF RF J RF RF 7 J RF3 3 RF3 RF4 RF4 J J J DOC-397 Page 0 of Document No. DOC UltraCMOS RFIC Solutions

11 PE4540 Figure 3. Package Drawing B A C (X) DETAIL A 0.50 (x8) ± (x3) 0.34 (x3) 0.50 (x8) ± (x3) 0.0 C (X) Pin # Corner TOP VIEW 0.6±0.05 (x3) BOTTOM VIEW ±0.050 (x3) DETAIL B RECOMMENDED LAND PATTERN 0.0 C.0 MAX DOC C SEATING PLANE 0.70 SIDE VIEW 0.4 C 0.0 C A B 0.05 C ALL FEATURES CHAMFER DETAIL A DETAIL B Figure 4. Marking Specifications 4540 YYWW ZZZZZZZ YYWW = Date Code ZZZZZZZ = Assembly lot code (maximum seven characters) DOC Document No. DOC Page of

12 PE4540 Figure 5. Tape and Reel Drawing Tape Feed Direction Notes:. 0 sprocket hole pitch cumulative tolerance ±0.0. Camber not to exceed mm in 00 mm 3. Material: PS + C 4. Ao and Bo measured as indicated 5. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier 6. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole Ao = 5.5 ± 0.05 mm Bo = 5.5 ± 0.05 mm Ko =. ± 0.05 mm Pin Top of Device Device Orientation in Tape Table 8. Ordering Codes for PE4540 Order Code Description Package Shipping Method PE4540E-Z PE4540 SP4T RF switch Green 3-lead 5 5 mm LGA 00 units/t&r EK PE4540 Evaluation kit Evaluation kit /Box Sales Contact and Information For sales and contact information please visit Advance Inf ormat io n: The product i s i n a formati ve or desi gn stage. The datasheet contai ns desi gn target specifi cati ons for product devel opment. S peci fi cati ons and features may change i n any manner without noti ce. Prelimina ry S pecif ication: The datasheet contai ns preli mi nary data. A ddi ti onal data may be added at a l ater date. Peregri ne reserve s the ri ght to change specifi cati ons at any ti me without noti ce i n order to suppl y the best possi bl e product. P ro duct Spec ificat io n: The datasheet contai ns fi nal data. In the event Peregri ne deci des to change the speci fi cati ons, Peregri ne will notify customer s of the i ntended changes by i ssui ng a CN F (Customer Notifi cati on Form). The i nformati on i n thi s datasheet i s beli eved to be reli abl e. Howe ver, Peregri ne assume s no li abili ty for the use of thi s i nformati on. Use shall be enti rel y at the user s own ri sk. Page of No patent ri ghts or li cense s to any ci rcui ts descri bed i n thi s datasheet are i mpli ed or granted to any thi rd party. P eregri ne s products are not desi gned or i ntended for use i n devi ces or sy stems i ntended for surgi cal i mpl ant, or i n other appli cati ons i ntended to support or sustai n li fe, or i n any appli cati on i n whi ch the fail ure of the P eregri ne product coul d create a si tuati on i n whi ch personal i nj ury or death mi ght occur. Peregri ne assu mes no liability for damages, i ncl udi ng consequenti al or i nci dental damages, ari si ng out of the use of i ts products i n such appli cati ons. The Peregri ne name, l ogo, Ul tracm OS and U TS i are regi stered trademarks and HaRP, Mul ti S wi tch and DuNE are trademarks of P eregri ne S emi conductor Corp. P eregri ne products are protected under one or more of the foll owi ng U.S. Patents: Document No. DOC UltraCMOS RFIC Solutions