OBSOLETE PE4150. Product Specification. UltraCMOS Low Frequency Passive Mixer with Integrated LO Amplifier. Product Description

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1 Product Description The PE45 is an ultra-high linearity Quad MOSFET mixer with an integrated LO amplifier. The LO amplifier allows for LO drive levels of less than dbm to produce IIP values similar to a Quad MOSFET Array driven with a 5 dbm LO drive. The PE45 operates with differential signals at the RF and IF ports and the integrated LO buffer amplifier drives the mixer core. It can be used as an upconverter or a downconverter. The PE45 is manufactured on Peregrine s UltraCMOS process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure. Functional Diagram PE45 UltraCMOS Low Frequency Passive Mixer with Integrated LO Amplifier Features Ultra-high linearity Quad MOSFET array with integrated LO amplifier Ideal for mobile radio and Up/down conversion applications Low conversion loss High LO Isolation Packaged in small 4x4x.85mm -lead QFN Figure. Package Type 4x4x.85 mm -Lead QFN Document No Peregrine Semiconductor Corp. All rights reserved. Page of

2 Table. AC and DC Electrical Specifications (V DD =.9 to. V, Temperature = -4 to +85 C unless specified otherwise) Notes: Parameters Min Typ Max Units Current Drain (a function of frequency) 8 ma Off state leakage current µa RF Input Frequency VHF Band UHF Band UHF Band LO Frequency VHF Band UHF Band UHF Band The RF to IF Isolation is measured with an input frequency equal with IF.. IIP is measured with two tones at dbm, khz spacing IF Output Frequency LO Input Power - -6 dbm RF Input Power dbm Conversion Loss VHF, UHF, UHF 7, 8, and 9 rd Order Input Intercept (IIP) 5 dbm nd Order Input Intercept (IIP) VHF, UHF, UHF 7, 8 and 9 RF to IF Isolation VHF, UHF, UHF 7, 8 and 9 LO to IF Isolation db LO to RF Isolation 5 db db db dbm dbm db db Peregrine Semiconductor Corp. All rights reserved. Document No UltraCMOS RFIC Solutions Page of

3 Figure. Pin Configuration (Top View) Table. Pin Descriptions Pin # Symbol Description GND Ground INB Negative LO Input INA Positive LO Input 4 N/C No Connect 5 N/C No Connect 6 EN Enable Pin (active low) 7 V DD V DD 8 IF_P Positive IF port 9 GND Ground IF_M Negative IF port GND Ground RF_P Positive RF Input RF_M Negative LO Input 4 GND Ground 5 MixBias External Mixer Bias 6 N/C No Connect 7 N/C No Connect 8 V DD V DD 9 V DD V DD GND Ground Pad GND Exposed Ground Paddle The RF and IF pins are differential signals connected directly to the passive mixer. The LO input can be differential or single-ended. Table. Operating Ranges Symbol Parameters/Conditions Min Typ V DD T OP V DD Power Supply Voltage Max Units Table 4. Absolute Maximum Ratings Symbol Parameters/Conditions Min Max Units V DD Supply Voltage 4. V V DS I DS-DC I DS-AC Maximum DC plus peak AC across drain-source Maximum DC current across drain-source Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Latch-Up Avoidance ±. V 6 ma T ST Storage temperature range C Tj V ESD Maximum AC current across drain-source Operating Junction Temperature ESD Voltage (HBM, MIL_STD 88 Method 5.7) 6 ma p-p 5 C V Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Device Description The PE45 passive broadband Quad MOSFET array is designed for use in up-conversion and down-conversion applications for high performance systems such as mobile radios, cellular infrastructure equipment, and STB/CATV systems. Operating temperature range.9.. V C Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE45 in the 4x4x.85 mm -lead QFN package is MSL. The PE45 is an ideal mixer core for a wide range of mixer products, including module level solutions that incorporate baluns or other single-ended matching structures enabling three-port operation. The performance level of this passive mixer is made possible by the very high linearity afforded by Peregrine s UltraCMOS process. Document No Peregrine Semiconductor Corp. All rights reserved. Page of

4 Evaluation Kit The Mixer Evaluation Kit board was designed to ease customer evaluation of the PE45 Quad MOSFET Mixer with integrated LO amplifier. The RF and IF ports are connected through 5ohm transmission lines and :4 transmission line transformers to J5 and J7, respectively. The LO ports are connected through 5 Ω transmission lines to J4 and J6, respectively, and can support either a single-ended or differential signal drive. With a single-ended input, no termination is needed on the un-used port. The board is constructed of a two metal layer FR4 with a total thickness of.6". The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of.7", trace gaps of.8", dielectric thickness of.59" and metal thickness of.5". J provides an optional external DC bias that can be applied to the LO input, if there is DC component to the applied RF input. To use this option, transformers T and T must be carefully chosen to allow the use of a non-zero commonmode level. J9 can be used to enable or disable the part. The chip enable/en is active low. De-coupling capacitors are provided on the V DD traces. These capacitors should be placed as close to the DV DD pin as possible. Figure 4. Evaluation Board Layout Peregrine Specification --A Peregrine Semiconductor Corp. All rights reserved. Document No UltraCMOS RFIC Solutions Page 4 of

5 Figure 5. Evaluation Board Schematic Peregrine Specification -96 INB LO INA J HEADER J4 4 6 J6 SMASM J J8 J9 CON Z=5 Ohm Z=5 Ohm Mounting Holes on PCB MTG MTG MTG MTG4 LG LG LG R6 R4 R4 OHM R OHM C pf C.µF R7 C6 C7 5 Ohm R5 5 Ohm 5pF 5pF C µf Place C,C,C4,C5 close to D Pin. C4 pf C5.µF GND INB INA 4 N/C 5 N/C R8 GND 6 EN R R4 9 _ 7 _ J7 Z=5 Ohm 8 _ U MLPQ4X4 8 IF_P SMASM IF 7 N/C 9 GND 6 N/C MIXBIAS IF_N GND RF_N RF_P R GND T R5 R R ETK4-T R 5 4 R9 R OHM R OHM R5 R6 Z=5 Ohm Z=5 Ohm Z=5 Ohm R8 R J J J OUTB OUTA MIXBIAS T ETK4-T R7 OHM 6 4 (NOT USED - SEE NOTE 5) (NOT USED - SEE NOTE 5) (OPTIONAL) R R9 R Z=5 Ohm J5 SMASM RF Document No Peregrine Semiconductor Corp. All rights reserved. Page 5 of

6 Loss [db] IIP/IIP Loss [dbm] [db] Typical Performance Plots Figure 6. Conversion Loss vs Temperature deg C +5 deg C +85 deg C RF Frequency [] Figure 8. Linearity vs Temperature IIP/IIP Loss [dbm] [db] Loss [db] Figure 7. Conversion Loss vs LO Power & V DD (V DD = V; LO Pwr = - dbm) (Temp = 5 C) LO_Pw r = -dbm; =V LO_Pw r = -dbm; =V LO_Pw r = -6dBm;=V LO_Pw r = -5dBm; =V LO_Pw r = -dbm; =.9V LO_Pw r = -dbm; = RF Frequency [] Figure 9. Linearity vs LO Power (V DD = V; LO Pwr = - dbm) (V DD = V; Temp = +5 C) -4 deg C +85 deg C +5 deg C +5 deg C -4 deg C +85 deg C IIP w / LO_Pw r = -dbm IIP w / LO_Pw r = -dbm IIP w / LO_Pw r = -6dBm IIP w / LO_Pw r = -5dBm IIP w / LO_Pw r = -dbm IIP w / LO_Pw r = -dbm 8 IIP w / LO_Pw r = -6dBm IIP w / LO_Pw r = -5dBm RF Frequency [] RF Frequency [] Peregrine Semiconductor Corp. All rights reserved. Document No UltraCMOS RFIC Solutions Page 6 of

7 IIP/IIP Loss [db] [dbm] Isolation Loss [db] Typical Performance Plots Figure. Linearity vs V DD (Temp = +5 C; LO Pwr = - dbm) IIP w / =.9V IIP w / =.V IIP w / =.9V IIP w / =.9V IIP w / =.V IIP w / = RF Frequency [] Figure. Isolation vs LO Power LO-IF Iso w / LO_Pw r = -dbm LO-IF Iso w / LO_Pw r = -dbm LO-IF Iso w / LO_Pw r = -6dBm LO-IF Iso w / LO_Pw r = -5dBm RF-IF Iso w / LO_Pw r = -dbm RF-IF Iso w / LO_Pw r = -dbm RF-IF Iso w / LO_Pw r = -6dBm RF-IF Iso w / LO_Pw r = -5dBm Isolation Loss [db] Isolation Loss [db] [db] Figure. Isolation vs Temperature (V DD = V; LO Pwr = - dbm) LO-IF -4 degc LO-IF +85 deg C RF-IF +5 deg C LO-IF +5 deg C RF-IF -4 deg C RF-IF +85 deg C RF Frequency [] Figure. Isolation vs V DD (V DD = V; Temp = +5 C) (Temp = +5 deg C; LO Pwr = - dbm) LO-IF Iso w / =.9V LO-IF Iso w / =.V LO-IF Iso w / =.9V RF-IF Iso w / =.9V RF-IF Iso w / =.V RF-IF Iso w / =.9V RF Frequency [] RF Frequency [] Document No Peregrine Semiconductor Corp. All rights reserved. Page 7 of

8 Figure 4. Package Drawing 4x4x.85 mm -lead QFN Peregrine Semiconductor Corp. All rights reserved. Document No UltraCMOS RFIC Solutions Page 8 of

9 Figure 5. Tape and Reel Drawing Figure 6. Marking Specification 45 YYWW ZZZZZ Table 5. Ordering Information Tape Feed Direction Device Orientation in Tape YYWW = Date Code (Year, Work Week) ZZZZZ = Last five digits of PSC Lot Number Order Code Part Marking Description Package Shipping Method EK-45- PE45-EK PE45 QFN 4x4mm-EK Evaluation Kit / Box PE45MLAB 45 PE45 G - QFN 4x4mm Green -lead 4x4mm QFN 75 units PE45MLAB-Z 45 PE45 G QFN 4x4mm-C Green -lead 4x4mm QFN units / T&R Pin Top of Device Document No Peregrine Semiconductor Corp. All rights reserved. Page 9 of

10 Sales Offices The Americas Peregrine Semiconductor Corporation 98 Carroll Park Drive San Diego, CA 9 Tel: Fax: Europe Peregrine Semiconductor Europe Bâtiment Maine -5 rue des Quatre Vents F-98 Garches, France Tel: Fax : High-Reliability and Defense Products Americas San Diego, CA, USA Phone: Fax: Europe/Asia-Pacific Parc Cezanne 8 Avenue Archimède Parc de la Duranne 857 Aix-En-Provence Cedex France Tel: +() Fax: +() Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). Peregrine Semiconductor Corp. All rights reserved. Document No UltraCMOS RFIC Solutions Page of Peregrine Semiconductor, Asia Pacific (APAC) Shanghai, 4, P.R. China Tel: Fax: Peregrine Semiconductor, Korea #B-67, Kolon Tripolis, Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, South Korea Tel: Fax: Peregrine Semiconductor K.K., Japan 6 Yaesu Kyodo Building -5-9 Yaesu, Chuo-ku Tokyo 4-8 Japan Tel: Fax: For a list of representatives in your area, please refer to our Web site at: The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp.