Features. = +25 C, With Vdd = Vdd1 = +5V, Vss = -5V. Parameter Frequency (GHz) Min. Typ. Max. Units GHz GHz

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1 v Typical Applications The is ideal for: Features 1. LSB Steps to 3 Fiber Optics & Broadband Telecom Microwave Radio & VSAT Military Radios, Radar & ECM Space Applications Sensors Test & Measurement Equipment Functional Diagram TTL/CMOS Compatible, Serial Control Unique Asynchronous Mode Control Allows Immediate Attenuation Level Setting ±1. Typical Bit Error High Input IP3: +43 m 24 Lead 4x4mm SMT Package: 16mm2 General Description The is a broadband 5-bit GaAs IC digital attenuator in a low cost leadless surface mount package. Covering.1 to 3. GHz, the insertion loss is less than 5.5 typical. The attenuator bit values are 1. (LSB), 2, 4, 8, 16 for a total attenuation of 3. Attenuation accuracy is excellent at ±. typical step error with an IIP3 of +43 m. The control interface is CMOS/TTL compatible and accepts a three wire serial input. The features a user selectable power up state and a serial output port for cascading other Analog Devices serial controlled components. Electrical Specifications, T A = +25 C, With Vdd = Vdd1 = +5V, Vss = -5V Parameter Frequency (GHz) Min. Typ. Max. Units Insertion Loss GHz GHz GHz Attenuation Range.1-3. GHz 3 Return Loss (RF1 & RF2, All Atten. States).1-3. GHz 1 Attenuation Accuracy: (Referenced to Insertion Loss) Input Power for. Compression Input Third Order Intercept Point (Two-Tone Input Power= m Each Tone) Switching Characteristics States 16-3 States 16-3 States 16-3 States trise, tfall (1/9% RF) ton/toff (5% CTL to 1/9% RF) GHz.1-2. GHz GHz GHz GHz.5-3. GHz GHz.5-3. GHz.1-3. GHz ± (.5 + 5%) of Atten. Setting Max ± (.5 + 5%) of Atten. Setting Max ± (.6 + 8%) of Atten. Setting Max ± (.6 + 1%) of Atten. Setting Max Idd GHz ma Iss.1-3. GHz ma m m m m ns ns 1 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 916, Norwood, MA

2 Insertion Loss vs. Temperature INSERTION LOSS () Input Return Loss (Only Major States are Shown) RETURN LOSS () v C +85 C -4 C Normalized Attenuation (Only Major States are Shown) NORMALIZED ATTENUATION () Output Return Loss (Only Major States are Shown) RETURN LOSS () IL IL 3 IL 3 Bit Error vs. Attenuation State BIT ERROR () ATTENUATION STATE () Bit Error vs. Frequency (Only Major States are Shown) BIT ERROR () GHz 1 GHz 18 GHz 26.5GHz 33GHz IL 3 2

3 Relative Phase vs. Frequency (Only Major States are Shown) RELATIVE PHASE (deg) v IL 3 Step Attenuation vs. Attenuation State 18-3 GHz STEP ATTENUATION () Step Attenuation vs. Attenuation State.1-18 GHz STEP ATTENUATION () ATTENUATION STATE () 5 GHz 1 GHz 18 GHz Input Power for. Compression P.1 (m) ATTENUATION STATE () 26.5 GHz 3GHz C 25C 85C Input IP3 Over Major Attenuation States 6 Input IP3 vs. Temperature (Minimum Attenuation State) IP3 (m) 4 IP3 (m) I.L C 25C +85C 3

4 v Serial Control Interface The contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). The serial control interface is activated when S/A is kept high. The 5-bit serial word must be loaded MSB first as a 6-bit word with the first bit ignored. The positive-edge sensitive CLK and LE requires clean transitions. If mechanical switches are used, sufficient debouncing should be provided. When LE is high, 5-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data transition during output loading. For all modes of operations, the state will stay constant while LE is kept low. Serial Mode Truth Table P4 P3 Control Voltage Input P2 P1 P Attenuation State RF1 - RF2 High High High High High Reference I.L. High High High High Low High High High Low High High High Low High High High Low High High High Low High High High High Low Low Low Low Low 3 Any combination of the above states will provide an attenuation approximately equal to the sum of the bits selected. Parameter Min. serial period, t SCK Control set-up time, t CS Control hold-time, t CH LE setup-time, t LN Min. LE pulse width, t LEW Min LE pulse spacing, t LES Serial clock hold-time from LE, t CKN Hold Time, t PH. Latch Enable Minimum Width, t LEN Setup Time, t PS Typ. 1 ns 2 ns 2 ns 1 ns 1 ns 63 ns 1 ns ns 1 ns 2 ns Asynchronous Mode The can be switched to an asynchronous mode to change the attenuation state rapidly to one of four predefined states. The logic state of ASM1-ASM2 determines one of the four attenuation states in the asynchronous mode per truth table. The asynchronous mode works either directly or latched. To activate the direct-asynchronousmode, S/A needs to be at logic low and LE needs to be at logic high. In the direct-asynchronous-mode, any change in the logic state of ASM1-ASM2 directly affects the attenuation state. In the latched-asynchronous-mode, the attenuation state changes per the asynchronous mode truth table when S/A is at logic low and LE is pulsed per the timing diagram. The attenuation stays constant (latched) as long as LE stays low. In the asynchronous mode, the inputs SERIN and CLK do not affect the attenuation state. 4

5 v Timing Diagram (Latched Asynchronous Mode) Asynchronous Mode Truth Table ASM1 ASM2 Attenuation State RF1-RF2 High High Reference I.L. Power-Up States If LE is set to logic LOW at power-up, the logic state of PUP determines the power-up state of the part per PUP truth table. If the LE is set to logic HIGH at powerup, the logic state of ASM1-ASM2 determines the power-up state of the part per truth table for the asynchronous mode. The attenuator latches in the desired power-up state approximately 2 ms after power-up. Bias Voltages & Currents Vdd Vdd1 Vss ma 4.5 ma 5.5 ma High Low 3 Low High 2 Low Low 3 PUP Truth Table PUP High Low Control Voltage State Attenuation State Reference I.L. 3 Note: The logic state of ASM1-ASM2 determines the power-up state of the part per truth table for the asynchronous mode when LE is high at power-up. Bias Condition Low 1 µa High 2 to 1 µa 5

6 v Absolute Maximum Ratings RF Input Power (.1 to 3. GHz) Control Voltage (CLK, SERIN, LE, PUP, ASM1, ASM2, S/A) Vdd, Vdd1 Vss +27 m Vdd +.5V +7 Vdc -7 Vdc Channel Temperature 15 C Continuous Pdiss (T = 85 o C) (derate 6.9 mw/ o C above 85 o C) Thermal Resistance.453 W C/W Storage Temperature -65 to + 15 C Operating Temperature -4 to +85 C ESD Sensitivity (HBM) Outline Drawing Class 1A ELECTROSTATIC SENSITIVE DEVICE OBSERVE HANDLING PRECAUTIONS Package Information NOTES: 1. LEADFRAME MATERIAL: COPPER ALLOY 2. DIMENSIONS ARE IN INCHES [MILLIMETERS] 3. LEAD SPACING TOLERANCE IS NON-CUMULATIVE. 4. PAD BURR LENGTH SHALL BE.15mm MAXIMUM. PAD BURR HEIGHT SHALL BE.5mm MAXIMUM. 5. PACKAGE WARP SHALL NOT EXCEED.5mm. 6. ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND. 7. REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED LAND PATTERN. Part Number Package Body Material Lead Finish MSL Rating Package Marking [2] [1] 118A RoHS-compliant Low Stress Injection Molded Plastic 1% matte Sn MSL3 XXXX [1] Max peak reflow temperature of 26 C [2] 4-Digit lot number XXXX 6

7 v Pin Descriptions Pad Number Function Description Interface Schematic 1 2 SERIN LE See truth table, control voltage table and timing diagram. 3 Vss Negative Bias -5V 4, 15 GND 6-13, 16 N/C 5, 14 RF1, RF2 These pins and package bottom must be connected to RF/DC ground. The pins are not connected internally; however, all data shown herein was measured with these pins connected to RF/DC ground externally. These pins are DC coupled and matched to 5 Ohms. Blocking capacitors are required if RF line potential is not equal to V. 17 Vdd1 Positive Bias +5V 18 SEROUT Serial input data delayed by 6 clock cycles PUP ASM1 ASM2 S/A CLK See truth table, control voltage table and timing diagram. 2 Vdd Serial Controller Bias +5V 7

8 v Application Circuit 8

9 v Evaluation PCB J1 SERIN J5 VSS J6 RF1 S/R LE CLK C4 C1 NC NC VDD C3 U THRU CAL NC PUP SEROUT J3 C5 C6 C2 RF2 NC VDD1 J4 J2 List of Materials for Evaluation PCB EV1HMC118ALP4 [1] Item Description J1, J2 2.9 mm PC Mount RF Connector J3, J4, J6 DC Connector J5 C1-C3 C4-C6 U1 PCB [2] 2mm DC Header 1 pf Capacitor, 42 Pkg. 1 pf Capacitor, 42 Pkg. Digital Attenuator Evaluation Board [1] Reference this number when ordering complete evaluation PCB [2] Circuit Board Material: Rogers 435 The circuit board used in the application should use RF circuit design techniques. Signal lines should have 5 Ohm impedance while the package ground leads should be connected directly to the ground plane similar to that shown. A sufficient number of via holes should be used to connect the top and bottom ground planes. The evaluation circuit board shown is available from Analog Devices upon request. 9

10 v Notes: 1