INTERFACE ELECTRONICS FOR PERIPHERAL NERVE RECORDING AND SIGNAL PROCESSING KANOKWAN LIMNUSON. Submitted in partial fulfillment of the requirements

Transcription

1 INTERFACE ELECTRONICS FOR PERIPHERAL NERVE RECORDING AND SIGNAL PROCESSING By KANOKWAN LIMNUSON Submitted in partial fulfillment of the requirements For the degree of Master of Science Thesis Advisor: Dr. Pedram Mohseni Department of Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY August, 28

2 CASE WESTERN RESERVE UNIVERSITY SCHOOL OF GRADUATE STUDIES We hereby approve the thesis/dissertation of candidate for the degree *. (signed) (chair of the committee) (date) *We also certify that written approval has been obtained for any proprietary material contained therein.

3 i Table of Contents List of Tables... ii List of Figures...iii Abstract... vii CHAPTER CHAPTER Front-End Amplifier and Filter Circuit Design and Analysis Full-Wave Rectifier Circuit Design and Analysis Moving Average Filter Circuit Design and Analysis Amplification and DC Removal Stage Circuit Design and Analysis Comparator with Hysteresis System-Level Measurement Results CHAPTER Neural Recording Amplifier Results and Discussion Highpass Filter Results and Discussion Precision Full-Wave Rectifier Results and Discussion Lowpass Filter Results and Discussion Comparator with Hysteresis System-Level Measurement Results CHAPTER Conclusion Future Work BIBLIOGRAPHY... 6

4 ii List of Tables Table 2.1: Measured Gain and Input Noise for Various Settings of R Table 3.1: Summary of Device Sizes Table 3.2: Summary of Simulated and Measured Performance Characteristics Table 3.3: Summary of Performance Characteristics of Major Circuitry Table 4.1: Performance Characteristics of Discrete and Integrated Systems... 57

5 iii List of Figures Figure 1.1: Illustration of a laryngeal pacemaker device implanted in a patient (from [1]) Figure 1.2: The proposed system architecture for neural recording and signal processing.3 Figure 1.3: Schematic block diagram of the neural recording and signal processing system implemented in discrete fashion Figure 1.4: Schematic block diagram of the neural recording and signal processing system implemented in integrated fashion... 5 Figure 1.5: Microphotograph of the integrated neural recording and signal processing system fabricated using the AMI 1.5 µm 2P/2M n-well CMOS process Figure 2.1: The front-end instrumentation amplifier for recording Figure 2.2: A 4 th -order bandpass filter constructed from cascading two 2 nd -order highpass and lowpass filter stages Figure 2.3: The Sallen-Key filter architecture Figure 2.4: Simulated (red line) and measured (dashed blue line) frequency response of the front-end amplifier and filter with R = 47 Ω Figure 2.5: Simulated (red line) and measured (blue line) input-referred noise performance versus frequency Figure 2.6: Schematic block diagram of the high-input-impedance inverting full-wave rectifier Figure 2.7: Simulated (red line) and measured (blue circles) rectification characteristics of the precision full-wave rectifier Figure 2.8: Simulated full-wave rectifier output with a 1-kHz sinusoidal input signal with amplitude levels of 5 mv, 1 mv, and 5 mv in the top, middle, and bottom traces, respectively Figure 2.9: Measured full-wave rectifier output with a 1-kHz sinusoidal input signal with amplitude levels of 5 mv, 1 mv, and 5 mv in the top, middle, and bottom traces, respectively Figure 2.1: Simulated full-wave rectifier output with a 5-mV sinusoidal input signal with frequencies of 5 Hz, 1 khz, 3 khz, and 5 khz from top to bottom, respectively. 18

6 iv Figure 2.11: Measured full-wave rectifier output with a 5-mV sinusoidal input signal with frequencies of 5 Hz, 1 khz, 3 khz, and 5 khz from top to bottom, respectively. 18 Figure 2.12: A 3 rd -order linear-phase modified lowpass Paynter filter Figure 2.13: Simulated and measured frequency response of the 3 rd -order linear-phase Paynter filter with an averaging interval of ms Figure 2.14: Simulated and measured step response of the Paynter filter with an averaging interval of ms compared to that of an ideal moving average filter Figure 2.15: Schematic of an additional amplification and dc removal stage prior to comparison Figure 2.16: Measured frequency response of the amplification and dc removal stage Figure 2.17: Schematic diagram of the comparator with hysteresis Figure 2.18: Comparator output voltage (green line) for a 3-mV pp saw-tooth input signal (yellow line). The upper and lower threshold voltages are 8 mv and -55 mv, respectively Figure 2.19: (Top) Schematic block diagram of neural recording and analog signal processing system implemented in discrete fashion. (Bottom) A photograph of the assembled system on a custom-designed PCB Figure 2.2: Measured traces #1 (yellow), #2 (green), #3 (purple) and #4 (pink) are probed at the output of the bandpass filter, rectifier, RC highpass filter/buffer, and comparator blocks, respectively Figure 3.1: Schematic diagram of the front-end low-noise amplifier with capacitive feedback [1] Figure 3.2: Transistor-level circuit schematic of the OTA used in the front-end amplifier [24]. The current source I bias is equal to 6 µa Figure 3.3: Measured frequency response of the front-end recording amplifier Figure 3.4: Simulated (red line) and measured (blue line) input-referred noise voltage characteristics of the front-end amplifier Figure 3.5: Schematic block diagram of a 2 nd -order OTA-C highpass filter [25], [26] Figure 3.6: A PMOS-input symmetrical OTA with series-parallel current division [27].34

7 v Figure 3.7: Simulated (dashed line) and measured (solid line) frequency response of the 2 nd -order highpass filter Figure 3.8: Simulated (dashed line) and measured (solid line) frequency response of the 4 th -order highpass filter Figure 3.9: Block diagram of the non-inverting precision full-wave rectifier... 4 Figure 3.1: Schematic of the precision full-wave rectifier [29]... 4 Figure 3.11: Schematic of the 2-stage CMOS op-amp used in Fig. 3.1 [3] Figure 3.12: (a) Transistor-level implementation of a MOS resistor. (b) A wide-swing current mirror used to implement CMN in Fig Figure 3.13: Transistor-level circuit schematic of the precision full-wave rectifier with MOS resistors and wide-swing current mirrors Figure 3.14: Measured voltage transfer characteristics of the precision full-wave rectifier (circles) and the fitted piecewise-linear curve (solid line) Figure 3.15: Simulated full-wave rectifier output voltage for a 1-kHz sinusoidal input signal with amplitude of 2 mv (top), 5 mv (middle), and 1 mv (bottom) Figure 3.16: Measured full-wave rectifier output voltage (blue trace) for a 1-kHz sinusoidal input signal (red trace) with amplitude of 25 mv (top) and 5 mv (bottom). 45 Figure 3.17: Simulated full-wave rectifier output voltage for a 5-mV sinusoidal input signal at 5 Hz (top), 1 khz (middle), and 3 khz (bottom) Figure 3.18: Measured full-wave rectifier output voltage for a 5-mV sinusoidal input signal at 5 Hz, 1 khz, 3 khz, and 1 khz from top to bottom, respectively Figure 3.19: An OTA-C lowpass filter Figure 3.2: Measured gain (top) and phase (bottom) versus frequency for the lowpass filter Figure 3.21: Transistor-level circuit schematic of the comparator with built-in feedback for hysteresis Figure 3.22: Comparator output voltage (yellow line) for a 6-mV pp saw-tooth input signal (Green line). The upper and lower threshold voltages are 1 mv and -1 mv, respectively

8 vi Figure 3.23: (Top) Block diagram of neural recording and signal processing system implemented in ASIC version. (Bottom) A photograph of the ASIC on a custom-designed PCB Figure 3.24: Measured frequency response of the cascaded combination of the highpass filter and the 2 nd gain stage (Block 1). A gain of ~2 db at 1 khz is achieved Figure 3.25: Measured waveforms in Case I. Traces #2 (green) and #4 (pink) are probed at the nodes designated by numbers 2 and 4 in Fig Figure 3.26: An expanded view of Fig at the rising edge of the second trigger pulse. Traces #2 (green) and #4 (pink) are probed at the nodes designated by numbers 2 and 4 in Fig Figure 3.27: Measured waveforms in Case II. Traces #1 (yellow), #2 (green), #3 (purple) and #4 (pink) are probed at the nodes designated by numbers 1, 2, 3 and 4 in Fig Figure 3.28: An expanded view of Fig at the rising edge of the second trigger pulse. Traces #1 (yellow), #2 (green), #3 (purple) and #4 (pink) are probed at the nodes designated by numbers 1, 2, 3 and 4 in Fig

9 vii Interface Electronics for Peripheral Nerve Recording and Signal Processing Abstract by KANOKWAN LIMNUSON Interface electronics for peripheral nerve recording and analog signal processing is developed in this work as part of sensing mechanism for a laryngeal pacemaker to reanimate the paralyzed larynx in subjects with bilateral vocal fold paralysis. The electronic system has been designed to record neural activity from the phrenic nerve, condition the neural signal, and provide activity-dependent triggering for stimulator control. The system has been implemented in discrete fashion with commercial off-theshelf components as well as integrated on a single mm 2 chip fabricated using the AMI 1.5 µm 2P/2M n-well CMOS process. System architecture, circuit design and analysis, simulation results, and measurement data from benchtop experiments with prerecorded neural activity are presented and discussed.

10 1 CHAPTER 1 INTRODUCTION In this work, interface electronics for peripheral nerve recording and signal processing has been developed as part of a sensing mechanism for a laryngeal pacemaker device (see Fig. 1.1) in patients with bilateral vocal fold paralysis to reanimate a paralyzed muscle via electrical stimulation controlled by a trigger signal from the sensing circuitry. The hypothesis is that neural activity from the phrenic nerve is an optimal indicator for inspiratory drive, and could be used to control the laryngeal stimulation. Therefore, interface electronics have been developed to record neural activity from the phrenic nerve, process the recorded signal, and generate an activity-dependent trigger signal for stimulation control. Figure 1.1: Illustration of a laryngeal pacemaker device implanted in a patient (from [1]). Peripheral nerve recording and signal processing for closed-loop operation had been previously introduced in the literature, but the proposed system was not implantable [2], [3]. The peripheral nerve signal characteristics depend on the electrode type,

11 2 electrode contact distance, and signal distribution rate on the nerve. In general, peripheral nerve signals are on the order of a few µv, and have significant frequency components extended to a few khz. Given such low-level amplitudes, noise is typically a major concern in recording and, therefore, both device and ambient noise should be minimized. Since peripheral nerve recording is typically performed close to other functioning organs such as the muscles or heart, large-amplitude biopotential artifacts such as the electromyogram (EMG) or the electrocardiogram (EKG) as well as low-frequency motion artifacts are also major sources of concern. Good electrode design practices in addition to signal filtering can reduce to some extent the impact of these artifacts on recording. In addition, over the past few years, recording architectures such as quasitripole (QT) [4]-[6], true-tripole (TT) [6], and adaptive-tripole (AT) [7] have been utilized by researchers to alleviate the artifact problem with varying degrees of success. Quasi-tripole and true-tripole recording architectures are mainly used for EMG rejection. Adaptive-tripole architecture is derived from the TT architecture by adding complex circuitry to compensate for electrode imbalance and reduce time-dependent impedance variations caused by the growing tissue. The amplitude of the recorded electroneurogram (ENG) signal in TT architecture is about twice as high as that in a QT one, but it is more severely affected by electrode imbalance. For varying degrees of electrode imbalance, the AT architecture had similar or better performance than that of the QT one [8], but it requires complex circuitry as mentioned previously. As a result, given the tradeoff between performance and system complexity as previously reported in the literature, a QT front-end architecture (or bipolar configuration) is used in this work.

12 3 One important specification for a front-end neural recording amplifier is lownoise performance in order not to corrupt the low-amplitude neural signals recorded by the electrode. Many low-noise amplifiers have been previously reported for biomedical recording applications [9]-[14]. For the discrete-level implementation of the system in this work, we have used a commercial low-noise instrumentation amplifier as detailed in Chapter 2. For the integrated implementation, the low-noise amplifier in [1] has been selected due to its simplicity and low-noise performance as detailed in Chapter 3. As stated previously, the neural recording and processing system in this work aims to generate a trigger signal from bursts of neural activity on the phrenic nerve, which is theoretically a good indicator for breathing since it slightly precedes diaphragm activation. The majority of peripheral nerve signal power lies within 1-2 khz with a peak around 1.5 khz [3]. Consequently, we have proposed a recording and signal processing system as depicted in Fig. 1.2 in which the recorded signal is amplified by a low-noise front-end amplifier, bandpass filtered, and then rectified and lowpass filtered to obtain the envelope signal. The envelop waveform is further amplified, filtered to remove dc and low-frequency drift components, and then used to generate a trigger signal at the output of a comparator with hysteresis. Figure 1.2: The proposed system architecture for neural recording and signal processing.

13 4 Based on the architecture depicted in Fig. 1.2, we have developed the proposed system in both discrete and integrated fashions. Figure 1.3 shows the schematic block diagram of the system architecture in discrete implementation. The recorded signal is amplified using a low-noise instrumentation amplifier with adjustable gain, bandpass filtered from 3 Hz to 5 khz, full-wave rectified and lowpass filtered in an averaging block with an averaging interval of ms to obtain the envelope signal, amplified with a gain of 1 (2 db) and highpass filtered for dc removal, and finally compared in a comparator with hysteresis to generate the trigger signal at the output. The system is designed to operate with ±2.5-V power supply. Details of circuit design and prototype measurement results are provided in Chapter 2. Figure 1.3: Schematic block diagram of the neural recording and signal processing system implemented in discrete fashion. Figure 1.4 shows the schematic block diagram of the system architecture in integrated implementation. The recorded signal is amplified with a low-noise neural recording amplifier with a gain of 93 (~39 db) and bandpass filtered up to 6 khz. The amplified signal is then filtered with a 2 nd -order highpass filter and additionally amplified with a gain of 11 (~21 db), full-wave rectified using a current-mode rectifier, and lowpass filtered with an OTA-C filter. A simple RC highpass filter is then used for dc

14 5 removal, and an additional amplification stage with a variable gain is used before feeding the signal into a comparator with hysteresis to generate the trigger signal at the output. A prototype integrated circuit measuring 2.2 mm 2.2 mm has been fabricated using the AMI 1.5 µm double-poly double-metal n-well standard CMOS process, operating from ±1.5-V power supply. Figure 1.5 shows a microphotograph of the fabricated chip. Various circuit blocks are included on this integrated circuit as isolated test structures that can be externally connected on a custom-designed printed-circuit board (PCB) to implement the full system. Details of circuit design and prototype measurement results are provided in Chapter 3. Finally, Chapter 4 draws some conclusions from this work and outlines additional tasks as future works in this project. Figure 1.4: Schematic block diagram of the neural recording and signal processing system implemented in integrated fashion.

15 Figure 1.5: Microphotograph of the integrated neural recording and signal processing system fabricated using the AMI 1.5 µm 2P/2M n-well CMOS process. 6

16 7 CHAPTER 2 SYSTEM IMPLEMENTATION: DISCRETE In this chapter, the discrete-level implementation of the proposed neural recording and analog signal processing system is described. The design and analysis of various circuit blocks, including front-end amplifier and filter, rectifier, integrator, dc rejection and additional gain stages, and finally the comparator, are presented. Functionality of all circuit blocks is verified by HSPICE TM simulations and in measurements. Benchtop-level functionality of the entire system is also verified in tests with pre-recorded neural data. 2.1 Front-End Amplifier and Filter The main performance characteristics of the front-end amplifier are high input impedance, low noise, low dc gain, and high ac gain, all within the frequency range of interest. The filter should be able to remove any remaining dc frequency components and additionally filter out the noise. In this system implementation, the filter bandwidth is set from 3 Hz to 5 khz, which aims to partially reject any interfering EMG signals as well as the 6-Hz and other high-frequency ambient noise Circuit Design and Analysis As stated previously, the front-end recording amplifier is implemented using a low-noise precision instrumentation amplifier (LT1167 from Linear Technology), as shown in Fig From the technical datasheet [15], the input-referred noise voltage is 7.5 nv Hz at 1 khz with a variable gain of either 1 or 1,. The listed input impedance is typically 1, GΩ in a test condition specified by the manufacturer.

17 8 Figure 2.1: The front-end instrumentation amplifier for recording. According to [15], the adjustable gain of the instrumentation amplifier can be derived as follows: Gain = 1+ (2.1) Z g where Z g is the gain-setting impedance value from a capacitor (C) and a resister (R) connected in series. Therefore, the gain equation can be rewritten as: Gain = 1+ 1 R + jωc (2.2) or Gain = 1+ R 3 R 1 R + jωc (2.3) which is equivalent to a 1 st -order highpass filter with cutoff frequency of 1/(2πRC), dc gain of 1, and in-band ac gain equal to /R, with R adjustable by external switches. The bandpass filter in the system architecture is implemented as shown in Fig. 2.2 using a 2 nd -order Butterworth active highpass filter cascaded with its lowpass counterpart.

18 9 Active filters have been used in the system implementation, because of their advantages in realizing high input and low output impedances, which is quite useful when implementing cascaded networks. Moreover, Butterworth filters are selected, because of their maximally flat response with no passband ripple. Figure 2.2: A 4 th -order bandpass filter constructed from cascading two 2 nd -order highpass and lowpass filter stages. The filters are constructed using the Sallen-Key architecture [16], [17], shown in Fig. 2.3, which provides high input and low output impedances with a simple architecture. The general transfer function for a Sallen-Key filter is: Y5 + Y 6 Y1Y 2 V Y 6 = Vi 2 Y5 + Y 6 ( Y2 + Y3 )( Y1 + Y2 + Y4 ) Y 2 Y2Y4 Y6 (2.4)

19 1 Figure 2.3: The Sallen-Key filter architecture. To implement a lowpass filter, admittance values are substituted by: Y =, Y =, Y = jωc, Y = jωc, Y = and Y = R1 R2 R3 R4 and therefore the resulting transfer function for a 2 nd -order Sallen-Key lowpass filter will be: V ( jω) = V 1 K R R C C jω ( 1 K ) R C R C R C R R C C i ω (2.5) where K is equal to (1 + R 4 /R 3 ). By re-arranging Equation (2.5), we will have: V K ( jω) = ( 1 ) Vi ω R1 R2C1C 2 jω R1 C1 R2C1 R1C 2 K (2.6) For a 2 nd -order lowpass filter, the standard frequency domain equation is given as:

20 11 V K ( j2 π f ) = fclp QLP fclp 2 Vi f jf (2.7) By substitutingω = 2π f in Equation (2.6) and comparing the result with Equation (2.7), we obtain: f clp 1 = (2.8) 2π R R C C Q LP R R C C = R C + R C + R C K ( ) (2.9) where Q LP is the quality factor and f clp is the cutoff frequency for a lowpass filter. To implement a highpass filter, admittance values in Fig. 2.3 are substituted by: Y = jωc, Y = jωc, Y =, Y =, Y = and Y = R1 R2 R3 R4 and therefore the resulting transfer function for a 2 nd -order Sallen-Key highpass filter will be: V ( jω) = V i ω 2 ω K 1 1 ( 1 K ) 1 jω R C R C R C R R C C (2.1) where K is equal to (1 + R 4 /R 3 ). For a 2 nd -order highpass filter, the standard frequency domain equation is given as:

21 12 f K f V ( j chp 2 π f ) = 2 Vi f jf fchp QHP fchp 2 (2.11) By substitutingω = 2π f in Equation (2.1) and comparing the result with Equation (2.11), we obtain: f chp 1 = (2.12) 2π R R C C Q HP = R R C C ( ) R C + R C + R C K (2.13) where Q HP is the quality factor and f chp is the cutoff frequency for a highpass filter. In the front-end instrumentation amplifier, capacitor C is selected to be 47 µf and resistor R is equal to 47 Ω, 477 Ω, and 5,577 Ω for amplification gain factors of 1,, 1, and 1, respectively. These resistor and capacitor values result in an amplifier low cutoff frequency below 3 Hz. Therefore, the desired low cutoff frequency of 3 Hz is implemented by the Sallen-Key highpass filter. To implement a highpass filter in Fig. 2.2, we have used Equations (2.12) and (2.13) with design parameters Q =.77, f c = 3 Hz, and K = 1 to calculate the corresponding component values. As a result, R 1 = 15 kω, R 2 = 3.9 kω, C 1 = 15 nf and C 2 = 33 nf. To implement a lowpass filter in Fig. 2.2, we have used Equations (2.8) and (2.9) with design parameters Q =.77, f c = 5 khz, and K = 1 to calculate the

22 13 corresponding component values. As a result, R 3 = 1 kω, R 4 = 3 kω, R 5 = 91 kω, R 6 = 1 kω, C 3 = 33 nf, and C 4 = 1 nf. All operational amplifiers used in implementing the bandpass filter as well as other circuit blocks in the system are high-precision operational amplifiers (OPA277 from Texas Instruments). Based on the setting of resistor R, the calculated total gain for the front-end instrumentation amplifier and the bandpass filter is in the range of 1-1,, with the bandpass filter providing a gain of 1. Figure 2.4 shows the simulated (red line) and measured (dashed blue line) frequency response for the combination of the front-end amplifier and bandpass filtering stages. With resistor R in the instrumentation amplifier set to 47 Ω, the measured gain at 1 khz was found to be 8.56 db (1,666), which is very close to the simulated value. The low and high cutoff frequencies were measured to be 3 Hz and 6 khz, respectively Gain (db) Frequency (Hz) Figure 2.4: Simulated (red line) and measured (dashed blue line) frequency response of the front-end amplifier and filter with R = 47 Ω.

23 14 Figure 2.5 shows the simulated (red line) and measured (blue line) input-referred noise versus frequency for the front-end amplification and filtering stages. The total input-referred noise in the bandpass frequency range of 3 Hz to 6 khz was found to be.62 µv rms. A summary of measurement results based on various settings for resistor R in the instrumentation amplifier is listed in Table 2.1. At lower gain settings for the instrumentation amplifier, the contribution of the bandpass filter to input-referred noise will be higher, leading to an overall increase in voltage noise. Nonetheless, even at these lower gain settings, the input-referred noise performance is quite satisfactory. 1-7 Simulated Measured Input-referred noise (V/ Hz) Frequency (Hz) Figure 2.5: Simulated (red line) and measured (blue line) input-referred noise performance versus frequency. Table 2.1: Measured Gain and Input Noise for Various Settings of R R (Ω) 1 khz (db) Input Noise (µv rms ) ,

24 Full-Wave Rectifier Circuit Design and Analysis Signal rectification is performed using an inverting precision full-wave rectifier as shown in Fig. 2.6 [18]. The rectifier architecture comprises two OPA277 operational amplifiers, two 1N4148 diodes, and 5%-tolerance resistors (R 1 =R 2 =R 3 =1 kω and R 4 =2 kω). The input signal is connected to the non-inverting input terminals of the two opamps to obtain high input impedance. The rectifier also exhibits low output impedance suitable for avoiding loading effects in cascading. The maximum input voltage (.5 V) is limited by the saturation voltage of the op-amps (1.5 V for ±2.5-V supply [19]) and forward bias voltage of the two diodes (1 V [2]). Figure 2.6: Schematic block diagram of the high-input-impedance inverting full-wave rectifier. Figure 2.7 shows the simulated (red line) and measured (blue circles) rectification characteristics of this circuit block with small input signals in the range of -5 mv to +5 mv. The measured results closely match those from simulation.

25 Measured Simulated Output (V) Input (V) Figure 2.7: Simulated (red line) and measured (blue circles) rectification characteristics of the precision full-wave rectifier. Rectification errors occur with low-amplitude input signals, because the diodes do not fully turn on at the transitional points (when input voltage is V) primarily due to the input offset voltage of the first amplifier. Figures 2.8 and 2.9 depict the simulated and measured, respectively, rectifier output waveform with a 1-kHz sinusoidal input signal with different amplitudes. The top, middle, and bottom traces in each figure correspond to input amplitudes of 5 mv, 1 mv, and 5 mv, respectively. Rectification errors at the transitional points are quite noticeable with lower input amplitudes. Similarly, Figs. 2.1 and 2.11 show the simulated and measured, respectively, effects of op-amp s finite bandwidth on the output waveform. The input is a 5-mV sinusoidal signal at various frequencies. The four traces from top to bottom in each figure correspond to input frequencies of 5 Hz, 1 khz, 3 khz, and 5 khz, respectively. As can be seen, the outputs at higher frequencies exhibit more rectification errors. Nonetheless,

26 17 these errors should be insignificant given the frequency range of interest in this work. Moreover, since we will perform lowpass filtering after rectification to acquire the signal envelope information, small errors on rectified outputs at low input amplitudes can be easily tolerated..6 Output (V).4.2 Output (V) Output (V) Time (S) x Time (S) x Time (S) x 1-3 Figure 2.8: Simulated full-wave rectifier output with a 1-kHz sinusoidal input signal with amplitude levels of 5 mv, 1 mv, and 5 mv in the top, middle, and bottom traces, respectively. Output (V) Time (S) x 1-3 Output (V) Time (S) x 1-3 Output (V) Time (S) x 1-3 Figure 2.9: Measured full-wave rectifier output with a 1-kHz sinusoidal input signal with amplitude levels of 5 mv, 1 mv, and 5 mv in the top, middle, and bottom traces, respectively.

27 18 Output (V) Output (V) Output (V) Output (V) Time (S) x Time (S) x Time (S) x Time (S) x 1-4 Figure 2.1: Simulated full-wave rectifier output with a 5-mV sinusoidal input signal with frequencies of 5 Hz, 1 khz, 3 khz, and 5 khz from top to bottom, respectively. Output (V) Time (S) x 1-3 Output (V) Time (S) x 1-3 Output (V) Time (S) x 1-3 Output (V) Time (S) x 1-4 Figure 2.11: Measured full-wave rectifier output with a 5-mV sinusoidal input signal with frequencies of 5 Hz, 1 khz, 3 khz, and 5 khz from top to bottom, respectively. 2.3 Moving Average Filter Averaging the recorded neural activity is performed in order to obtain a simple neural waveform without distorting meaningful information such as activation and deactivation time and the average activity level [21]. A moving-time averaging method is

28 19 selected to implement this function. Compared to other averaging techniques such as integration or spike and pulse counting from a voltage-to-frequency converter, the moving-time averaging method is easy to implement and does not require additional processors [22]. A 3 rd -order linear-phase modified Paynter filter is used due to its superior characteristics such as the frequency response, step response, and phase response that are close to an ideal moving average function [23]. A modified Paynter filter is highly linear and has satisfactory accuracy in the averaging function Circuit Design and Analysis Figure 2.12 shows the circuit-level schematic of a 3 rd -order linear-phase modified lowpass Paynter filter. This filter gives 18-degree phase shift to the in-band input signal. The general transfer function for this filter is given as: 2 2 (1 + τ s ) (1 2 s)(1 1.2 s s ) H ( s) = (2.14) + τ + τ + τ and the averaging interval is equal to: T = 2π RC = 2πτ (2.15) The moving average filter in our system is constructed according to Fig with R=1 kω and C=27 nf, resulting in a moving average window of ~16.67 ms that is ideal for removing the 6-Hz ambient noise.

29 2 Figure 2.12: A 3 rd -order linear-phase modified lowpass Paynter filter. Figure 2.13 shows the simulated (dashed red line) and measured (blue line) frequency response of this filter. The measured notch frequency is slightly higher than 6 Hz due to tolerance in the values of passive components. The measured 3-dB cutoff frequency is 28 Hz. Figure 2.14 shows the simulated (red line) and measured (blue line) step response of this filter with a moving average interval of ms, superimposed on that of an ideal moving average filter (dashed black line), demonstrating that the implemented filter can accurately represent a moving average function in this system.

30 21 1 Simulated Measured Gain (db) Frequency (Hz) Figure 2.13: Simulated and measured frequency response of the 3 rd -order linear-phase Paynter filter with an averaging interval of ms Output (V) Simulated Ideal moving average Measured Time (S) Figure 2.14: Simulated and measured step response of the Paynter filter with an averaging interval of ms compared to that of an ideal moving average filter.

31 Amplification and DC Removal Stage Circuit Design and Analysis In order to condition the rectified and filtered signal just prior to comparison, an additional amplification and dc removal stage is utilized after lowpass filtering. As shown in Fig. 2.15, this stage comprises an amplifier with resistive feedback for additional amplification, an RC highpass filter for residual dc removal, and a buffer. The buffer is used for protecting the RC highpass filter from the loading effect of the following comparator. Resistors R 1 and R 2 are set to provide a gain of 1 (2 db). Resistor R 3 and Capacitor C are set to 1 MΩ and 2.2 µf, respectively, to implement a very low cutoff frequency. Figure 2.16 shows the measured frequency response in the range of 5 mhz to 1 Hz, exhibiting an in-band gain of 2 db and a cutoff frequency of ~6 mhz. Figure 2.15: Schematic of an additional amplification and dc removal stage prior to comparison.

32 Gain (db) Frequency (Hz) Figure 2.16: Measured frequency response of the amplification and dc removal stage. 2.5 Comparator with Hysteresis At the backend of the system, a comparator with hysteresis is used to reduce the probability of false triggers in the system when generating a trigger signal from bursts of neural activity that might be present on the phrenic nerve. A simple comparator as shown in Fig [18] is used with R 1, R 2, and R 3 equal to 1 kω, 3 kω, and 5.6 MΩ, respectively. As shown in Fig. 2.18, this results in measured upper and lower threshold voltages of 8 mv and -55 mv, respectively.

33 24 Figure 2.17: Schematic diagram of the comparator with hysteresis. Figure 2.18: Comparator output voltage (green line) for a 3-mV pp saw-tooth input signal (yellow line). The upper and lower threshold voltages are 8 mv and -55 mv, respectively. 2.6 System-Level Measurement Results For a system-level measurement, all the aforementioned circuit blocks were assembled and connected to each other on a custom-designed PCB, as shown in Fig The schematic block diagram of the entire system is also shown for clarity. The total gain

34 25 of the front-end amplification and filtering stages was set to 1, (8 db). Pre-recorded neural activity with maximum spike amplitude of ~6 µv pp was used as the input signal. The total system power consumption was measured to be ~3 mw from ±2.5-V power supply. Figure 2.2 shows the measured results. Each trace number corresponds to a numbered node within the system schematic block diagram. As can be seen, the system can correctly generate a trigger signal from the input neural activity. Figure 2.19: (Top) Schematic block diagram of neural recording and analog signal processing system implemented in discrete fashion. (Bottom) A photograph of the assembled system on a custom-designed PCB.

35 Figure 2.2: Measured traces #1 (yellow), #2 (green), #3 (purple) and #4 (pink) are probed at the output of the bandpass filter, rectifier, RC highpass filter/buffer, and comparator blocks, respectively. 26

36 27 CHAPTER 3 SYSTEM IMPLEMENTATION: INTEGRATED In this chapter, we present an integrated implementation for the neural recording and analog signal processing system that was previously introduced. Various circuit blocks in this system have been fabricated on a custom chip using the AMI 1.5 µm double-poly double-metal n-well CMOS process. This chapter includes details on the circuit design and analysis, simulation results, and measurement data for individual circuit blocks as well as for the entire system. 3.1 Neural Recording Amplifier Since extracellular neural activity has amplitude levels on the order of a few tens of µvs, it is necessary to amplify the weak neural signal before any further signal processing can be performed. Neural recording amplifiers in general have to be low noise and should provide adequate ac amplification and dc rejection at the electrode-electrolyte interface. The front-end neural recording amplifier used in this work is a low-noise CMOS amplifier based on the design in [1], as shown schematically in Fig This accoupled amplifier is capable of rejecting dc frequency components at the interface and amplifying the ac components in the mhz to khz frequency range. The mid-band ac gain is set by the ratio of C 1 /C 2. The low and high cutoff frequencies are equal to 1/(2 r inc C 2 ) and g m /A v C L, respectively, where r inc is the incremental resistance of one MOSbipolar pseudo-resistor device (M 1 -M 4 ), and A v is the closed-loop ac gain of the amplifier. C 1 and C 2 are set to 2 pf and 2 ff, respectively, for a mid-band ac gain of 4 db (1). Figure 3.2 shows the transistor-level circuit schematic of the operational

37 28 transconductance amplifier (OTA) used in the front-end neural recording circuitry. The current source I bias is equal to 6 µa. Device sizes are listed in Table 3.2. Figure 3.1: Schematic diagram of the front-end low-noise amplifier with capacitive feedback [1]. Figure 3.2: Transistor-level circuit schematic of the OTA used in the front-end amplifier [24]. The current source I bias is equal to 6 µa.

38 29 Table 3.1: Summary of Device Sizes Device W/L (µm / µm) M 1, M /4 M 3, M 4, M 5, M 6 4/23.2 M 7, M /36.8 M 9, M 1 36/12 M a, M b, M c, M d 4/ Results and Discussion Figure 3.3 shows the measured frequency response of the front-end recording amplifier. The measured mid-band ac gain of the amplifier was found to be db, in close agreement with the simulated value of 39.4 db. The implemented gain was slightly lower than the theoretical value of 4 db (set by capacitive feedback ratio), because parasitic capacitances from the pseudo-resistor devices would lead to an increase in the effective value of C 2. Due to very high incremental resistance of these devices, the measured low cutoff frequency was found to be ~3 mhz, which was significantly lower than the simulated value of ~1.3 Hz. This is primarily due to the fact that it is rather difficult to accurately model or simulate these MOS-bipolar pseudo-resistor devices. The measured high cutoff frequency of 6 khz, on the other hand, matched nicely with the simulated value. Figure 3.4 shows the simulated (red line) and measured (blue line) input-referred noise voltage characteristics of the front-end amplifier over the frequency range of 1 Hz to 1 khz. The measured input-referred noise over the frequency range of 1 Hz to 6 khz was found to be 2.38 µv rms. The measured total harmonic distortion was found to be.24% for a 9-mV pp sinusoidal input, leading to an input dynamic range of ~62.5 db. The

39 3 measured common-mode rejection ratio (CMRR) was 65 db at 1 Hz, which was much lower than the simulated value. This is primarily due to device mismatches in capacitors, pseudo-resistors, and input differential pair transistors. Table 3.2 summarizes the simulated and measured performance characteristics of the front-end amplifier Gain (db) Frequency (Hz) Figure 3.3: Measured frequency response of the front-end recording amplifier.

40 31 Input-referred noise (V/ Hz) Measured Simulated Frequency (Hz) Figure 3.4: Simulated (red line) and measured (blue line) input-referred noise voltage characteristics of the front-end amplifier. Table 3.2: Summary of Simulated and Measured Performance Characteristics Parameter Simulation Measurement Supply Voltage ±1.5 V ±1.5 V Supply Current 12 µa N/A AC Gain 39.4 db db Bandwidth 6 khz 6 khz Low Cutoff Frequency 1.35 Hz 3 mhz Input Noise (1 Hz - 6 khz) 2.62 µv rms 2.38 µv rms Input Noise (29 Hz - 6 khz) 2.13 µv rms 1.95 µv rms 9mV pp Input.272%.24% Dynamic Range (.24% THD) N/A 62.5 db 1 Hz 91 db 65 db Silicon Area N/A.285 mm 2

41 Highpass Filter A 2 nd -order Butterworth highpass filter has been implemented based on the design in [25], [26] with a standard transfer function as given by Equation (3.1) below: H( s) = s 2 s ω + s + ω 2 p 2 p Qp (3.1) where ω p and Q p are the pole frequency and quality factor of the highpass filter, respectively. Filter implementation using the OTA-C stages has been previously discussed in [25]. The basic architecture for an OTA-C highpass filter is shown in Fig. 3.5 where G mi (i = 1, 2, 3, 4) represents the transconductance of the i th OTA. The following equations describe the relationship between various design parameters in this architecture and the transfer function characteristics: G G ω = (3.2) 2 m1 m 2 p C1C 2 G m 3 1 G = (3.3) m 4 ω p G = m2 (3.4) Q p C 2 As a result, design parameters C 1 and C 2 are given as below: C G m1 1 = (3.5) Qpω p C G Q m2 p 2 = (3.6) ω p

42 33 Figure 3.5: Schematic block diagram of a 2 nd -order OTA-C highpass filter [25], [26]. The quality factor of a 2 nd -order Butterworth filter is Q p = In hand calculations, the desired highpass filter cutoff frequency f = ω 2π is taken as 3 Hz. For a practical implementation, on-chip capacitor values should be in the range of a few p p pf to occupy reasonable silicon area. Assuming C 1 equal to 7 pf in Equation (3.5), G m1 will be 9.3 ns. For simplicity in filter implementation, G m2 is chosen to be equal to G m1, leading to a value of 3.5 pf for C 2 based on Equation (3.6). Therefore, for implementing a low-cutoff-frequency active filter with on-chip capacitors, OTA stages with very low transconductance values (G m1,2 ) are needed. An OTA stage featuring a small transconductance value and an extended linear range is designed based on [27] by using the series-parallel current division technique. A transistor-level circuit schematic of the OTA is shown in Fig. 3.6, employing a PMOSinput symmetrical design with series-parallel current division without any loss in the linear range.

43 34 Figure 3.6: A PMOS-input symmetrical OTA with series-parallel current division [27]. For the NMOS current mirror, N number of unit transistors M 2 are placed in both series and parallel to achieve an effective output transconductance, G m, given by: G m gm 1 = (3.7) 2 N where g m1 is the transconductance of transistor M 1 in the differential input stage. The linear range V lin of the differential pair is defined as: V lin = 2nφ t 6 α (1 + i ) 3 2 f 1 2 3(1 + i f ) 1 (3.8) where n is the slope factor, φ t is the thermal voltage, α is the acceptable error in linearity range, and i f is the inversion level of M 1. For i f << 1, the transistor is in weak inversion, whereas for i f > 1 the transistor is in strong inversion [28]. To design a very low G m_ x transconductor with specified lin _ x V input linear range, the inversion level, i f1,

44 35 of the input pair is determined by Equation (3.8). For a given bias current (I bias ), the normalization current is given as: I I 1 W = = µ C nφ bias 2 1 s ox t 2i f 1 2 L1 (3.9) where µ is the effective mobility, C ox is the oxide capacitance per unit area, W 1 is the input pair transistor s width and L 1 is the input pair transistor s length. As a result, g m1, W1 L 1, and N can be calculated as below. The sizing of transistors M 2 and M 3 only influences leakage currents, matching, and noise. g m1 2i f Is = nφ.( 1+ i + 1) t f (3.1) W L 1 1 Is = (3.11) 1 2 µ Coxnφt 2 N g G m1 = (3.12) m _ x The maximum input signal level of an OTA-C highpass filter that is neither clipped nor slew-rate limited can be expressed as: Vs I s Vin = min,, 1, 2,..., max k = n H k ( jω) Y ( ) max k jω max (3.13) where V is the maximum input signal level, V s and I s are the maximum available in max voltage and current levels at the output determining the boundaries of the linear operation region, Hk ( jω) is the maximum value of the voltage transfer function defined as the max ratio of the phasor output voltage to the phasor input voltage of the k th OTA, and

45 36 Yk ( jω ) is the maximum value of the transfer admittance function defined as the ratio max of the phasor output current to the phasor input voltage of the k th OTA. In this work, a 4 th -order Butterworth highpass filter is also implemented as an isolated test structure using two cascaded 2 nd -order highpass filter stages with a standard transfer function as given by: 2 2 s s H( s) =. ω ω s + s + ω s + s + ω 2 p1 2 2 p2 2 p1 p2 Qp 1 Qp2 (3.14) where p1, p2 ω ω and Qp 1, p2 highpass filter, respectively. Q are the pole frequencies and quality factors of the 4 th -order Results and Discussion A 2 nd -order Butterworth highpass filter is implemented with G m1 = G m2 = 1 ns, G m3 = m4 G = 14 µs, C 1 = 7 pf, C 2 = 3.5 pf and Q =.77. These design values correspond to a cutoff frequency of ~32 Hz in hand calculations. All the transconductor stages are designed as outlined above in Equations (3.7) (3.12). For an OTA with G m = 1 ns and V lin = 18 mv linearity range for α = 5%, design parameters are found to be I bias = 2 na, i f = 52, W 1 = 8 µm, L 1 = 5 µm, and N = 8. For an OTA with G m = 14 µs and V lin =18 mv linearity range for α = 5%, design parameters are found to be I bias = 4 µa, i f = 59, W 1 = 56 µm, L 1 = 2 µm, and N = 1.

46 37 We simulated the Vs and I s parameters of the OTAs in Cadence based on the boundaries of the linear operation region with 5% linearity. For the OTA with ns, the G m = 1 V s and I s parameters are equal to 1.1 V and 1.75 na, respectively. For the OTA with G m = 14 µs, the V s and I s parameters are equal to.23 V and 2.43 na, respectively. Based on Equation (3.13), the maximum input signal amplitude for this highpass filter is calculated to be 18 mv. Figure 3.7 shows the simulated (dashed line) and measured (solid line) frequency response of this 2 nd -order highpass filter. The simulated and measured cutoff frequency is 32 Hz and 29 Hz, respectively. The simulated and measured in-band gain is -.89 db and -.68 db, respectively. The measured cutoff frequency is slightly lower than the simulated value due to potential variations in the value of capacitive components (C 1 and C 2 ) post fabrication. Gain (db) Simulated Measured Frequency (Hz) Figure 3.7: Simulated (dashed line) and measured (solid line) frequency response of the 2 nd -order highpass filter.

47 38 As stated previously, the 4 th -order Butterworth highpass filter is implemented by cascading two 2 nd -order highpass filter stages. The first 2 nd -order highpass filter stage has G m1 = m2 G = 1 ns, G m3 = G m4 = 14 µs, C 1 = 4 pf, C 2 = 7 pf and Q p1 = 1/.765. The second 2 nd -order highpass filter has G m1 = G m2 = 1 ns, G m3 = G m4 = 14 µs, C 1 = 9.8 pf, C 2 = 2.8 pf and Q p2 = 1/ These values correspond to a cutoff frequency of ~3 Hz in hand calculations. All the OTAs are designed as previously outlined above. Following the aforementioned procedure for calculating the maximum input signal amplitude, it is found to be 75 mv for this 4 th -order highpass filter. Figure 3.8 shows the simulated (dashed line) and measured (solid line) frequency response of the filter. The simulated and measured cutoff frequency is 272 Hz and 269 Hz, respectively. The simulated and measured in-band gain is db and db, respectively. The simulated and measured cutoff frequencies closely match each other, but are slightly lower than the hand-calculated value of 3 Hz. These small variations in the cutoff frequency of both the 2 nd -order and 4 th -order highpass filters are still quite acceptable for our neural recording application. The maximum input signal levels for both filters are adequately higher than the levels of amplified neural data. Therefore, the filters are not expected to contribute much to signal distortion.

48 Gain (db) Frequency (Hz) Measured Simulated Figure 3.8: Simulated (dashed line) and measured (solid line) frequency response of the 4 th -order highpass filter. 3.3 Precision Full-Wave Rectifier A non-inverting precision full-wave rectifier has been implemented based on the design in [29]. As shown schematically in Fig. 3.9, the input voltage V in is first converted into current, I in. Next, the current is applied to a precision current-based rectifier, and the resulting output current I O is then converted back to voltage, V out. Figure 3.1 shows the schematic block diagram of the non-inverting precision full-wave rectifier. Current rectification is performed by a CMOS precision rectifier consisting of two transistors (M n and M p ) and two current mirrors (CMN and CMP). The CMOS current rectifier is placed in the feedback loop of an op-amp with a large voltage gain. Assuming I in is the current that flows through resistor R 1, we then have:

49 4 I in V R in = (3.15) 1 Figure 3.9: Block diagram of the non-inverting precision full-wave rectifier. Figure 3.1: Schematic of the precision full-wave rectifier [29]. During the positive cycle, M n is turned on and M p is turned off. As a result, the drain current of M n is equal to I in. This current is then mirrored by CMP and produces the positive output voltage V out across resistor R 2. On the other hand, during the negative cycle, M p is turned on and M n is turned off. As a result, the drain current of M p is now equal to I in. This current is then mirrored first by CMN and then by CMP to produce the

50 41 positive output voltage V out across resistor R 2. Assuming the op-amp has a large voltage gain, and the current mirrors as well as the resistors are all ideal elements, the noninverting full-wave rectifier output voltage can be written as: V out = A V (3.16) in where A= R2 R1. In our design, A = 1. In the on-chip implementation, the op-amp is a two-stage CMOS op-amp as shown in Fig [3]. The two resistors R 1 and R 2 in Fig. 3.1 have been implemented as MOS resistors as shown in Fig. 3.12(a) where the resistor value R is given by: R = 1 W 2 µ Cox ( Vdd Vtp ) L (3.17) where the two matched transistors M x and M y operate in the saturation region. Therefore, the MOS resistors should provide good linearity at least within one threshold voltage from the power supply. The ideal current mirror CMN is replaced by a wide-swing current mirror [31] as shown in Fig. 3.12(b). The CMP current mirror is replaced by its PMOS counterpart. Figure 3.13 depicts the transistor-level circuit schematic of the precision full-wave rectifier incorporating MOS resistors and wide-swing current mirrors.

51 42 Figure 3.11: Schematic of the 2-stage CMOS op-amp used in Fig. 3.1 [3]. (a) (b) Figure 3.12: (a) Transistor-level implementation of a MOS resistor. (b) A wide-swing current mirror used to implement CMN in Fig. 3.1.

52 43 Figure 3.13: Transistor-level circuit schematic of the precision full-wave rectifier with MOS resistors and wide-swing current mirrors Results and Discussion Figure 3.14 shows the measured voltage transfer characteristics of the noninverting full-wave rectifier and the fitted piecewise-linear curve. The input (on X axis) and output (on Y axis) offset voltages were found to be ~6 mv and ~1 mv, respectively. The input offset voltage is mainly due to the offset in the op-amp, whereas the output offset voltage is primarily due to mismatches in transistors M 13 and M 14 as well as the offset in an internal buffer used for the measurement. The rectifier gain was measured to be 1.28 and for positive and negative cycles, respectively. Gain deviations from the designed value of 1 are mainly caused by device mismatches in implementing R 1 and R 2, device mismatches in the current mirrors,

53 44 and the finite output impedance of the current mirrors. During the negative cycle, rectifier gain is more adversely impacted than the gain in positive cycle, because the output current is mirrored by both CMN and CMP current mirrors. Output (V) Input (V) Figure 3.14: Measured voltage transfer characteristics of the precision full-wave rectifier (circles) and the fitted piecewise-linear curve (solid line). A dead zone in the full-wave rectifier output voltage typically occurs during the transition period between the positive and negative cycles when both transistors M n and M p are turned off. The rectifier output is ideally zero during this time period. A dead zone is mainly caused by the non-idealities of the op-amp such as its finite gain and bandwidth. Given the finite op-amp gain, a dead zone occurs when the input signal is so small that the op-amp output is not high enough to fully turn on transistors M n or M p. Figure 3.15 shows the simulated rectifier output for a 1-kHz sinusoidal input signal with amplitude of 2 mv, 5 mv, and 1 mv. Figure 3.16 shows the measured rectifier output for a 1-kHz sinusoidal input signal with amplitude of 25 mv and 5 mv.

54 45 Output (V) Time (S) x 1-3 Output (V) Output (V) Time (S) x Time (S) x 1-3 Figure 3.15: Simulated full-wave rectifier output voltage for a 1-kHz sinusoidal input signal with amplitude of 2 mv (top), 5 mv (middle), and 1 mv (bottom) Voltage (V) Time (S) x 1-3 Voltage (V) Time (S) x 1-3 Figure 3.16: Measured full-wave rectifier output voltage (blue trace) for a 1-kHz sinusoidal input signal (red trace) with amplitude of 25 mv (top) and 5 mv (bottom).

55 46 As can be seen, the amount of dead zone in the rectifier output voltage increases as the input signal amplitude decreases for a given input frequency. In order to ameliorate the dead zone effect, neural signals need to be sufficiently amplified prior to rectification. Dead zones can occur with frequency as well. Due to the op-amp finite bandwidth, op-amp gain decreases as the input frequency increases, leading once again to a dead zone effect. Figure 3.17 shows the simulated rectifier output for a 5-mV sinusoidal input signal at 5 Hz, 1 khz, and 3 khz. Figure 3.18 shows the measured rectifier output for a 5-mV sinusoidal input signal at 5 Hz, 1 khz, 3 khz, and 1 khz. As can be seen again, the amount of dead zone in the rectifier output voltage increases as the input frequency increases for given input amplitude. Given our frequency range of interest of 3 Hz to 6 khz (less than 1 khz) in this application, dead zone effects as a result of frequency are not expected to adversely affect system performance. Moreover, the measured output waveform does not exhibit any clipping with input signal amplitudes as high as 5 mv (1 mv pp ), which is sufficiently higher than the maximum amplitude of a typical neural signal after amplification.

56 47.6 Output (V) Time (S) x Output (V) Time (S) x Output (V) Time (S) x 1-3 Figure 3.17: Simulated full-wave rectifier output voltage for a 5-mV sinusoidal input signal at 5 Hz (top), 1 khz (middle), and 3 khz (bottom). Output (V) Output (V) Output (V) Output (V) Time (S) x Time (S) x Time (S) x Time (S) x 1-4 Figure 3.18: Measured full-wave rectifier output voltage for a 5-mV sinusoidal input signal at 5 Hz, 1 khz, 3 khz, and 1 khz from top to bottom, respectively.

57 Lowpass Filter An OTA-C lowpass filter as shown in Fig has been implemented as the envelope detection block in the analog signal processing system. The cutoff frequency of the lowpass filter is targeted at 1 Hz, which is also able to remove any possible 6-Hz noise and clean up the neural signal without too much signal attenuation. This target frequency is specified for a proof-of-concept study and is based on the assumption that the system input signal comprises bursts of neural activity that correlate with the breathing rhythm. This cutoff frequency can be changed later on when the characteristics of the phrenic nerve signal are studied and specified in greater details. The transfer function of a 1 st -order lowpass filter is given as: 1 H ( s) = C 1 + s g m (3.18) and the cutoff frequency f c is given as: f c gm = (3.19) 2πC Figure 3.19: An OTA-C lowpass filter.

58 Results and Discussion For the on-chip implementation, capacitor C is chosen to be 2 pf. According to Equation (3.19), the required g m will be 1.25 ns for a cutoff frequency of 1 Hz. The transconductor stage has been designed based on the same topology described in Section 3.2. Figure 3.2 shows the measured frequency response (gain and phase versus frequency) of the lowpass filter, exhibiting a cutoff frequency of ~8.75 Hz. The measured cutoff frequency is slightly lower than the simulated value of 1 Hz, most likely due to variations in the value of C post fabrication. Figure 3.2: Measured gain (top) and phase (bottom) versus frequency for the lowpass filter.

59 5 3.5 Comparator with Hysteresis A comparator with hysteresis using built-in feedback has been implemented based on the design in [32] as shown schematically in Fig The external reference voltage Vref is used to control the center point of the hysteresis loop. The current source I bias is set to 5 na. Figure 3.22 shows the measured comparator output voltage (yellow line) with a 1-Hz, 6-mV pp, 5% saw-tooth input signal (green line). The reference voltage Vref is set to zero. The measured positive and negative trip points were found to be 1 mv and -1 mv, respectively. This 2-mV hysteresis loop is designed for a proof-of-concept study and can be changed later on when the characteristics of the phrenic nerve signal are studied and specified in greater details. Figure 3.21: Transistor-level circuit schematic of the comparator with built-in feedback for hysteresis.

60 51 Figure 3.22: Comparator output voltage (yellow line) for a 6-mV pp saw-tooth input signal (Green line). The upper and lower threshold voltages are 1 mv and -1 mv, respectively. 3.6 System-Level Measurement Results Benchtop experiments were performed with three different input signals as described below to verify the system-level functionality of the integrated circuit. Frontend amplifier and analog processing system were externally connected to each other on a custom-designed PCB according to the system architecture shown in Fig The input was directly applied to the positive input terminal of the front-end amplifier with the negative input terminal held at ground. The 2 nd and 3 rd gain stages in Fig are implemented with standard two-stage CMOS op-amps in resistive feedback configuration. The 2 nd gain stage is designed to provide a gain of ~11 to further amplify the filtered neural signal and compensate for slight signal attenuation in the highpass

61 52 filter. Figure 3.24 shows the measured frequency response of the cascaded combination of the highpass filter and the 2 nd gain stage (Block 1), exhibiting a measured gain of ~1 (2 db) at 1 khz. Considering the front-end neural recording amplifier, this provides a total gain of ~932 (59.4 db) to the neural signal prior to rectification. A highpass RC filter was inserted between blocks 2 and 3 to remove any residual dc offsets in the signal. The precision full-wave rectifier and the lowpass filter perform envelope detection. The 3 rd gain stage has externally variable gain (via a resistor) to adjust the amplitude of the detected envelop prior to comparison. Figure 3.23: (Top) Block diagram of neural recording and signal processing system implemented in ASIC version. (Bottom) A photograph of the ASIC on a custom-designed PCB.

62 Gain (db) Frequency (Hz) Figure 3.24: Measured frequency response of the cascaded combination of the highpass filter and the 2 nd gain stage (Block 1). A gain of ~2 db at 1 khz is achieved. Case I: The input is pre-recorded neural activity with maximum spike amplitude of ~23 µv pp and signal-to-noise amplitude ratio (SNR) of ~4.4 db. The gain in the 3 rd gain stage is adjusted externally to get a trigger signal. Figures 3.25 and 3.26 show the measured waveforms that were probed at the nodes designated by numbers 2 and 4 in Fig Case II: The input is an amplitude-modulated, 1-kHz, sinusoidal signal with maximum amplitude of ~27 µv pp and SNR of ~6 db. The amplitude modulation profile is the temporal profile of surface EMG signal as described in [33].The gain in the 3 rd gain stage is adjusted externally to get a trigger signal. Figures 3.27 and 3.28 show the measured waveforms that were probed at the nodes designated by numbers 1, 2, 3, 4 in Fig Case I represents test results with pre-recorded neural activity from the peripheral nerves. The system works well with input signal amplitude of ~23 µv pp. Measured

63 54 latency in triggering is ~3 ms. Case II represents test results with an EMG-modulated sinusoidal input signal. The system works well with minimum input signal amplitude of ~27 µv pp and SNR of ~6 db. The gradual increase in the input signal amplitude in this case leads to a measured latency of ~21 ms in triggering. In addition to the noise already present in the input signals (neural background noise in Case I and intentionally added white noise from MATLAB TM in Case II), ambient 6-Hz noise can also be seen in all the measurements since they were conducted in open air outside a faraday shielding cage. The recording and signal processing system still operates satisfactorily with noisy signals and in noisy environments. Finally, Table 3.3 summarizes some of the performance characteristics of major circuitry in the implemented system. Table 3.3: Summary of Performance Characteristics of Major Circuitry Circuit Block Parameter Measured Value 1 khz db Front-End Amplifier Bandwidth 3 mhz to 6 khz Input-Referred Noise (29 Hz - 6 khz) 1.95 µv rms 2 nd -Order Highpass Filter Cutoff Frequency 29 Hz Full-Wave Rectifier Positive Cycle Gain Negative Cycle Gain 1.28 (2.1 db) (2.7 db) Lowpass Filter Cutoff Frequency 8.75 Hz Comparator Hysteresis Loop 2 mv

64 55 Figure 3.25: Measured waveforms in Case I. Traces #2 (green) and #4 (pink) are probed at the nodes designated by numbers 2 and 4 in Fig Figure 3.26: An expanded view of Fig at the rising edge of the second trigger pulse. Traces #2 (green) and #4 (pink) are probed at the nodes designated by numbers 2 and 4 in Fig

65 56 Figure 3.27: Measured waveforms in Case II. Traces #1 (yellow), #2 (green), #3 (purple) and #4 (pink) are probed at the nodes designated by numbers 1, 2, 3 and 4 in Fig Figure 3.28: An expanded view of Fig at the rising edge of the second trigger pulse. Traces #1 (yellow), #2 (green), #3 (purple) and #4 (pink) are probed at the nodes designated by numbers 1, 2, 3 and 4 in Fig