HARDWARE IMPLEMENTATION OF A STIMULUS ARTIFACT REJECTION ALGORITHM IN CLOSED-LOOP NEUROPROSTHESES CHIA-WEI SOONG

Transcription

1 HARDWARE IMPLEMENTATION OF A STIMULUS ARTIFACT REJECTION ALGORITHM IN CLOSED-LOOP NEUROPROSTHESES By CHIA-WEI SOONG Submitted in partial fulfillment of the requirements For the degree of Master of Science Thesis Advisor: Dr. Pedram Mohseni Department of Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY August, 2008

2 CASE WESTERN RESERVE UNIVERSITY SCHOOL OF GRADUATE STUDIES We hereby approve the thesis/dissertation of candidate for the degree *. (signed) (chair of the committee) (date) *We also certify that written approval has been obtained for any proprietary material contained therein.

3 Table of Contents 1. INTRODUCTION MOTIVATION BACKGROUND SA Rejection with Blanking Techniques SA Rejection with Subtraction Techniques RESEARCH OBJECTIVES SYSTEM DESIGN AND IMPLEMENTATION SYSTEM STRUCTURE DESIGN OF SAR BLOCK Basic Methodology SAR Block Architecture SAR Algorithm Parameters Averaging Method SYSTEM SIMULATION AND HARDWARE IMPLEMENTATION System Simulation of SAR Algorithm Hardware Implementation of SAR Algorithm Hardware Implementation of SAR System PROTOTYPE SYSTEM MEASUREMENT RESULTS OVERVIEW MEASUREMENT RESULTS CONCLUSION AND FUTURE WORK APPENDICES...39 APPENDIX A APPENDIX B BIBLIOGRAPHY...51 I

4 List of Tables Table 3.1: System Features and Measured Performance Characteristics...28 II

5 List of Figures Figure 1.1: The characteristics of a stimulus artifact (top) and a neural action potential (bottom)...2 Figure 2.1: (a) Traditional neural recording system with offline implementation of the SAR block in software. (b) The proposed system implementation with the SAR block placed after the first amplification stage....9 Figure 2.2: a) Input signal containing both a large-amplitude SA and a small neural spike. b) Estimated SA reference signal for subtraction. c) Recovered neural spike after SA subtraction Figure 2.3: Architecture of the proposed stimulus artifact rejection block Figure 2.4: Flow chart diagram of the proposed stimulus artifact rejection algorithm...13 Figure 2.5: Simplified illustration of sampling rate effect on the SAR algorithm performance. Sampling rates are set to 50 and 25 Hz in the top and bottom plots, respectively...15 Figure 2.6: System-level simulation results for the SAR block Figure 2.7: An expanded view of the simulated data in Fig Figure 2.8: Data flow chart and memory arrangement for the implementation of the SAR algorithm in the microcontroller...23 Figure 2.9: Schematic diagram of the hardware implementation for the SAR system...24 Figure 2.10: Schematic block diagram of the front-end neural recording circuitry, comprising an instrumentation amplifier and two cascaded filtering stages Figure 2.11: Simulated frequency response of the front-end neural recording circuitry Figure 2.12: Simulated ac response of the front-end neural recording circuitry Figure 3.1: Photograph of the custom-designed hardware implementation of the SAR block...27 Figure 3.2: Two different stimulus artifact waveforms used in generating the input signal for the SAR block...29 Figure 3.3: System measurement results with Test Signal 1. The top trace depicts the amplified signal fed to the SAR block that contains five stimulus artifacts III

6 (occurring at 10 Hz) and randomly positioned neural spikes. The middle trace depicts the estimated stimulus artifact template signal. The bottom trace shows the SAR block output after subtraction where neural spikes are recovered in between the artifacts...32 Figure 3.4: An expanded view of the three signals in Fig. 3.3, depicting on the bottom trace the two residual stimulus artifacts as well as a neural spike recovered from the decaying tail of the artifact...32 Figure 3.5: System measurement results with Test Signal 2. The top trace depicts the amplified signal fed to the SAR block that contains five stimulus artifacts (occurring at 10 Hz) and randomly positioned neural spikes. The middle trace depicts the estimated stimulus artifact template signal. The bottom trace shows the SAR block output after subtraction where neural spikes are recovered in between the artifacts...33 Figure 3.6: An expanded view of the three signals in Fig. 3.5, depicting on the bottom trace the two residual stimulus artifacts as well as a neural spike recovered from the decaying tail of the artifact...33 Figure 3.7: System measurement results with Test Signal 3. The top trace depicts the amplified signal fed to the SAR block that contains five stimulus artifacts (occurring at 10 Hz) and randomly positioned neural spikes. The middle trace depicts the estimated stimulus artifact template signal. The bottom trace shows the SAR block output after subtraction where neural spikes are recovered in between the artifacts...34 Figure 3.8: An expanded view of the three signals in Fig. 3.7, depicting on the bottom trace the two residual stimulus artifacts as well as a neural spike recovered shortly after the decaying tail of the artifact Figure 3.9: System measurement results with Test Signal 4. The top trace depicts the amplified signal fed to the SAR block that contains five stimulus artifacts (occurring at 2.5 Hz) and randomly occurring neural spikes. The middle trace depicts the estimated stimulus artifact template signal. The bottom trace shows the SAR block output after subtraction where neural spikes are recovered in between the artifacts...35 Figure 3.10: An expanded view of the three signals in Fig. 3.9, depicting on the bottom trace the two residual stimulus artifacts as well as a neural spike recovered from the decaying tail of the artifact Figure 3.11: Measured waveforms of the SAR block with Test Signal 1 as the input at 4 different timestamps during the operation. It takes ~9 seconds to reach steady state in plot D...36 IV

7 Figure 3.12: Stimulus artifact rejection results (with Test Signal 2) with a) the original SAR algorithm and b) the proposed SAR algorithm in hardware implementation using the pseudo-higher sampling rate concept. Additional suppression of ~5.5 db is achieved...37 V

8 Hardware Implementation of a Stimulus Artifact Rejection Algorithm in Closed-Loop Neuroprostheses Abstract by CHIA-WEI SOONG Due to their large amplitudes, stimulus artifacts can easily saturate neural recording amplifiers and hamper neural signal analysis during recording. In this work, we present a prototype stimulus artifact rejection (SAR) system, which is based on the template subtraction technique. A reference template signal of the stimulus artifact is generated by a pseudo-higher sampling rate averaging method, which is then subtracted from the original contaminated signal to reveal the desired neural activity. Measurement results from a proof-of-concept discrete implementation of the SAR system indicate that it is highly effective in reducing the amplitude of the stimulus artifacts. The system exhibits a stimulus artifact rejection of ~10-15 db at the rising and falling edges of the artifact (where it is changing rapidly with time) and successfully recovers microvolt-range neural action potentials from the slowly decaying tail of the artifact. Compared to the existing subtraction-based SAR algorithms, additional stimulus artifact suppression of ~5.5 db is achieved in this work. VI

9 1. Introduction 1.1 Motivation Recording electrical activity from the nervous system plays a significant role in today s neurophysiological studies. However, there are many technical challenges involved in neuroelectrical recording, in particular when recording from and stimulating the nervous system occur simultaneously and in close proximity in the same medium. One of the most common problems in such a scenario is the presence of stimulus artifacts (SA), interfering with extracellular neural recording. The extracellular electrodes record the electric field induced by the ionic channel currents rather than measuring the membrane potentials directly. Typically, the membrane potentials are in the millivolt range, whereas the extracellular signals at the electrode sites are in the microvolt range because the electric field decreases with distance away from the cell. Similarly, signal loss also occurs in the reverse path. Therefore, extracellular stimulation requires voltages at the electrode that are many orders of magnitude larger than those due to cellular electrical activity [1]. The stimulation-induced voltages can overwhelm the sensitive recording system, creating the stimulus artifact problem in closed-loop neuroprostheses. The SA waveform is characterized by a large spike followed by a slowly decaying tail whose amplitude, shape and time constant depend on the type of stimulator used, stimulating and recording electrode characteristics, and the filtering characteristics of the pre-amplification stages in the recording system [2]. Generally, the amplitude of SA is in the millivolt range. On the other hand, the amplitude of neural action potentials is in the microvolt range, so that there are many orders of magnitude difference between these two signals, as illustrated in Fig Due to the large amplitude of the SA, it either saturates 1

10 the recording preamplifiers, or contaminates the recorded neural activity. This problem is further exacerbated in high-frequency stimulation (HFS) applications such as deep brain stimulation, because more of the recording becomes hampered by the SA and the duration of the usable signal between successive stimulations becomes smaller. Therefore, it is important to eliminate or heavily suppress the stimulus artifacts in neural recording. Figure 1.1: The characteristics of a stimulus artifact (top) and a neural action potential (bottom). 2

11 1.2 Background Many techniques for eliminating or suppressing the stimulus artifacts in neural recording have been reported in the literature, and the methods applied are highly dependent on the particular biopotential being recorded and the conditions under which the recordings are taking place. Many of these techniques use the same fundamental principles for SA rejection or suppression. The two major categories of stimulus artifact rejection methods are blanking and subtraction techniques SA Rejection with Blanking Techniques Blanking techniques essentially disconnect the input terminal of the preamplifiers from the recording interface during the stimulation period. Stimulation-synchronized blanking of recording can be achieved by several methods. With a simple circuit design, the amplifier input can be switched to ground whenever the SA appears [3]-[5], or can be connected to the output of a sample-and-hold circuit to hold the data at a past value in the duration of stimulation [6], [7]. Another method is to use a grounding auto-zero switch to bleed off charge during the stimulation period, attempting to maintain some viable recording during the stimulation period [8]. In general, these techniques are relatively simple, effectively reject the large SA from the recorded signal, and are particularly useful in preventing amplifier saturation. Unfortunately, these techniques also eliminate the useful information during the stimulation period because no recording can be performed during the stimulation-synchronized blanking time, rendering blanking techniques quite ineffective in HFS applications. Analog filtering is also used to eliminate high-frequency 3

12 components of the SA [9]. However, there typically exists a significant overlap in frequency components between the desired neural signal and the interfering SA, reducing the efficacy of a simple filtering technique for SA suppression. Digitally-controlled implementation of the amplifier gain is suggested by [10] to suppress the SA. However, it is also pointed out by the authors that this method is not always sufficient to effectively remove artifacts. Amplifier slew rate limiting is a simple method that allows recording during the stimulation period and keeps the residual SA level lower than the background noise level, but can result in significant signal distortion as well [11]. Other methods based on the recording electrode configuration, such as quasi- and true-tripolar cuff electrode recording, have also been shown to reduce stimulation artifacts in peripheral nerve recordings [12], [13]. Since blanking techniques do not allow recording of useful neural activity during the stimulation period, many researchers have focused on subtraction techniques for stimulus artifact rejection, as described below SA Rejection with Subtraction Techniques The basic principle involved in most subtraction techniques requires subtracting a reference SA template signal from the contaminated recorded data. Generating an accurate reference waveform, faithfully representing the SA, is thus the main focus of research in subtraction techniques and can be accomplished by various methods. An uncontaminated SA as the reference signal can be obtained by simply recording from a stimulation isopotential line that does not contain biopotential activity [14], or by recording a subthreshold artifact where the stimulus intensity is reduced below the threshold for nerve excitation [15]. These techniques occasionally suffer from the residual SA due to not taking into 4

13 account the time-varying nature and the nonlinearity of the SA. In order to solve the problem of the SA nonlinearity, a method has been employed using Volterra series expansion to model the nonlinearity of the recorded signal, and has been shown to achieve a better SA suppression compared to other techniques [16], [17]. Digital averaging of multiple stimulation cycles also provides a representative SA template signal, based on the assumption that the shape of the SA remains the same over repeated stimulation periods [18], [19]. Some researchers have used a temporal average of a train of pulses to account for gradual changes in artifact shape, in conjunction with border extrapolation to alleviate reference contamination by stimulation-correlated activity [20]. Other researchers have modified a poor reference estimate using an adaptive filter or neural network in frequency or wavelet domain [21], [22]. In other works, a two-stage peak detection algorithm has been developed to identify, isolate, and remove the SA by setting high and low threshold levels. However, the limitation of this technique is that it is only applicable when the artifact signal and the biopotential are non-overlapping [23]. A multichannel real-time SA suppression technique is also proposed in which the SA is modeled by fitting polynomial or exponential curves to the recorded data. This method is shown to perform well on a wide range of artifact shapes [24]. Finally, a method of digitally replacing the artifact window with an average of the uncontaminated signal is also proposed [25]. In conclusion, blanking techniques in most cases can entirely reject the SA in real time and prevent amplifier saturation. However, they are incapable of retaining the useful information during the stimulation period, which is especially problematic in HFS applications. On the contrary, the primary advantage of most subtraction techniques is that they retain useful information during the stimulation period. Unfortunately, these 5

14 techniques by themselves do not prevent amplifier saturation and tend to be more complicated than blanking techniques, often requiring substantial digital signal processing (DSP). Therefore, the majority of the subtraction techniques are currently applied offline in software after the contaminated signal has already been recorded. 6

15 1.3 Research Objectives The overall objective in this research project is to design and implement a prototype stimulus artifact rejection (SAR) system in mixed-signal hardware that can suppress the SA amplitude as much as possible, not only recovering the useful biopotential information during stimulation periods but also functioning in real time to prevent preamplifier saturation. Moreover, the SAR system should be functional with a variety of biopotential recording systems without having to make significant hardware modifications. Specifically, the first goal of this project is to design the SAR block and implement the algorithm in hardware, as described in detail in Chapter 2. The second goal of this work is to integrate the SAR block with a simple neural recording front-end and test the prototype system performance with neural biopotentials. Details of the measurement results are described in Chapter 3. 7

16 2. System Design and Implementation 2.1 System Architecture Figure 2.1 illustrates the traditional as well as the proposed neural recording system architectures incorporating a SAR block. As shown in Fig. 2.1(a), for the traditional implementation, the recorded neural signal is amplified, filtered, sampled, digitized and stored. Once the data is fully recorded, it is further processed for offline analysis with a SAR algorithm implemented on a PC [19], [20]. The performance of the SAR algorithm in this case is limited by the sampling rate of the recorded data and the ADC number of resolution bits. Furthermore, the front-end amplification stages should be able to handle the large-amplitude SA without being saturated and the ADC needs to have adequate number of resolution bits to quantize large amplitude levels of the SA as well as small neural signal amplitudes. In order to alleviate the aforementioned drawbacks, the neural recording system shown in Fig. 2.1(b) is proposed in this work, where the SAR block is placed after the first amplification stage. In this manner, the stimulus artifact is suppressed before being fed to the second amplifier stage and the following ADC. Consequently, these stages only need to handle the desired neural activity superimposed on much smaller residual stimulus artifacts, not a combination of high-amplitude SA and low-amplitude neural signal. Moreover, the neural spikes can be amplified to the full dynamic range of the ADC, and recorded or transmitted through a wireless link to the PC for additional signal processing. The SAR block should be modular and not limited by various experimental system parameters (e.g., ADC sampling frequency or number of resolutions bits). The SAR block parameters can be selected independently to optimize SA rejection results. 8

17 Figure 2.1: (a) Traditional neural recording system with offline implementation of the SAR block in software. (b) The proposed system implementation with the SAR block placed after the first amplification stage. 2.2 Design of SAR block Basic Methodology As described in the previous chapter, the main problem with neural recording and stimulation within the same medium is the presence of large-amplitude stimulus artifacts that can easily hamper recording during the stimulation periods. Therefore, the proposed SAR algorithm is envisioned to execute during each stimulation period only, rather than throughout the whole recording period. In a system incorporating both stimulation and recording units, the occurrence time instances of stimulus pulses are typically controlled by a certain trigger signal, which can be used to indicate the start time for the execution of the SAR algorithm. Given the fact that the shape of the stimulus artifact does not change rapidly with time from one stimulus period to another, a reference signal for faithful representation of the SA can be estimated by sampling the input signal (i.e., signal containing both the SA and the randomly superimposed neural activity) during multiple stimulation cycles 9

18 followed by averaging. This basic SAR methodology is illustrated in Fig. 2.2 below, where the desired neural activity (trace C) is fully recovered after subtracting the estimated SA reference signal (trace B) from the contaminated input signal (trace A) that contains a large-amplitude SA as well as a small neural action potential at t = 80 ms. Figure 2.2: a) Input signal containing both a large-amplitude SA and a small neural spike. b) Estimated SA reference signal for subtraction. c) Recovered neural spike after SA subtraction. 10

19 2.2.2 SAR Block Architecture Figure 2.3 depicts the system architecture of the proposed SAR block, containing an ADC, memory, digital control unit, averaging circuitry, DAC, and an analog adder. The digital control unit generates the clock signals for the SAR block and is controlled by the stimulus trigger signal, as described previously. During each stimulation period when the trigger signal is high, the input signal is sampled and digitized by the ADC. The SA template signal is then generated by the averaging method and sent to the DAC. This signal is then subtracted from the input signal by the adder to obtain the output signal that contains the desired neural activity as well as some low-amplitude residual stimulus artifacts. Figure 2.3: Architecture of the proposed stimulus artifact rejection block. 11

20 Figure 2.4 shows the flow chart diagram of the proposed SAR algorithm. For each stimulation cycle, the SAR algorithm executes when the trigger signal to the control unit is high. The data analysis steps are listed as follows. 1. Read the input signal. 2. Convert the analog input signal to digital data for further processing. 3. Send the averaged data of previous cycle out by DAC while waiting for ADC. 4. Check operation of ADC. 5. If ADC work is done, then obtain a SA template signal by averaging. 6. Subtract the estimated template signal from the input signal by adder. 7. Obtain the output signal. In step 2, it is rather inefficient if the rest of the commands are executed only after the ADC conversion is completed. Therefore, in order to minimize the data processing time, the stored averaged data of the previous cycle is sent out by the DAC while waiting for the digitization of the current sampled data by the ADC. 12

21 Figure 2.4: Flow chart diagram of the proposed stimulus artifact rejection algorithm. 13

22 2.2.3 SAR Algorithm Parameters As shown in Fig. 2.3, there are several important parameters in the present work that can affect the performance of the SAR algorithm once implemented in hardware, namely, the sampling frequency and the number of resolution bits in the ADC and DAC as well as the size and word length of the memory. The stimulus artifact typically has a large slope during the rise and fall time instances, which makes the choice of the ADC sampling rate crucial to faithfully represent the SA during these transitional periods in each stimulation cycle. Figure 2.5 illustrates a simplified example of how the ADC sampling rate can affect the overall performance of the SAR algorithm. In this case, the input signal is a 1-Hz sinusoidal waveform plotted as the dashed green trace. The blue trace is the digitized signal and the red trace is the output signal obtained after subtracting the blue trace from the green trace. The sampling rates of the input signal in the top and bottom plots are 50 and 25 Hz, respectively. As clearly seen, the resulting output signal with a 25-Hz sampling rate exhibits residual amplitudes that are nearly three times larger than those obtained with higher sampling rate. It is therefore expected that higher sampling rates will lead to a more faithful representation of the stimulus artifact especially during the rapidly varying portions of the waveform and thus better overall performance in the SAR algorithm. From a practical point of view, however, higher sampling rates also lead into larger memory size and higher power consumption in hardware implementation of the system. 14

23 Figure 2.5: Simplified illustration of sampling rate effect on the SAR algorithm performance. Sampling rates are set to 50 and 25 Hz in the top and bottom plots, respectively. The number of bits in the ADC affects the resolution of the data. Higher number of resolution bits leads into more accurate estimation of the large-amplitude stimulus artifacts. Nevertheless, the number of bits cannot be arbitrarily large due to practical issues such as the resulting memory size in hardware implementation as well as on-chip realization in the future. The required memory size is affected by the sampling rate, the duration of the stimulus artifact, and the number of resolution bits. Obviously, larger memory size allows higher sampling rates, leading to better SA rejection results. Nonetheless, the area of the memory block can also be a major challenge in future system-on-a-chip (SOC) implementation of the proposed SAR algorithm. 15

24 2.2.4 Averaging Method As described in Chapter 1, there are various methods for producing the stimulus artifact template signal for subtraction purposes. The most common method is the conventional direct averaging, which is based on calculating the mean value of multiple cycles of data. Data recorded in each stimulation cycle for N consecutive cycles are stored in the memory, and the mean value is calculated according to Equation 2.1, where the superscript, k, identifies the k th data point in a cycle and the subscript, i, identifies the number of cycles. The averaged value obtained in this manner is more precise as compared to other methods. However, this method requires longer computational time to produce the output. X N k = 1 i+ X k i i= 1 Equation 2.1 N Weighting is the procedure to modulate the distributions in the sample data to approximate those of the population from which it is drawn. In this method, previously averaged data have higher weighting factors, while the incoming SA data are weighted lower. Finally, these weighted data are added together in order to generate an averaged signal for the next cycle as shown by Equation 2.2. The resulting weighting effect depends on the weighting factors, w, and the number of data points, N. Nevertheless, some data bits have to be thrown away to perform division in this method, thereby some meaningful data will be lost and it can lead to a high approximation error. X k i+ 1 w k N w k = ( X i ) + ( X i 1 ) Equation 2.2 N N Another method is based on comparison of each data point. As shown by Equation 2.3, if the input signal is higher than the previous averaged value, the averaged 16

25 value is increased by an increment M. On the other hand, if the input signal is lower than the previous averaged value, the latter is decreased by M. The value of M can be used to control the averaging speed. Increasing M results in a faster response time for the system at the expense of decreased resolution in the averaged value. Therefore, the value of M cannot be arbitrarily high when resolution is considered. In order to get more accurate estimates, one cannot achieve very fast response times using this method. X k X i 1 + M ; = k X i 1 M ; X > X k k k i i 1 i+ 1 k k X i < X i 1 Equation 2.3 For the implementation of the SAR algorithm in this work, the comparison method is selected for simplicity in programming. However, in order to improve its performance, a modified version of the method is developed and described later. 17

26 2.3 System Simulation and Hardware Implementation System Simulation of SAR Algorithm MATLAB TM is used to verify the system-level functionality of the proposed SAR algorithm with the comparison method for averaging as described previously. The input data used for system simulation was previously recorded from a marine mollusk Aplysia californica with a sampling frequency of 20 khz after 10-Hz current-based stimulation of the nervous system. A typical raw stimulus artifact and neural spike in the recorded data had amplitude levels of ~4 mv pp and ~150 µv pp, respectively. A 15-s portion of this raw input data is shown as the top trace in Fig. 2.6 (trace A). Prior to being fed to the SAR algorithm for processing, the data were amplified in MATLAB TM by a gain of 60 db, representing a typical gain for Amplifier 1 in Fig A 10-Hz trigger signal was also generated as shown in the second trace in Fig. 2.6 (trace B). System parameters such as the ADC number of resolution bits and sampling frequency were set to 8 and 20 khz, respectively. The memory length was selected to be 360 samples (8 bits), given stimulus artifact duration of ~18 ms. As shown in the third trace of Fig. 2.6 (trace C), the SA template signal achieved steady-state status after ~10 s, and the output signal (trace D) was then obtained via subtraction of the template. Figure 2.7 shows a 400-ms expanded portion of the simulated data, revealing that the microvolt-range neural spikes could indeed be recovered in between successive stimulus artifacts. The amplitude of the residual stimulus artifacts were ~50 mv pp (50 µv pp when referred to the input, representing a suppression of more than 38 db). With 6 and 10 bits of resolution in the ADC, the resulting input-referred residual stimulus artifacts were found to be 200 µv pp and <10 µv pp. Although the 18

27 residual stimulus artifacts are practically negligible with a 10-bit ADC, an 8-bit ADC is selected in the hardware implementation of the system as will be described later. The MATLAB TM code for the system-level simulation is enclosed in Appendix A. Figure 2.6: System-level simulation results for the SAR block. 19

28 Figure 2.7: An expanded view of the simulated data in Fig Hardware Implementation of SAR Algorithm Compared to the MATLAB TM simulation running on a PC, the computational resources in an implantable microcontroller are much more limited. Therefore, one would expect to have residual stimulus artifact peaks with higher amplitudes compared to the results obtained in MATLAB TM simulation. The implementation of the SAR algorithm in a microcontroller provides for real-time signal processing. However, it is necessary to modify the algorithm in order to obtain satisfactory performance given the limited computational resources available in a closed-loop implantable device. In this work, the SAR algorithm is implemented using Assembly language in an 8-bit microcontroller with 10-bit built-in ADC (PIC16F688 from Microchip) that has 12 I/O pins, adequate for the operation of the algorithm. There are bit registers 20

29 available in the memory block. The maximum clock frequency of this microcontroller is 20 MHz (i.e., 5 million instructions per second). The clock frequency, F osc, is selected as 8 MHz and the ADC clock is set by F osc /16. As previously discussed in Section 2.2.3, the sampling rate is a crucial factor in generating the SA template signal in order to suppress the residual peaks especially at the rise and fall time instances of the artifact where it has a large slope. As a result, a pseudo-higher sampling rate method is employed in hardware implementation in order to increase the effective sampling rate without the requirement for a larger-size memory. In this technique, the mean value of two consecutive estimated points is also calculated and sent out by the DAC. As a result, the effective sampling rate is twice as higher. Nonetheless, the memory size needed actually remains the same. There are three memory banks in this microcontroller and a total of 256 bytes are available as general-purpose registers. In this implementation of the SAR algorithm, 250 bytes are used in the memory with 6 bytes unused and available for other tasks. Each register is accessed through file-select register (FSR). The indirect file (INDF) buffer is not a physical register in the microcontroller. Any instruction using the INDF register actually accesses the data pointed to by the FSR. Figure 2.8 shows the data flow chart and memory arrangement for implementation of the SAR algorithm in the microcontroller. The Assembly code programmed in the PIC16F688 microcontroller is enclosed in Appendix B. (a) In the current cycle, FSR points to the first address while the first incoming data, 1 X i, is being sampled and converted to a digital number by the ADC. Also, 21

30 1 X i 1 is loaded to Buffer 1 for calculating the middle estimated point. (b) Next, FSR is moved to the second register and loads 2 X i 1 for calculating the mean value of 1 X i 1 and 2 X i 1 (i.e., m12 X i 1 ) and saving it back in Buffer 1 to be sent out by the DAC. (c) The DAC buffer sends 1 X i 1 out and loads X into its register and updates m12 i 1 the output. (d) This is followed by sending m12 X i 1 out and loading X 2 i 1 into the DAC buffer. (e) The completion of ADC conversion is checked. If ADC work is not finished, then it waits for the completion to occur. If ADC work is completed, then it starts to calculate the estimated averaged data based on the comparison method (i.e., Equation 2.3). In order to simplify the programming, only the 8 most significant bits (MSB) of the ADC buffer are read for averaging. Once the averaged data, is calculated, it is saved to the first register to be sent out in the following operation cycle. 1 X i, (f) FSR moves to the second address and the same process as described above is repeated. 22

31 Figure 2.8: Data flow chart and memory arrangement for the implementation of the SAR algorithm in the microcontroller. 23

32 2.3.3 Hardware Implementation of SAR System Figure 2.9 shows the schematic diagram for the hardware implementation of the SAR system. As described previously, An 8-bit microcontroller (PIC16F688 from Microchip) is programmed to execute the SAR algorithm. The microcontroller is interfaced with a 10-bit DAC (LTC1661 from Linear Technology) to convert the digitized SA template signal into an analog waveform for subtraction. The double-buffered input logic of the DAC provides simultaneous update capability. An operational amplifier (OPA277 from Texas Instruments) is utilized for subtraction. The op-amp gain is set by the ratio of R 3 /R 1. The input signal applied to the non-inverting terminal (V in+ ) is essentially the output signal from the preceding pre-amplification and filtering stages (see Fig. 2.1(b)). The estimated SA template signal from the DAC output is fed to the inverting terminal of the op-amp (V in- ). Therefore, the op-amp output signal can be derived from the following: V out R ( V V ) 3 = in+ in R1 Equation 2.4 Figure 2.9: Schematic diagram of the hardware implementation for the SAR system. 24

33 Figure 2.10 shows the schematic block diagram of the front-end neural recording and filtering circuitry. The amplified and filtered signal at the output of this block is fed as the input signal to the SAR system depicted above. The front-end recording circuitry utilizes an instrumentation amplifier (LT1167 from Linear Technology) for the INAmp circuit block. This is a low-noise wideband amplifier with very low input bias current, exhibiting very high input impedance. The filtering block consists of cascaded 2 nd -order lowpass and 2 nd -order Sallen-Key highpass filter stages, exhibiting a bandpass response from khz with unity gain. The values for all the passive components in the front-end are listed below: C 1 = 0.33 µ F, R 1 = 2 kω, R 2 = 2.74 kω, R 3 = 19.6 kω, C 2 = 1nF, C = nf C 4 = 0.1 µ F, C = 47 5 nf, R = 15 kω 4, R 5 = 5.1kΩ. Figure 2.10: Schematic block diagram of the front-end neural recording circuitry, comprising an instrumentation amplifier and two cascaded filtering stages. Figure 2.11 shows the simulated frequency response of the front-end recording circuitry in HSPICE TM. An ac gain of 60 db is achieved at 1 khz with a bandpass frequency response from khz. The front-end successfully rejects dc components in the input signal as well, as shown in the top trace of Fig A 1-kHz, 100-µV pp sinusoidal signal on a dc level of 11 mv is applied to the input. The amplifier 25

34 successfully rejects the dc component in the input and amplifies only the ac component with a gain of 60 db (bottom trace). Figure 2.11: Simulated frequency response of the front-end neural recording circuitry. Figure 2.12: Simulated ac response of the front-end neural recording circuitry. 26

35 3. Prototype System Measurement Results 3.1 Overview Figure 3.1 shows a photograph of the hardware implementation of the proposed SAR block on a custom-designed printed-circuit board, operating from ±2.5-V power supply. The input signal for the SAR block was generated in MATLAB TM using one stimulus artifact and one neural spike that were previously recorded in vivo. In order to generate an analog input waveform from the data in MATLAB TM, the data was first read by LabVIEW from the PC into a data acquisition card (DAQ) and then fed to the SAR hardware as an analog input waveform. In order to ensure that the low-amplitude data would not be corrupted by noise during this transfer, it was read into the DAQ with a gain of ~72 db (4000) set in software. At the output of the DAQ and prior to feeding the data into the SAR block, it was attenuated by the same factor to obtain the original amplitude levels for the SA and neural spike. Some of the system features and measured performance characteristics are listed in Table 3.1. Figure 3.1: Photograph of the custom-designed hardware implementation of the SAR block. 27

36 Table 3.1: System Features and Measured Performance Characteristics Front-End Recording Circuitry 1 khz f -3dB f +3dB db 260 Hz 7.9 khz SAR Block ADC # of Bits 8 DAC # of Bits 8 Sampling Rate 20 khz Memory Size 250 bytes Total System Power Supply ±2.5 V Total Power Dissipation ~35 mw 3.2 Measurement Results Four test input signals are used in system measurement. Figures 3.2(a) and 3.2(b) show two different stimulus artifact waveforms used in constructing the input signal, which were previously recorded in vivo. Three different input signals were constructed from these stimulus artifacts and a ~150-µV pp neural spike, which was also recorded in vivo. The fourth test input signal is a snapshot of pre-recorded neural activity from Aplysia californica. The four signals are described as follows: Test Signal 1: Generated with the SA in Fig. 3.1(a) with an amplitude level of 2.5 mv pp. Test Signal 2: Generated with the SA in Fig. 3.1(a) with an amplitude level of 4 mv pp. Test Signal 3: Generated with the SA in Fig. 3.1(b) with an amplitude level of 3.9 mv pp. 28

37 Test Signal 4: A snapshot of pre-recorded neural activity from Aplysia californica containing 0.4-mV pp stimulus artifacts Figure 3.2: Two different stimulus artifact waveforms used in generating the input signal for the SAR block. Measured waveforms of the prototype system with Test Signal 1 as the input are shown in Fig The top trace depicts the amplified analog input that is fed to the SAR block. A 500-ms portion of the data, as shown, contains five stimulus artifacts occurring every 100 ms (i.e., at 10 Hz) with much smaller neural action potentials randomly superimposed on the artifact data. The middle trace depicts the SA reference signal estimated by the SAR block, and the bottom trace shows the output data after subtracting the SA reference signal. Figure 3.4 shows an expanded view of a single stimulus artifact in this experiment. As can be seen in the bottom trace, there are only two residual peaks left from the stimulus artifact at its rise and fall time instances where it is rapidly varying with time. 29

38 The larger residual signal has amplitude of ~0.87 V pp, exhibiting a stimulus artifact rejection of ~9.6 db at the edges. In the slowly varying portions of the artifact including its decaying tail, the artifact is fully removed and the neural spike is recovered from the tail. Figures 3.5 and 3.6 show the same measurement results with Test Signal 2 as the input waveform to the SAR block. The same performance as before is achieved with the larger stimulus artifact residual spike having amplitude of ~1.3 V pp, exhibiting a SA rejection of ~10.2 db at the edges. A neural action potential is again fully recovered from the slowly decaying tail of the artifact. Figures 3.7 and 3.8 show the same measurement results with Test Signal 3 as the input waveform to the SAR block. The amplitude of the stimulus artifact residual signal after subtraction is ~0.72 V pp, exhibiting a suppression of ~15.1 db at the edges. Given that the stimulus artifact in Fig. 3.2(b) has much slower transitions with time compared to its counterpart in Fig. 3.1(a), it is quite expected that better stimulus artifact rejection would be achieved in this case. Figures 3.9 and 3.10 show the same measurement results using Test Signal 4 as the input waveform to the SAR block. A 2-s portion of the input data, containing five stimulus artifacts at 2.5 Hz together with smaller neural action potentials randomly occurring throughout the data, is shown in the top trace of Fig Due to slight variations in the shape of the stimulus artifact waveforms and the timing of stimulation occurrence from cycle to cycle, the system exhibits a suppression performance of only ~1.6-6 db at the edges. However, despite the two residual peaks, the slowly varying portions of the stimulus artifact are still successfully eliminated and the neural action 30

39 potentials superimposed on the decaying tail of the artifact are fully recovered as shown in Fig Figure 3.11 illustrates the measured waveforms from the SAR block with Test Signal 2 as the input at four different time instances during the operation. The plots A through D correspond to timestamps of 1, 3, 7, and 9 seconds after the operation starts. It takes ~9 seconds to reach steady state and achieve a stable reliable stimulus artifact template signal for subtraction purposes, as shown in plot D. Finally, Fig compares the measured artifact suppression results, using Test Signal 2 as the input, of the original SAR algorithm with that of the proposed SAR algorithm in hardware implementation using the pseudo-higher sampling rate concept. From the peak-to-peak amplitude of the larger stimulus artifact residual spike, it can be seen that the implemented algorithm achieves ~5.5 db higher suppression. 31

40 Figure 3.3: System measurement results with Test Signal 1. The top trace depicts the amplified signal fed to the SAR block that contains five stimulus artifacts (occurring at 10 Hz) and randomly positioned neural spikes. The middle trace depicts the estimated stimulus artifact template signal. The bottom trace shows the SAR block output after subtraction where neural spikes are recovered in between the artifacts. Residual SA Recovered Neural Spike Figure 3.4: An expanded view of the three signals in Fig. 3.3, depicting on the bottom trace the two residual stimulus artifacts as well as a neural spike recovered from the decaying tail of the artifact. 32

41 Figure 3.5: System measurement results with Test Signal 2. The top trace depicts the amplified signal fed to the SAR block that contains five stimulus artifacts (occurring at 10 Hz) and randomly positioned neural spikes. The middle trace depicts the estimated stimulus artifact template signal. The bottom trace shows the SAR block output after subtraction where neural spikes are recovered in between the artifacts. Figure 3.6: An expanded view of the three signals in Fig. 3.5, depicting on the bottom trace the two residual stimulus artifacts as well as a neural spike recovered from the decaying tail of the artifact. 33

42 Figure 3.7: System measurement results with Test Signal 3. The top trace depicts the amplified signal fed to the SAR block that contains five stimulus artifacts (occurring at 10 Hz) and randomly positioned neural spikes. The middle trace depicts the estimated stimulus artifact template signal. The bottom trace shows the SAR block output after subtraction where neural spikes are recovered in between the artifacts. Figure 3.8: An expanded view of the three signals in Fig. 3.7, depicting on the bottom trace the two residual stimulus artifacts as well as a neural spike recovered shortly after the decaying tail of the artifact. 34

43 Figure 3.9: System measurement results with Test Signal 4. The top trace depicts the amplified signal fed to the SAR block that contains five stimulus artifacts (occurring at 2.5 Hz) and randomly occurring neural spikes. The middle trace depicts the estimated stimulus artifact template signal. The bottom trace shows the SAR block output after subtraction where neural spikes are recovered in between the artifacts. Figure 3.10: An expanded view of the three signals in Fig. 3.9, depicting on the bottom trace the two residual stimulus artifacts as well as a neural spike recovered from the decaying tail of the artifact. 35

44 (a =1 second) (b = 3 seconds) (c = 7 seconds) (d = 9 seconds) Figure 3.11: Measured waveforms of the SAR block with Test Signal 1 as the input at 4 different timestamps during the operation. It takes ~9 seconds to reach steady state in plot D. 36

45 (a) Suppression with original SAR algorithm (b) Suppression with proposed SAR algorithm Figure 3.12: Stimulus artifact rejection results (with Test Signal 2) with a) the original SAR algorithm and b) the proposed SAR algorithm in hardware implementation using the pseudo-higher sampling rate concept. Additional suppression of ~5.5 db is achieved. 37

46 4. Conclusion and Future Work In this work, a stimulus artifact rejection algorithm based on the subtraction technique is first simulated using the MATLAB TM program to determine the appropriate design parameters, and is next successfully implemented in an 8-bit microcontroller using the Assembly language. The microcontroller has been interfaced with a front-end neural recording amplifier on a custom-designed printed-circuit board. The performance of the entire SAR block has been verified and characterized with input signals, containing actual stimulus artifact waveforms with various shapes and amplitudes. Compared with the existing template subtraction methods for artifact rejection [19], [20], the work proposed herein can suppress large-amplitude stimulus artifact signals in real time (online) and recover useful neural information that might be superimposed on the slowly varying portions of the artifact. In general, subtraction-based techniques by themselves do not alleviate the amplifier saturation problem. However, the amplifier gain or stimulus intensity is typically adjusted to permit non-saturated recording of the full-scale stimulus artifact and the superimposed neural spikes. From the test results, it is apparent that some residual stimulus artifact signal will still remain after subtraction, primarily at the rise and fall time instances of the artifact where it is rapidly changing with time. In future work, a possible solution for this problem could be to implement an adaptive sampling rate, which means to have a high sampling rate for the rapidly varying portions of the artifact for a more faithful representation in the template, and a lower sampling rate for the rest of the artifact (slowly varying portions) to decrease the required memory size. 38

47 5. Appendices Appendix A % MATLAB TM Code for Simulation of the SAR Algorithm close all; clear all; %load signal_1202.mat; %load signal_0218_4mv.mat; load signal_onepeak_4mv.mat; % system parameters gain=1000; % Define gain num_bits=8; % Define ADC number of bit num_reg=250; % Define memory length smp_skip=0.5; % Define sample frequency %num_reg=1200 % % initial condition trig=-2.5; %Initial trigger signal cnt=0; signal_record=zeros(1,num_reg); signal_record1=zeros(1,num_reg); signal_template=zeros(1,num_reg); signal_tem0=[]; signal_out=[]; signal_out1=[]; signal_out_add=[]; signal_tem=[]; signal_tem_add=[]; cnd=1; signal_tem0(1: )=0; signal=signal(1:smp_skip:length(signal)); sc_signal=sc_signal(1:smp_skip:length(sc_signal)); signal_tem0=signal_tem0(1:smp_skip:length(signal_tem0)); % % SAR algorithm while cnd==1 cnt=cnt+1; signal_out_add=[signal_out_add signal(cnt)*gain]; signal_tem_add=[signal_tem_add signal_tem0(cnt)]; new_trig=sc_signal(cnt); %Record input signal in non-stimulation periods if and(trig==-2.5,new_trig==2.5), %When trigger signal is high, starts SAR algorithm signal_out=[signal_out signal_out_add]; signal_tem=[signal_tem signal_tem_add]; signal_out_add=[]; signal_tem_add=[]; for cnt2=1:num_reg; adc_out1=(round((1+gain*signal(cnt+cnt2))*2^((num_bits-1)))); %Get the digitized data from ADC adc_out=(adc_out1/2^(num_bits-1))-1; 39

48 if (adc_out>signal_record(cnt2)) % Averaged methods signal_record(cnt2)=signal_record(cnt2)+(5/2^(num_bits-1)); elseif (adc_out<signal_record(cnt2)) signal_record(cnt2)=signal_record(cnt2)-(5/2^(num_bits-1)); else signal_record(cnt2)=signal_record(cnt2); end; % signal_record(cnt2)=(adc_out+31*signal_record(cnt2))/32; signal_record1(cnt2)=(signal(cnt+cnt2))*gain; signal_tem(cnt2)=[signal_record(cnt2)]; %Record input signal in stimulation period %Record template signal in stimulation period end; cnt=cnt+num_reg; signal_out=[signal_out signal_record1-signal_record]; signal_tem=[signal_tem signal_record]; %signal_out1=[ signal_out1 signal_record]; (cnt/length(signal))*100 if ((cnt/length(signal))*100)>80, cnd=0; end; %Output signal = input signal - template end; trig=new_trig; end; signal_out=[signal_out zeros(1,length(signal)-length(signal_out))]; signal_tem=[signal_tem zeros(1,length(signal)-length(signal_tem))] % % Plot Results %signal=signal(400000:440000); %sc_signal=sc_signal(400000:440000); %signal_tem=signal_tem(400000:440000); %signal_out=signal_out(400000:440000); timestep=(1:length(signal))/40000; figure(1); subplot (4,1,1); plot (timestep,signal); subplot (4,1,2); plot (timestep,sc_signal); subplot (4,1,3); plot (timestep,signal_tem); subplot (4,1,4); plot(timestep,signal_out); 40