NLAS Low Voltage Single Supply Dual DPDT Analog Switch

Size: px

Start display at page:

Download "NLAS Low Voltage Single Supply Dual DPDT Analog Switch"

Adela Haynes
5 years ago
Views:

Low Voltage Single Supply Dual DPDT Analog Switch The NLAS4499 is an advanced dual independent CMOS double pole double throw (DPDT) analog switch fabricated with silicon gate CMOS technology.

1 Low Voltage Single Supply Dual DPDT Analog Switch The NLAS4499 is an advanced dual independent CMOS double pole double throw (DPDT) analog switch fabricated with silicon gate CMOS technology. It achieves high speed propagation delays and low ON resistances while maintaining CMOS low power dissipation. This DPDT controls analog and digital voltages that may vary across the full power supply range (from to GND). The device has been designed so the ON resistance (R ON ) is much lower and more linear over input voltage than R ON of typical CMOS analog switches. The channel select input is compatible with standard CMOS outputs. The channel select input structure provides protection when voltages between V and. V are applied, regardless of the supply voltage. This input structure helps prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc. The NLAS4499 can also be used as a quad 2 to multiplexer demultiplexer analog switch with two Select pins that each controls two multiplexer demultiplexers. Channel Select Input Over Voltage Tolerant to. V Fast Switching and Propagation Speeds Break Before Make Circuitry Low Power Dissipation: I CC = 2 A (Max) at T A = 2 C Diode Protection Provided on Channel Select Input Improved Linearity and Lower ON Resistance over Input Voltage Latch up Performance Exceeds 3 ma ESD Performance: Human Body Model; > 2 V, Machine Model; > 2 V Chip Complexity: 8 FETs Pb Free Packages are Available QFN 6 MN SFFIX CASE 48G TSSOP 6 DT SFFIX CASE 948F A L Y W 6 AS 449 ALYW MARKING DIAGRAMS Current Part Marking = Assembly Location = Wafer Lot = Year = Work Week 6 C ALYW Previous Part Marking* *Previous releases of this device may be marked as shown in this diagram. 6 6 NLAS 449 ALYW ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, 2 April, 2 Rev. 3 Publication Order Number: NLAS4499/D

2 QFN 6 PACKAGE COM A NO A 6 4 NC D 3 FNCTION TABLE Select AB or CD On Channel L H NC to COM NO to COM NC A 2 COM D SAB 2 See TSSOP 6 Switch Configuration NO D NO B 3 SCD COM B 4 9 NC C NC B GND NO C COM C SELECT AB X NO A COM A / NC A TSSOP 6 PACKAGE COM B 2/3 2 3 NO B NC B NO A 6 SELECT CD X NO C COM A 2 NC D COM C / 2 NC C NO D NC A 3 4 COM D COM D 2/3 3 NC D SELECT AB 4 3 NO D Figure 2. IEC Logic Symbol NO B 2 SELECT CD COM B 6 NC C NC B 7 COM C GND 8 9 NO C Figure. Logic Diagram 2

3 MAXIMM RATINGS Symbol Parameter Value nit Positive DC Supply Voltage. to 7. V V IS Analog Input Voltage (V NO or V COM ). V IS. V IN Digital Select Input Voltage. V I 7. V I IK DC Current, Into or Out of Any Pin ma P D Power Dissipation in Still Air QFN 6 TSSOP mw T STG Storage Temperature Range 6 to C T L Lead Temperature, mm from Case for Seconds 26 C T J Junction Temperature nder Bias + C MSL Moisture Sensitivity Level F R Flammability Rating Oxygen Index: 3% 3% L 94 V (.2 in) V ESD ESD Withstand Voltage Human Body Model (Note ) Machine Model (Note 2) Charged Device Model (Note 3) 2 2 V I Latch p Latch p Performance Above and Below GND at 2 C (Note 4) 3 ma JA Thermal Resistance QFN 6 TSSOP C/W Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions.. Tested to EIA/JESD22 A4 A. 2. Tested to EIA/JESD22 A A. 3. Tested to JESD22 C A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max nit DC Supply Voltage 2.. V V IN Digital Select Input Voltage GND. V V IS Analog Input Voltage (NC, NO, COM) GND V T A Operating Temperature Range 2 C t r, t f Input Rise or Fall Time, SELECT = 3.3 V.3 V =. V. V 2 ns/v DEVICE JNCTION TEMPERATRE VERSS TIME TO.% BOND FAILRES Junction Temperature C Time, Hours Time, Years 8,32, , , , , , ,9. NORMALIZED FAILRE RATE FAILRE RATE OF PLASTIC = CERAMIC NTIL INTERMETALLICS OCCR T J = 3 C T J = 2 C T J = C T J = C TIME, YEARS Figure 3. Failure Rate vs. Time Junction Temperature T J = 9 C T J = 8 C 3

4 DC CHARACTERISTICS Digital Section (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Condition C to 2 C 8 C 2 C nit V IH Minimum High Level Input V Voltage, Select Inputs V IL I IN Maximum Low Level Input Voltage, Select Inputs Maximum Input Leakage Current V IN =. V or GND A V I OFF I CC Power Off Leakage Current, Select Inputs Maximum Quiescent Supply Current V IN =. V or GND A Select and V IS = or GND A DC ELECTRICAL CHARACTERISTICS Analog Section Guaranteed Limit Symbol Parameter Condition C to 2 C 8 C 2 C nit R ON Maximum ON Resistance (Figures 7 23) V IN = V IL or V IH V IS = GND to I IN I. ma R FLAT (ON) ON Resistance Flatness (Figures 7 23) V IN = V IL or V IH I IN I. ma V IS = V, 2 V, 3. V I NC(OFF) I NO(OFF) NO or NC Off Leakage Current (Figure 9) V IN = V IL or V IH V NO or V NC =. V COM 4. V. na I COM(ON) COM ON Leakage Current (Figure 9) V IN = V IL or V IH V NO. V or 4. V with V NC floating or V NO. V or 4. V with V NO floating V COM =. V or 4. V. na 4

5 AC ELECTRICAL CHARACTERISTICS (Input t r = t f = ns) Symbol Parameter Test Conditions t ON Turn On Time (Figures 2 and 3) R L = 3 C L = 3 pf (Figures and 6) Guaranteed Maximum Limit V IS C to 2 C 8 C 2 C (V) (V) Min Typ* Max Min Max Min Max nit ns t OFF Turn Off Time (Figures 2 and 3) R L = 3 C L = 3 pf (Figures and 6) ns t BBM Minimum Break Before Make Time V IS = V (Figure 4) R L = 3 C L = 3 pf ns C IN C NO or C NC C COM C (ON) Maximum Input Capacitance, Select Input Analog I/O (switch off) Common I/O (switch off) Feedthrough (switch on) *Typical Characteristics are at 2 C. 2, =. V 8 2 pf ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND nless Noted) Symbol Parameter Condition BW Maximum On Channel 3dB Bandwidth or Minimum Frequency Response (Figure ) V IN = dbm V IN centered between and GND (Figure 7) V ONL Maximum Feedthrough On Loss V IN = khz to MHz V IN centered between and GND (Figure 7) V ISO Off Channel Isolation (Figure ) f = khz; V IS = V RMS V IN centered between and GND (Figure 7) Q Charge Injection Select Input to Common I/O (Figure ) THD Total Harmonic Distortion THD + Noise (Figure 4) V IN = to GND, F IS = 2 khz t r = t f = 3 ns R IS =, C L = pf Q = C L * V OT (Figure 8) VCT Channel to Channel Crosstalk f = khz; V IS = V RMS V IN centered between and GND (Figure 7) Typical V 2 C nit 4 MHz F IS = 2 Hz to khz, R L = Rgen = 6, C L = pf V IS =. V PP sine wave db db pc % db

6 . F DT V OT 3 3 pf Input GND 9% t BMM 9% of V OH Switch Select Pin GND Figure 4. t BBM (Time Break Before Make) DT Input V % %. F Open V OT 3 3 pf V OH 9% 9% V OL Input t ON t OFF Figure. t ON /t OFF DT 3 Input V % % Open V OT 3 pf VOH V OL % % Input t OFF t ON Figure 6. t ON /t OFF 6

7 Reference DT Generator Input Transmitted Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. V ISO, Bandwidth and V ONL are independent of the input signal direction. V ISO = Off Channel Isolation = 2 Log V OT for V IN at khz VIN V ONL = On Channel Loss = 2 Log V OT for V IN at khz to MHz VIN Bandwidth (BW) = the frequency 3 db below V ONL V CT = se V ISO setup and test to all other switch analog input/outputs terminated with Figure 7. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/V ONL DT Open V IN GND C L V IN Off On Off V OT Figure 8. Charge Injection: (Q) LEAKAGE (na)... I COM(ON) I COM(OFF) =. V I NO(OFF) TEMPERATRE ( C) Figure 9. Switch Leakage vs. Temperature 7

8 (db) Off Isolation.. FREQENCY (MHz) =. V T A = 2 C 2 (db) Bandwidth (ON RESPONSE) PHASE SHIFT =. V T A = 2 C FREQENCY (MHz) PHASE ( ) Figure. Off Channel Isolation Figure. Typical Bandwidth and Phase Shift = 4. V 2 2 TIME (ns) t ON (ns) TIME (ns) t ON t OFF (ns) t OFF (VOLTS) Figure 2. t ON and t OFF vs. at 2 C Temperature ( C) Figure 3. t ON and t OFF vs. Temp V INpp = V = 3.6 V 2. THD + NOISE (%). V INpp =. V =. V Q (pc) = 3 V = V. FREQENCY (khz) Figure 4. Total Harmonic Distortion Plus Noise vs. Frequency V COM (V) Figure. Charge Injection vs. COM Voltage 8

9 I CC (na).. = V.. =. V Temperature ( C) Figure 6. I CC vs. Temp, = 3 V & V = 2. V 8 6 = 2. V 4 = V = 4. V 2 =. V Figure 7. R ON vs., Temp = 2 C C 3 2 C 2 C 8 C Figure 8. R ON vs Temp, = 2. V C 2 C C 8 C Figure 9. R ON vs. Temp, = 2. V C 8 C 2 C C Figure 2. R ON vs. Temp, = V C 8 C 2 C C Figure 2. R ON vs. Temp, = 4. V 9

10 C 2 2 C 8 C 2 C C 8 C 2 C C Figure 22. R ON vs. Temp, =. V Figure 23. R ON vs. Temp, =. V DEVICE ORDERING INFORMATION Device Circuit Indicator Technology Device Nomenclature Device Function Package Suffix Tape & Reel Suffix Package Type Shipping NLAS4499DT NL AS 4499 DT TSSOP 6* 96 / nit Rail NLAS4499DTR2 NL AS 4499 DT R2 TSSOP 6* 2 / Tape & Reel NLAS4499MN NL AS 4499 MN QFN 6 24 nit / Rail NLAS4499MNG NL AS 4499 MN QFN 6 (Pb Free) 24 nit / Rail NLAS4499MNR2 NL AS 4499 MN R2 QFN 6 2 / Tape & Reel NLAS4499MNR2G NL AS 4499 MN R2 QFN 6 (Pb Free) 2 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. *This package is inherently Pb Free.

11 PACKAGE DIMENSIONS QFN 6 MN SFFIX CASE 48G ISSE B PIN LOCATION ÎÎÎ D A B E NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASRED BETWEEN.2 AND.3 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.. L max CONDITION CAN NOT VIOLATE.2 MM MINIMM SPACING BETWEEN LEAD TIP AND FLAG. C. C. C TOP VIEW (A3) A MILLIMETERS DIM MIN MAX A.8. A.. A3.2 REF b.8.3 D BSC D2.6.8 E BSC E2.6.8 e. BSC K.2 L.3. 6 X.8 C SIDE VIEW A C SEATING PLANE SOLDERING FOOTPRINT 6X L NOTE D2 e 8 EXPOSED PAD EXPOSED PAD 4 9 6X K e 2 E C. C 6X b A B NOTE BOTTOM VIEW..2 SCALE :.3.2 mm inches

12 PACKAGE DIMENSIONS TSSOP 6 CASE 948F ISSE A. (.6) T. (.6) T. (.4) T SEATING PLANE L PIN IDENT. D S S 2X L/2 C 6X K REF. (.4) M T S V S A V G B H N N J NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLDE MOLD K FLASH. PROTRSIONS OR GATE BRRS. K MOLD FLASH OR GATE BRRS SHALL NOT EXCEED. (.6) PER SIDE. ÎÎÎ ÏÏÏ 4. DIMENSION B DOES NOT INCLDE INTERLEAD FLASH OR PROTRSION. J ÎÎÎ INTERLEAD FLASH OR PROTRSION SHALL NOT EXCEED.2 (.) PER SIDE.. DIMENSION K DOES NOT INCLDE SECTION N N DAMBAR PROTRSION. ALLOWABLE DAMBAR PROTRSION SHALL BE.8 (.3) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMM MATERIAL CONDITION. 6. TERMINAL NMBERS ARE SHOWN FOR REFERENCE ONLY..2 (.) 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX M A B C.2.47 D F F G.6 BSC.26 BSC DETAIL E H J J K K W L 6.4 BSC.22 BSC M 8 8 DETAIL E ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PBLICATION ORDERING INFORMATION LITERATRE FLFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 632, Phoenix, Arizona SA Phone: or Toll Free SA/Canada Fax: or Toll Free SA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free SA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2 9 Kamimeguro, Meguro ku, Tokyo, Japan 3 Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. NLAS4499/D

NLAS Low Voltage Single Supply Dual DPDT Analog Switch

NLAS Low Voltage Single Supply Dual DPDT Analog Switch NLAS4499 Low Voltage Single Supply Dual DPDT Analog Switch The NLAS4499 is an advanced dual independent CMOS double pole double throw (DPDT) analog switch fabricated with silicon gate CMOS technology.