NLAS4051. Analog Multiplexer/ Demultiplexer. TTL Compatible, Single Pole, 8 Position Plus Common Off
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1 NLAS4 Analog Multiplexer/ Demultiplexer TTL Compatible, SinglePole, 8Position Plus Common Off The NLAS4 is an improved version of the MC4 and MC74HC4 fabricated in submicron Silicon Gate CMOS technology for lower R DS(on) resistance and improved linearity with low current. This device may be operated either with a single supply or dual supply up to ±3. to pass a 6. PP signal without coupling capacitors. When operating in single supply mode, it is only necessary to tie EE, pin 7 to ground. For dual supply operation, EE is tied to a negative voltage, not to exceed maximum ratings. Features Improved R DS(on) Specifications Pin for Pin Replacement for MAX4 and MAX4A One Half the Resistance Operating at. Single or Dual Supply Operation Single 2.. Operation, or Dual ±3. Operation With of 3. to 3.3, Device Can Interface with.8 Logic, No Translators Needed Address and Inhibit Logic are Overoltage Tolerant and May Be Driven Up +6. Regardless of Improved Linearity Over Standard HC4 Devices Popular SOIC, and Space Saving TSSOP, and QSOP Pin Packages PbFree Packages are Available* SOIC D SUFFIX CASE 7B TSSOP DT SUFFIX CASE 948F QSOP QS SUFFIX CASE 492 A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or = PbFree Package MARKING DIAGRAMS NLAS4G AWLYWW NLAS 4 ALYW S4 ALYW NO 2 NO 4 NO NO 6 ADD C ADD B ADD A NO NO 3 COM NO 7 NO Inhibit EE Figure. Pin Connection (Top iew) 8 ORDERING INFORMATION Device Package Shipping NLAS4DR2 SOIC /Tape & Reel NLAS4DR2G SOIC (PbFree) /Tape & Reel NLAS4DTR2 TSSOP /Tape & Reel NLAS4DTR2G TSSOP (PbFree) /Tape & Reel NLAS4QSR QSOP /Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 26 May, 26 Rev. 3 Publication Order Number: NLAS4/D
2 NLAS4 TRUTH TABLE Inhibit X don t care Address C B A X don t care X don t care ON SWITCHES* All switches open COMNO COMNO COMNO 2 COMNO 3 COMNO 4 COM NO NO NO 2 NO 3 NO 4 NO NO 6 COMNO COMNO 6 COMNO 7 *NO and COM pins are identical and interchangeable. Either may be considered an input or output; signals pass equally well in either direction. ADD C ADD B ADD A LOGIC NO 7 Figure 2. Logic Diagram Inhibit ÎÎ MAXIMUM RATINGS Parameter SymbolÎÎÎÎÎÎÎ alue ÎÎ Unit Negative DC Supply oltage (Referenced to ) EE ÎÎÎÎÎÎÎ 7. to. ÎÎ Positive DC Supply oltage (Note ) (Referenced to ) ÎÎÎÎÎÎÎ. to 7. ÎÎ (Referenced to EE ). to 7. ÎÎÎÎÎÎÎ ÎÎ Analog oltage IS EE. to. Digital oltage (Referenced to ) IN. to 7. DC Current, Into or Out of Any Pin I ma Storage Temperature Range 6 to T STG C Lead Temperature, mm from Case for Seconds T L ÎÎÎÎÎÎÎ 26 ÎÎ C Junction Temperature under Bias T J ÎÎÎÎÎÎÎ ÎÎ C Thermal Resistance SOIC JA ÎÎÎÎÎÎÎ 43 ÎÎ TSSOP ÎÎÎÎÎÎÎ 4 ÎÎ C/W QSOP 4 Power Dissipation in Still Air, SOIC P D TSSOP ÎÎÎÎÎÎÎ 4 ÎÎ mw QSOP 4 Moisture Sensitivity MSL Level Flammability Rating Oxygen Index: 3% 3% F R UL in ESD Withstand oltage Human Body Model (Note 2) ESD 2 Machine Model (Note 3) ÎÎÎÎÎÎÎ 2 ÎÎ Charged Device Model (Note 4) Latchup Performance Above and Below at C (Note ) I LATCHUP ÎÎÎÎÎÎÎ 3 ÎÎ ma Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. The absolute value of EE Tested to EIA/JESD22A4A. 3. Tested to EIA/JESD22AA. 4. Tested to JESD22CA.. Tested to EIA/JESD78. 2
3 NLAS4 RECOMMENDED OPERATING CONDITIONS Parameter ÎÎÎÎÎ Symbol Min Max Unit.ÎÎÎ Î Negative DC Supply oltage (Referenced to ) EE ÎÎÎ ÎÎ Î Positive DC Supply oltage (Referenced to ) ÎÎÎ 2. ÎÎÎ. ÎÎ (Referenced to EE ) Î ÎÎÎ ÎÎÎÎÎ Analog oltage IS EE Î ÎÎÎ ÎÎÎÎÎ Digital oltage (Note 6) (Referenced to ) IN. Î ÎÎÎ ÎÎÎÎÎ Operating Temperature Range, All Package Types T A C Î ÎÎÎ ÎÎÎÎÎ Rise/Fall Time Î CC = 3..3 t r, t f ÎÎÎ ÎÎÎ ÎÎ ns/ (Channel Select or Enable s) =.. 6. Unused digital inputs may not be left open. All digital inputs must be tied to a highlogic voltage level or a lowlogic input voltage level. 2 DC CHARACTERISTICS Digital Section (oltages Referenced to ) Parameter Minimum HighLevel oltage, Address and Inhibit s Maximum LowLevel oltage, Address and Inhibit s Maximum Leakage Current, Address or Inhibit s Condition Guaranteed Limit Symbol to C 8 C C IH IL IN = 6. or I IN to A Unit Maximum Quiescent Supply Current (per Package) Address, Inhibit and IS = or I CC A DC ELECTRICAL CHARACTERISTICS Analog Section SymbolÎÎÎ ÎÎÎ ÎÎ Parameter Test Conditions ÎÎÎÎÎÎ ÎÎ Guaranteed Limit ÎÎ EE ÎÎÎÎÎ to CÎÎÎ 8 CÎÎÎÎ C ÎÎ Unit Maximum ON Resistance IN = IL or IH R ON ÎÎÎ 3. ÎÎ ÎÎÎÎÎ 86 ÎÎÎ 8ÎÎÎÎ 2 ÎÎ (Note 7) IS = ( EE to ) I S = ma ÎÎÎ 3. ÎÎ 3. ÎÎÎÎÎ 26 ÎÎÎ 33 ÎÎÎÎ 37 ÎÎ (Figures 4 thru 9) ÎÎÎÎÎ Maximum Difference in ON Resistance Between Any Two IN = IL or IH, IS = 2. R ON IS = ½ ( EE ), IS = 3. ÎÎÎ ÎÎ ÎÎÎÎÎ 3 ÎÎÎ 8 ÎÎÎÎ 8 ÎÎ Channels in the Same Package I S = ma, IS = 2. ÎÎÎ 3. ÎÎ 3. ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ON Resistance Flatness Maximum OffChannel Leakage Current Maximum OnChannel Leakage Current, Channel tochannel I S = ma COM =, 2, 3. COM = 2,, 2 Switch Off IN = IL or IH IO =. or EE +. (Figure 7) Switch On IO =. or EE +. (Figure 7) Rflat(ON) I NC(OFF) 6. I NO(OFF) 3. I COM(ON) At supply voltage ( ) approaching 2. the analog switch onresistance becomes extremely nonlinear. Therefore, for low voltage operation it is recommended that these devices only be used to control digital signals na na 3
4 NLAS4 AC CHARACTERISTICS ( t r = t f = 3 ns) ÎÎ Guaranteed Limit ÎÎ Î Parameter Test Conditions ÎÎÎÎ Symbol ÎÎ ÎÎÎ to C ÎÎÎÎÎÎÎ EE ÎÎÎ Min ÎÎÎ Typ* ÎÎÎ 8 CÎÎÎÎ C ÎÎ Unit Minimum BreakBefore Make Time *Typical Characteristics are at C. IN = IL or IH IS = R L = 3 C L = 3 pf (Figure 9) AC CHARACTERISTICS (C L = 3 pf, t r = t f = 3 ns) t BBM ns Parameter Transition Time (Address Selection Time) (Figure 8) Turnon Time (Figures 4,, 2, and 2) Inhibit to N O or N C Turnoff Time (Figures 4,, 2, and 2) Inhibit to N O or N C Guaranteed Limit to C 8 C C EE Symbol Min Typ Max Min Max Min Max t TRANS t ON t OFF Unit ns ns ns C, =. Maximum Capacitance, Select s C IN 8 pf Analog I/O C NO or C NC Common I/O C COM Feedthrough C (ON). ADDITIONAL APPLICATION CHARACTERISTICS ( = ) Parameter Maximum OnChannel Bandwidth or Minimum Frequency Response Condition IS = ½ ( EE ) Source Amplitude = dbm (Figures and 22) OffChannel Feedthrough Isolation f = khz; IS = ½ ( EE ) Source = dbm (Figures 2 and 22) Maximum Feedthrough On Loss IS = ½ ( EE ) Source = dbm (Figures and 22) Charge Injection Total Harmonic Distortion THD + Noise IN = to EE, f IS = khz, t r = t f = 3 ns R IS =, C L = pf, Q = C L * OUT (Figures and ) f IS = MHz, R L = K, C L = pf, IS =. PP sine wave IS = 6. PP sine wave (Figure 3) EE Typ Symbol C BW ISO ONL Q. 3. THD Unit MHz db db pc % 4
5 NLAS4 I CC (na).... = 3. = Temperature ( C) Figure 3. I CC versus Temp, = 3 and IS (DC) Figure 4. R ON versus, Temp = C C C 8 C C Com () Figure. Typical On Resistance = 2., EE = C 8 C C C Com () Figure 6. Typical On Resistance = 3., EE = 2 8 C C 2 8 C C C C C C Com () Figure 7. Typical On Resistance =, EE = Com () Figure 8. Typical On Resistance =., EE =
6 NLAS4 2 8 C C C C Com () Figure 9. Typical On Resistance = 3.3, EE = BANDWIDTH (db) BANDWIDTH (ONRESPONSE).. PHASE SHIFT 8%/DI (db) PHASE SHIFT.. FREQUENCY (mhz) FREQUENCY (mhz) Figure. Bandwidth, =. Figure. Phase Shift, =. OFF ISOLATION db/di DISTORTION (%) FREQUENCY (mhz) Figure 2. Off Isolation, =.. FREQUENCY (mhz) Figure 3. Total Harmonic Distortion 6
7 NLAS4 3 3 T A = C = 2 2 TIME (ns) t ON (ns) TIME (ns) t ON t OFF (ns) t OFF (OLTS) Figure 4. t ON and t OFF versus 4 8 Temperature ( C) Figure. t ON and t OFF versus Temp 3. Q (pc) = = 3 LEAKAGE (na).. I COM(ON) I COM(OFF) = COM (). I NO(OFF) TEMPERATURE ( C) Figure. Charge Injection versus COM oltage Figure 7. Switch Leakage versus Temperature. F EE 3 OUT 3 pf % % 9% Address Select Pin EE % t trans t trans Figure 8. Channel Selection Propagation Delay 7
8 NLAS4. F DUT 3 OUT 3 pf 9% t BMM 9% of OH Address Select Pin Figure 9. t BBM (Time BreakBeforeMake) DUT % %. F Open 3 OUT 3 pf OH 9% 9% Enable t ON t OFF Figure 2. t ON /t OFF DUT 3 % % Open 3 pf OUT CC Enable OL t OFF % t ON % Figure 2. t ON /t OFF 8
9 NLAS4 Reference Generator DUT Transmitted Channel switch Address and Inhibit/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. ISO, Bandwidth and ONL are independent of the input signal direction. ISO = Off Channel Isolation = 2 Log OUT for IN at khz IN ONL = On Channel Loss = 2 Log OUT for IN at khz to MHz IN Bandwidth (BW) = the frequency 3 db below ONL Figure 22. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/ ONL DUT Open IN C L IN Off On Off OUT Figure. Charge Injection: (Q) TYPICAL OPERATION EE 7 8 EE Figure 24.. olts Single Supply =., EE = Figure. Dual Supply = 3., EE = 3. 9
10 NLAS4 PACKAGE DIMENSIONS SOIC D SUFFIX CASE 7B ISSUE J A 9 8 B P 8 PL. (.) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION. (.6) PER SIDE.. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.27 (.) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE G K C D PL. (.) M T B S A S M R X 4 J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC. BSC J K M 7 7 P R....9 TSSOP CASE 948F ISSUE A. (.6) T. (.6) T. (.4) T SEATING PLANE L U PIN IDENT. U D S S 2X L/2 C X K REF. (.4) M T U S S 9 8 A G B U H N J N J F DETAIL E DETAIL E K K ÇÇÇ ÉÉÉ SECTION NN. (.) M W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED. (.6) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED. (.) PER SIDE.. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.8 (.3) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C.2.47 D F G.6 BSC.26 BSC H J J K K L 6.4 BSC.2 BSC M 8 8
11 NLAS4 PACKAGE DIMENSIONS QSOP QS SUFFIX CASE 492 ISSUE O L B. (.) M T C A G R U K P Q H x 4 RAD..3 X. DP. MAX RAD... TYP DETAIL E MOLD PIN MARK N 8 PL NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: INCH. 3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE ONLY). BOTTOM PACKAGE DIMENSION SHALL FOLLOW THE DIMENSION STATED IN THIS DRAWING. 4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 6 MILS PER SIDE.. BOTTOM EJECTOR PIN WILL INCLUDE THE COUNTRY OF ORIGIN (COO) AND MOLD CAITY I.D. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G. BSC.64 BSC H J K.4... L M 8 8 N 7 7 P Q.2 DIA. DIA R U D PL. (.) M T B S A S T SEATING PLANE M J F DETAIL E ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 3, Denver, Colorado 827 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 8298 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NLAS4/D
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