A 90nm Variable Frequency Clock System for a Power- Managed Itanium Architecture Processor

Transcription

1 A 90nm Variable Frequency Clock System for a Power- Managed tanium Architecture Processor Tim Fischer, Ferd Anderson, Ben Patella, Sam Naffziger ntel, Fort Collins, CO

2 Presentation Overview Montecito Clock System Architecture Montecito Voltage to Frequency Converter (VFC) Architecture Digital Frequency Divider (DFD) Regional Voltage Detector (RVD) Results Summary and Acknowledgements

3 Clock System Architecture Variable Supply SLCB CVD Gater Pins Fuses Frequency Translation Table Divisors DFD RVD SLCB RAD Balanced Tree Clock Distribution Fixed Supply Bus Clock 1/1 PLL 1/M Core0 Core1 Foxton /Os Bus Logic DFD DFD DFD DFD DFD CVD Gater SLCB CVD Gater SLCB RAD CVD Gater SLCB CVD Gater 1/N 1/N Phase Aligner

4 Montecito Clock Generation Overview PLL generates master clock: Fmax = M*F bus_clock DFDs lock on Fmax using local DLLs Synthesize core / uncore frequencies in 1.6% Fmax steps (ticks) DFD range is Fmax*1.0 to Fmax*0.504 Translation table sets DFD frequency at startup Supply / Clock Domains 2 Cores : variable V, F Uncore (bus logic): fixed V, F = N * bus clock Foxton controller : fixed V, F = 1 GHZ, DSP algorithms Master PLL : fixed V, F, within clock system only

5 Montecito Clock System Floorplan RVDs PLL / translation table / clock control CORE 0 Core DFDs FSB DFDs Foxton Controller DFD Bus Logic DFD FSB DFDs CORE 1

6 Clock System Modes Fixed Frequency (FFM) Cores/Uncore are frequency and phase aligned Cores/Uncore interfaces synchronous Variable Frequency (VFM) Core supply modulated by Foxton Controller to manage power envelope Core frequencies track Vcore via Regional Voltage Detector (RVD) V-F curves Respond to Foxton modulation and local transients V-F curves match worst-scaling paths on chip Core/Uncore interfaces asynchronous

7 Voltage-to-Frequency Conversion (VFC) Per Core Foxton-managed VDD from VR di/dt noise + VDD Local Blocks RVD8 Process, Temp RVD8 local environment RVD9 ~2400um RVD10 RVD11 DOWN[11:8], HOLD[11:8] DFD2 2 Utility Clocks 4 Utility Clocks L1 Clock Route To SLCBS RVD4 RVD5 RVD6 RVD7 L0 Clock Route from PLL DOWN[7:4], HOLD[7:4] 2 RVD0 RVD1 RVD2 RVD3 8 2 DFD1 4 2 Utility Clocks L1 Clock Route To SLCBS DOWN[3:0], HOLD[3:0] 8 DFD0 4 L1 Clock Route To SLCBS

8 DFD Output Clock Example VFC Supply Droop Response Clock period increased No Adjust needed this cycle Vcore RVD Delay Line Clock Droop increases RVD delay line delay ncreased delay asserts period UP for two cycles Period UP to DFD

9 PLL CLOCK DFFERENTAL NPUT RVD UP / DOWN REQUESTS 16-PHASE DLL AND NTERPOLATON PCSM TO / FROM SAME-CORE PCSMS Digital Frequency Divider (DFD) Block Diagram 64 PHASES PEROD ADJUST +2 TO -1 STATE MACHNE ODCS CONTROL DVDE BY 2 STARTUP CONTROL DVDE BY 2 ½ FREQUENCY QUADRATURE DFFERENTAL CLOCK ROUTES TO SLCBS FULL FREQUENCY DFFERENTAL UTLTY CLOCK ROUTES TO CLOCK SYSTEM SCAN AND TRGGERS

10 DFD Phase Selection Datapath FROM PCSM FROM S/M adj0 psel0 FROM DLL rck VDD adj3 psel3 GND VDD VDD GND sel0 sel1 phs0 phs1 GND VDD sel8 sel9 phs8 phs9 pd0 sel7 phs7 GND pd1 sel15 phs15 GND VDD GND clk_15_0_out fb_terms VDD pd GND clk_31_16_out clk_47_32_out clk_63_48_out CLOCK O 4:1 PHASE ADJUST 16:1 PHASE SELECTON 4:1 PHASE OR & CLOCK DRVE

11 VFC/RVD Voltage Tracking and CMOS Critical Path Scaling Delay (norm to 1100 mv) Supply Voltage (mv) circuit1 circuit2 circuit3 circuit4 circuit5

12 RVD Block Diagram Delay Line 0A dly0in dly0out HOLD Delay Line 0B RVD FSM eval0 eval1 eval0 eval1 additional delay CVDs create deadzone dly1in Delay Line 1A dly1out DOWN clk Delay Line 1B eval0 eval1

13 RVD Delay Line in FNE R F R odd F coarse_sel Coarse Delay ncremental Curves R R COARSE F F F F F F F R R Dynamic Mux R R delay line out Fine Delay ncremental Curves R 1.60E E E E E E E E E E E-10 4 Coarse Elements 6.00E E E E E E E-10 3 Coarse Elements

14 RVD Coarse Delay Element run config_fet nrun nfet nrun fet nodd nclear VDD fbp VDD nrun VDD nfet out O in GND run GND fbn Metal 1 Serpentine Resistor nrun nout clear even GND fbp run

15 RVD Phase Comparator rck in0 VDD noh in1 out O ev0 nd0 ev1 nd1 eck GND

16 V c ore b) VFM Performance ncrease (%) Time (ps ) Supply Noise (mv) x V c ore PS D (dbv) c) Average (50 MHz Noise) Peak Time 10-1 (ps ) Frequency (GHz) VFM Performance vs. Supply Noise a) 50% Activity Power Virus

17 FFM/VFM Core/Bus Clock Oscilloscope Traces FFM, 1.2V Core clock 1.6GHz Bus Logic clock 1.6GHz VFM, 1.2V Core clock 2.14GHz Bus Logic clock 1.6GHz

18 Core Clock Spectral Content FFM Fmax=2GHz, Ffixed=1.6GHz, 1.2Vcore VFM Fmax=2GHz, 1.2 Vcore +/- 100mV, slow RVD curve

19 Summary Clock system enables a dynamic voltage-scaling power management system (Foxton) Generates low-skew fixed- and variable- frequency clocks High-BW Voltage-to-Frequency conversion (VFC) Regional Voltage Detectors Synchronized Digital Frequency Dividers VFC follows programmed V/F response VFC lock onto and tracks local supply voltage Tracks high-bw switching transients:1 cycle VFC loop response Tracks low-bw Foxton-based supply modulation Performance benefits through reduced guardband: Fast response to switching transients (3-8%, path dependent) Tracks process, temperature (3%) VFM operation demonstrated above 2GHz

20 Acknowledgements E. Fetzer, S. Ghahremani, B. Doyle, A. Barton, M. Peters, S. Hall, J. Desai, E. Lee, F. Verdico, C. Pie, C. Bendele, A. Allen, R. Alley, P. Wyatt, B. Johnson, S. Undy, G. Benjamin, R. McGowen, R. Sandoval, C. Zhu, C. Young, A. Shoning, J. McBride, K. Kerr, D. Newsome, D. Sherlock, B. Haskin, J. Platenak, A. Gouldey, V. Freytag, R. Sims, G. Kumar, J. Pettsinger, R. Weidner, P. Liu, S. Wells, D. Clifford, S. Liepe, J. gnowski, G. Ranson, P. Kummrow, C. Keen, W. Kever