A transparent, conformable, active multielectrode array using organic electrochemical transistors

Transcription

1 Supplementary Information A transparent, conformable, active multielectrode array using organic electrochemical transistors Wonryung Lee a, Dongmin Kim a,b, Naoji Matsuhisa a, Masae Nagase a,b, Masaki Sekino a,b, George G Malliaras c, Tomoyuki Yokota a,b, and Takao Someya a,b,d,1 a Department of Electrical Engineering and Information Systems, The University of Tokyo, Hongo, Bunkyo-ku, Tokyo , Japan b Exploratory Research for Advanced Technology (ERATO), Japan Science and Technology Agency (JST), Hongo, Bunkyo-ku, Tokyo , Japan c Ecole Nationale Supérieure des Mines, 880, route de Mimet, Gardanne, France d Thin-Film Device Laboratory & Center for Emergent Matter Science (CEMS), RIKEN, 2-1 Hirosawa, Wako, Saitama , Japan

2 Figure S1: Fabrication process for manufacturing the electrophysiology array with transparent organic electrochemical transistors (OECTs).

3 Figure S2: Correlation between the conductance and transparency of the Au grid, which is obtained by calculation. (ρ = Ωm, Tc = (p w) 2 / p 2 ).

4 Figure S3: Microscope image (Scale bar: 1 mm) of (A) transparent OECT and (B) nontransparent OECT with a magnified view (Scale bar: 70 μm).

5 Figure S4: The bandwidth of the transparent OECT (W/L = 70 µm/20 µm) (A) The schematic of the measurement set-up (B) The I V curve of the transparent OECT. gm was 3.5 ms (Vg = 0 V). (C) Ids fluctuation when 10 mv amplitude of sinusoidal Vgs was applied. (D) gm of transparent OECT at various frequencies.

6 Figure S5: Leakage current of 1.2-μm-thick SU-8 with DC bias in 37 degrees PBS (A) Schematic of experimental setting for evaluation of leakage current (B) The leakage current after dipping 0 hr and 24 hrs. (C) The time-leakage current curve at 0.6V bias voltage.

7 Figure S6: The long-term gate leakage current of OECTs in 37 degrees PBS (A) Schematic of experimental setting for evaluation of gate leakage current of OECTs (B) The drain current (Id) and gate leakage current (Ig) after dipping 0 hr and 24 hrs. (C) The time-ig curve when the drain voltage was 0.6V and the gate voltage was 0V.

8 Figure S7: The Ids Vg curve of the transistor for simulation of Figure S7, S8, S9. The p-type transistor was set to Vth = 1 V and gm = 0.6 ms. PSpice (student version 9.1) was used for the simulation.

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10 Figure S8: Crosstalk evaluation when unselected data/scan lines are grounded and floating. (A) Concepts that describe how crosstalk is avoided by grounding the unselected data/scan lines. No voltage difference was applied to the OECTs on the unselected data lines, resulting in no current in these OECTs and no crosstalk (Is = I2). (B) Concepts that describe how crosstalk happens when the unselected data/scan lines are open. Voltage differences are applied to OECTs on the unselected data lines, resulting in currents in these OECTs and crosstalk (Is = I1 + I2). (C) Circuit schematic to evaluate crosstalk current when the unselected data/scan lines are grounded. (D) The simulation result of currents from each transistor in C. Except I4~6 (selected data line), the current was 0. I5 showed current fluctuation of 3 Hz, and was identical as Is. (E) Circuit schematic to evaluate crosstalk current when the unselected data/scan lines are open. (F) The simulation result of currents from each transistor in E. Currents were observed in I1,3,7,9 and I2,4,6,8 because the voltage difference is induced to the corresponding OECTs. Consequently, Is was mixed (I2 + I5 + I8).

11 Figure S9: The crosstalk simulation with different frequency inputs. Signals with frequencies of 2, 3, and 5 Hz were applied to 3 different OECTs (M21, M22, and M23 respectively), and the current in one of the scan lines was compared when unselected data/scan lines are grounded (A, B) and open (C,D). (A,C) Circuit schematics. (B,D) Simulation results of Is.

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13 Figure S10: Simulation data when the array was multiplexed. (A) Circuit schematic of the OECT array when it was multiplexed. The output signal of Is1, Is2, Is3 was shown in the bottom of circuit schematic, while the gate voltages (Vg13, Vg21, Vg22, Vg31, Vg32) of amplitude 100 mv were applied to the transistors (M13, M21, M22, M31,M32). (B) The output signal of Id1s1~Id3s3, which is separated by the timing of the applied pulse (V1, V2, V3), while the gate voltages (Vg13, Vg21, Vg22, Vg31,Vg32) of amplitude 100 mv were applied to the transistors (M13, M21, M22, M31,M32). The separated current was named by the number of scan lines (S1, S2, S3) and data lines (D1, D2, D3).

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15 Figure S11: Experimental evaluation of crosstalk in an OECT array. (A) Photographic image of the 3 3 OECT array. Scale bar: 1 mm (B) Magnified microscope view of a cell in the array. Scale bar: 100 μm (C) Circuit schematic for evaluating crosstalk in a data line. Different gate voltage inputs were applied to OECTs on the same data line. (D) Measured currents in each of the scan lines. Outputs with different frequencies were clearly recorded in each scan line. (E) Circuit schematic for evaluating crosstalk in a scan line. Different gate voltage inputs were applied to OECTs on the same scan line. (F) Measured currents when voltages in the data lines were switched. Signals with specific frequencies were obtained when voltage was applied to the corresponding data line.

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17 Figure S12: Simulation data when the array was multiplexed with high load resistance (RL). (A) Circuit schematic of the OECT array when it was multiplexed with 1 kω of RL. The gate voltages (Vg13, Vg21, Vg22, Vg31, Vg32) of amplitude 100 mv were applied to the transistors (M13, M21, M22, M31,M32) which is same as Fig S10(A). (B) The output signal of Vd1s1~Vd3s3, which is separated by the timing of the applied pulse (V1, V2, V3), while the gate voltages (Vg13, Vg21, Vg22, Vg31, Vg32) of the amplitude of 100 mv were applied to the transistors (M13, M21, M22, M31,M32). The separated current was named by the number of scan lines (S1, S2, S3) and data lines (D1, D2, D3).

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19 Figure S13: Simulation data when the array was multiplexed with 300Ω of wire resistance (Rw). (A) Circuit schematic of the OECT array when it was multiplexed with 300Ω of Rw. The gate voltages (Vg13, Vg21, Vg22, Vg31, Vg32) of amplitude 100 mv were applied to the transistors (M13, M21, M22, M31,M32) which is same as Fig S10(A). (B) The output signal of Vd1s1~Vd3s3, which is separated by the timing of the applied pulse (V1, V2, V3), while the gate voltages (Vg13, Vg21, Vg22, Vg31, Vg32) of the amplitude of 100 mv were applied to the transistors (M13, M21, M22, M31,M32). The separated current was named by the number of scan lines (S1, S2, S3) and data lines (D1, D2, D3).

20 Figure S14: Continuous current measurement of the transparent OECT (Vds = 0.6 V), which is directly stimulated by light through an optical fiber (with diameter 500 µm) on its channel at 5 Hz and a duration of 5 ms during an in-vivo experiment. It was conducted on the brain surface of living and dead optogenetic rats. The data was filtered at the frequency of more than 1 khz. The RMS was 0.02 µa. No clear light artefact was observed for the control data.

21 Figure S15: The site impedance of the transparent OECT (W/L = 70 µm/20 µm). The site impedance at 1 khz was 10 kω.