Variable Resolution, 10-Bit to 16-Bit R/D Converter with Reference Oscillator AD2S1210-EP

Transcription

1 Data Sheet Variable Resolution, -Bit to -Bit R/D Converter with Reference Oscillator ADS-EP FEATURES Complete monolithic resolver-to-digital converter 35 rps maximum tracking rate (-bit resolution) ±.5 arc minutes of accuracy -/-/-/-bit resolution, set by user Parallel and serial -bit to -bit data ports Absolute position and velocity outputs System fault detection Programmable fault detection thresholds Differential inputs Incremental encoder emulation Programmable sinusoidal oscillator on board Compatible with DSP and SPI interface standards 5 V supply with.3 V to 5 V logic interface ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard) Military temperature range: 55 C to +5 C Controlled manufacturing baseline assembly/test site fabrication site Product change notification Qualification data available on request APPLICATIONS DC and ac servo motor control Encoder emulation Electric power steering Electric vehicles Integrated starter generators/alternators Automotive motion sensing and control GENERAL DESCRIPTION The ADS-EP is a complete -bit to -bit resolution tracking resolver-to-digital converter, integrating an on-board programmable sinusoidal oscillator that provides sine wave excitation for resolvers. The converter accepts 3.5 V p-p ± 7% input signals, in the range of khz to khz on the sine and cosine inputs. A Type II servo loop is employed to track the inputs and convert the input sine and cosine information into a digital representation of the input angle and velocity. The maximum tracking rate is 35 rps. Full details about this enhanced product, including theory of operation, registers details, and applications information, are available in the ADS data sheet, which should be concluded in conjunction with this data sheet. EXCITATION OUTPUTS INPUTS FROM RESOLVER ENCODER EMULATION OUTPUTS FUNCTIONAL BLOCK DIAGRAM ADC ADC ENCODER EMULATION RESET REFERENCE OSCILLATOR (DAC) SYNTHETIC REFERENCE REFERENCE PINS VOLTAGE REFERENCE TYPE II TRACKING LOOP POSITION REGISTER VELOCITY REGISTER MULTIPLEXER DATA BUS OUTPUT DATA I/O CRYSTAL INTERNAL CLOCK GENERATOR ADS-EP Figure. FAULT DETECTION CONFIGURATION REGISTER FAULT DETECTION OUTPUTS DATA I/O PRODUCT HIGHLIGHTS. Ratiometric tracking conversion. The Type II tracking loop provides continuous output position data without conversion delay. It also provides noise immunity and tolerance of harmonic distortion on the reference and input signals.. System fault detection. A fault detection circuit can sense loss of resolver signals, out-of-range input signals, input signal mismatch, or loss of position tracking. The fault detection threshold levels can be individually programmed by the user for optimization within a particular application. 3. signal range. The sine and cosine inputs can accept differential input voltages of 3.5 V p-p ± 7%.. Programmable excitation frequency. Excitation frequency is easily programmable to a number of standard frequencies between khz and khz. 5. Triple format position data. Absolute -bit to -bit angular position data is accessed via either a -bit parallel port or a -wire serial interface. Incremental encoder emulation is in standard A-quad-B format with direction output available.. Digital velocity output. -bit to -bit signed digital velocity accessed via either a -bit parallel port or a -wire serial interface. 95- Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 ADS-EP TABLE OF CONTENTS Features... Enhanced Product Features... Applications... General Description... Functional Block Diagram... Product Highlights... Revision History... Specifications... 3 Data Sheet Timing Specifications...5 Absolute Maximum Ratings...7 ESD Caution...7 Pin Configuration and Function Descriptions... Typical Performance Characteristics... Outline Dimensions... Ordering Guide... REVISION HISTORY 5/ Rev. to Rev. A Changes to Features Section... Added Enhanced Product Features Section... Updated Outline Dimensions... Changes to Ordering Guide... / Revision : Initial Version Rev. A Page of

3 Data Sheet ADS-EP SPECIFICATIONS AVDD = DVDD = 5. V ± 5%, CLKIN =.9 MHz ± 5%, EXC, EXC frequency = khz to khz (-bit); khz to khz (-bit); 3 khz to khz (-bit); khz to khz (-bit); TA = TMIN to TMAX; unless otherwise noted. Table. Parameter Min Typ Max Unit Conditions/Comments SINE, COSINE INPUTS Voltage Amplitude V p-p Sinusoidal waveforms, differential SIN to SINLO, COS to COSLO Input Bias Current.5 μa VIN =. V p-p, CLKIN =.9 MHz Input Impedance 5 kω VIN =. V p-p, CLKIN =.9 MHz Phase Lock Range + Degrees Sine/cosine vs. EXC output, Control Register D3 = Common-Mode Rejection ± arc sec/v Hz to MHz, Control Register D = ANGULAR ACCURACY 3 Angular Accuracy ±.5 + LSB ±7 + LSB arc min Resolution,,, Bits No missing codes Linearity INL -Bit ± LSB -Bit ± LSB -Bit ± LSB -Bit ± LSB Linearity DNL ±.9 LSB Repeatability ± LSB VELOCITY OUTPUT Velocity Accuracy -Bit ± LSB Zero acceleration -Bit ± LSB Zero acceleration -Bit ± LSB Zero acceleration -Bit ± LSB Zero acceleration Resolution 5 9,, 3, 5 Bits DYNAMNIC PERFORMANCE Bandwidth -Bit Hz 9 5 Hz CLKIN =.9 MHz -Bit 9 Hz Hz CLKIN =.9 MHz -Bit 5 Hz Hz CLKIN =.9 MHz -Bit 35 Hz 5 75 Hz CLKIN =.9 MHz Tracking Rate -Bit 35 rps CLKIN =. MHz 5 CLKIN =.9 MHz -Bit 5 rps CLKIN =. MHz CLKIN =.9 MHz -Bit 5 rps CLKIN =. MHz 5 CLKIN =.9 MHz -Bit 5.5 rps CLKIN =. MHz 5 CLKIN =.9 MHz Acceleration Error -Bit 3 arc min At 5, rps, CLKIN =.9 MHz -Bit 3 arc min At, rps, CLKIN =.9 MHz -Bit 3 arc min At 5 rps, CLKIN =.9 MHz -Bit 3 arc min At 5 rps, CLKIN =.9 MHz Rev. A Page 3 of

4 ADS-EP Data Sheet Parameter Min Typ Max Unit Conditions/Comments Settling Time Step Input -Bit..9 ms To settle to within ± LSB, CLKIN =.9 MHz -Bit. 3.3 ms To settle to within ± LSB, CLKIN =.9 MHz -Bit.5 9. ms To settle to within ± LSB, CLKIN =.9 MHz -Bit 7.5 ms To settle to within ± LSB, CLKIN =.9 MHz Settling Time 79 Step Input -Bit.5. ms To settle to within ± LSB, CLKIN =.9 MHz -Bit.75. ms To settle to within ± LSB, CLKIN =.9 MHz -Bit.5 5. ms To settle to within ± LSB, CLKIN =.9 MHz -Bit 5 ms To settle to within ± LSB, CLKIN =.9 MHz EXC, EXC OUTPUTS Voltage V p-p Load ± μa, typical differential output (EXC to EXC) = 7. V p-p Center Voltage V Frequency khz EXC/EXC DC Mismatch 3 mv EXC/EXC AC Mismatch 3 mv THD 5 db First five harmonics VOLTAGE REFERENCE REFOUT V ±IOUT = μa Drift ppm/ C PSRR db CLKIN, XTALOUT VIL Voltage Input Low. V VIH Voltage Input High. V LOGIC INPUTS VIL Voltage Input Low. V VDRIVE =.7 V to 5.5 V.7 V VDRIVE =.3 V to.7 V VIH Voltage Input High. V VDRIVE =.7 V to 5.5 V.7 V VDRIVE =.3 V to.7 V IIL Low Level Input Current (Non- Pull-Up) μa IIL Low Level Input Current (Pull-Up) μa RES, RES, RD, WR/FSYNC, A, A, and RESET pins IIH High Level Input Current μa LOGIC OUTPUTS VOL Voltage Output Low. V VDRIVE =.3 V to 5.5 V VOH Voltage Output High. V VDRIVE =.7 V to 5.5 V. V VDRIVE =.3 V to.7 V IOZH High Level Three-State Leakage μa IOZL Low Level Three-State Leakage μa POWER REQUIREMENTS AVDD V DVDD V VDRIVE V POWER SUPPLY IAVDD ma IDVDD 35 ma IOVDD ma Temperature range is as follows: 55 C to +5 C. The voltages SIN, SINLO, COS, and COSLO, relative to AGND, must always be between.5 V and AVDD. V. 3 All specifications within the angular accuracy parameter are tested at constant velocity, that is, zero acceleration. The velocity accuracy specification includes velocity offset and dynamic ripple. 5 For example, when RES = and RES =, the position output has a resolution of bits. The velocity output has a resolution of bits with the MSB indicating the direction of rotation. In this example, with a CLKIN frequency of.9 MHz, the velocity LSB is. rps, that is, rps/( ). The clock frequency of the ADS-EP can be supplied with a crystal, an oscillator, or directly from a DSP/microprocessor digital output. When using a single-ended clock signal directly from the DSP/microprocessor, the XTALOUT pin should remain open circuit and the logic levels outlined under the logic inputs parameter in Table apply. Rev. A Page of

5 Data Sheet ADS-EP TIMING SPECIFICATIONS AVDD = DVDD = 5. V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table. Parameter Description Limit at TMIN, TMAX Unit fclkin Frequency of clock input. MHz min. MHz max tck Clock period (tck = /fclkin) 9 ns min 3 ns max t A and A setup time before RD/CS low ns min t Delay CS falling edge to WR/FSYNC rising edge ns min t3 Address/data setup time during a write cycle 3 ns min t Address/data hold time during a write cycle ns min t5 Delay WR/FSYNC rising edge to CS rising edge ns min t Delay CS rising edge to CS falling edge ns min t7 Delay between writing address and writing data tck + ns min t A and A hold time after WR/FSYNC rising edge ns min t9 Delay between successive write cycles tck + ns min t Delay between rising edge of WR/FSYNC and falling edge of RD ns min t Delay CS falling edge to RD falling edge ns min t Enable delay RD low to data valid in configuration mode VDRIVE =.5 V to 5.5 V 37 ns min VDRIVE =.7 V to 3. V 5 ns min VDRIVE =.3 V to.7 V 3 ns min t3 RD rising edge to CS rising edge ns min ta Disable delay RD high to data high-z ns min tb Disable delay CS high to data high-z ns min t5 Delay between rising edge of RD and falling edge of WR/FSYNC ns min t SAMPLE pulse width tck + ns min t7 Delay from SAMPLE before RD/CS low tck + ns min t Hold time RD before RD low ns min t9 Enable delay RD/CS low to data valid VDRIVE =.5 V to 5.5 V 7 ns min VDRIVE =.7 V to 3. V ns min VDRIVE =.3 V to.7 V 33 ns min t RD pulse width ns min t A and A set time to data valid when RD/CS low VDRIVE =.5 V to 5.5 V 3 ns min VDRIVE =.7 V to 3. V 37 ns min VDRIVE =.3 V to.7 V 9 ns min t Delay WR/FSYNC falling edge to SCLK rising edge 3 ns min t3 Delay WR/FSYNC falling edge to SDO release from high-z VDRIVE =.5 V to 5.5 V ns min VDRIVE =.7 V to 3. V ns min VDRIVE =.3 V to.7 V 9 ns min t Delay SCLK rising edge to DBx valid VDRIVE =.5 V to 5.5 V ns min VDRIVE =.7 V to 3. V ns min VDRIVE =.3 V to.7 V 3 ns min t5 SCLK high time. tsclk ns min t SCLK low time. tsclk ns min t7 SDI setup time prior to SCLK falling edge 3 ns min t SDI hold time after SCLK falling edge ns min Rev. A Page 5 of

6 ADS-EP Data Sheet Parameter Description Limit at TMIN, TMAX Unit t9 Delay WR/FSYNC rising edge to SDO high-z 5 ns min t3 Delay from SAMPLE before WR/FSYNC falling edge tck + ns ns min t3 Delay CS falling edge to WR/FSYNC falling edge in normal mode ns min t3 A and A setup time before WR/FSYNC falling edge ns min t33 A and A hold time after WR/FSYNC falling edge In normal mode, A =, A = / tck + 5 ns ns min In configuration mode, A =, A = tck + 5 ns ns min t3 Delay WR/FSYNC rising edge to WR/FSYNC falling edge ns min fsclk Frequency of SCLK input VDRIVE =.5 V to 5.5 V MHz VDRIVE =.7 V to 3. V 5 MHz VDRIVE =.3 V to.7 V 5 MHz Temperature range is as follows: 55 C to +5 C. A and A should remain constant for the duration of the serial readback. This may require clock periods to read back the -bit fault information in addition to the bits of position/velocity data. If the fault information is not required, A/A may be released after clock cycles. Rev. A Page of

7 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter AVDD to AGND, DGND DVDD to AGND, DGND VDRIVE to AGND, DGND AVDD to DVDD AGND to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Analog Output Voltage Swing Input Current to Any Pin Except Supplies Operating Temperature Range (Ambient) EP Grade Storage Temperature Range θja Thermal Impedance θjc Thermal Impedance RoHS-Compliant Temperature, Soldering Reflow ESD Rating.3 V to +7. V.3 V to +7. V.3 V to AVDD.3 V to +.3 V.3 V to +.3 V.3 V to AVDD +.3 V.3 V to VDRIVE +.3 V.3 V to VDRIVE +.3 V.3 V to AVDD +.3 V ± ma 55 C to +5 C 5 C to +5 C 5 C/W 5 C/W ( 5/+) o C kv HBM ADS-EP Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Transient currents of up to ma do not cause latch-up. JEDEC SP standard board. Rev. A Page 7 of

8 ADS-EP Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RES REFOUT REFBYP COS COSLO AV DD SINLO SIN AGND EXC EXC A RES CS PIN 3 A 35 DOS RD 3 3 LOT WR/FSYNC 33 RESET DGND DV DD CLKIN 5 7 ADS-EP TOP VIEW (Not to Scale) 3 DIR 3 NM 3 B XTALOUT 9 A SOE 9 DB SAMPLE 7 DB DB5/SDO DB DB/SDI 5 DB DB3/SCLK DB DB DB DB9 V DRIVE DGND DB DB7 DB DB5 DB 95- Figure. Pin Configuration Table. Pin Function Descriptions Pin No. Mnemonic Description RES Resolution Select. Logic input. RES in conjunction with RES allows the resolution of the ADS-EP to be programmed. CS Chip Select. Active low logic input. The device is enabled when CS is held low. 3 RD Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and output enable for the parallel data outputs, DB5 to DB. The output buffer is enabled when CS and RD are held low. When the SOE pin is low, the RD pin should be held high. WR/FSYNC Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and input enable for the parallel data inputs, DB7 to DB. The input buffer is enabled when CS and WR/FSYNC are held low. When the SOE pin is low, the WR/FSYNC pin acts as a frame synchronization signal and enable for the serial data bus. 5, 9 DGND Digital Ground. These pins are ground reference points for digital circuitry on the ADS-EP. Refer all digital input signals to this DGND voltage. Both of these pins can be connected to the AGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than.3 V apart, even on a transient basis. DVDD Digital Supply Voltage,.75 V to 5.5 V. This is the supply voltage for all digital circuitry on the ADS-EP. The AVDD and DVDD voltages should ideally be at the same potential and must not be more than.3 V apart, even on a transient basis. 7 CLKIN Clock Input. A crystal or oscillator can be used at the CLKIN and XTALOUT pins to supply the required clock frequency of the ADS-EP. Alternatively, a single-ended clock can be applied to the CLKIN pin. The input frequency of the ADS-EP is specified from. MHz to. MHz. XTALOUT Crystal Output. When using a crystal or oscillator to supply the clock frequency to the ADS-EP, apply the crystal across the CLKIN and XTALOUT pins. When using a single-ended clock source, the XTALOUT pin should be considered a no connect pin. 9 SOE Serial Output Enable. Logic input. This pin enables either the parallel or serial interface. The serial interface is selected by holding the SOE pin low, and the parallel interface is selected by holding the SOE pin high. SAMPLE Sample Result. Logic input. Data is transferred from the position and velocity integrators to the position and velocity registers after a high-to-low transition on the SAMPLE signal. The fault register is also updated after a high-to-low transition on the SAMPLE signal. DB5/SDO Data Bit 5/Serial Data Output Bus. When the SOE pin is high, this pin acts as DB5, a three-state data output pin controlled by CS and RD. When the SOE pin is low, this pin acts as SDO, the serial data output bus controlled by CS and WR/FSYNC. The bits are clocked out on the rising edge of SCLK. DB/SDI Data Bit /Serial Data Input Bus. When the SOE pin is high, this pin acts as DB, a three-state data output pin controlled by CS and RD. When the SOE pin is low, this pin acts as SDI, the serial data input bus controlled by CS and WR/FSYNC. The bits are clocked in on the falling edge of SCLK. Rev. A Page of

9 Data Sheet ADS-EP Pin No. Mnemonic Description 3 DB3/SCLK Data Bit 3/Serial Clock. In parallel mode, this pin acts as DB3, a three-state data output pin controlled by CS and RD. In serial mode, this pin acts as the serial clock input. to DB to Data Bit to Data Bit 9. Three-state data output pins controlled by CS and RD. 7 DB9 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. Decouple this pin to DGND. The voltage range on this pin is.3 V to 5.5 V and may be different from the voltage range at AVDD and DVDD but should never exceed either by more than.3 V. DB Data Bit. Three-state data output pin controlled by CS and RD. to DB7 to DB Data Bit 7 to Data Bit. Three-state data input/output pins controlled by CS, RD, and WR/FSYNC. 9 A Incremental Encoder Emulation Output A. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. 3 B Incremental Encoder Emulation Output B. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. 3 NM North Marker Incremental Encoder Emulation Output. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. 3 DIR Direction. Logic output. This output is used in conjunction with the incremental encoder emulation outputs. The DIR output indicates the direction of the input rotation and is high for increasing angular rotation. 33 RESET Reset. Logic input. The ADS-EP requires an external reset signal to hold the RESET input low until VDD is within the specified operating range of.75 V to 5.5 V. 3 LOT Loss of Tracking. Logic output. Loss of tracking (LOT) is indicated by a logic low on the LOT pin and is not latched. 35 DOS Degradation of Signal. Logic output. Degradation of signal (DOS) is detected when either resolver input (sine or cosine) exceeds the specified DOS sine/cosine threshold or when an amplitude mismatch occurs between the sine and cosine input voltages. DOS is indicated by a logic low on the DOS pin. 3 A Mode Select. Logic input. A in conjunction with A allows the mode of the ADS-EP to be selected. 37 A Mode Select. Logic input. A in conjunction with A allows the mode of the ADS-EP to be selected. 3 EXC Excitation Frequency. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the excitation frequency register. 39 EXC Excitation Frequency Complement. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the excitation frequency register. AGND Analog Ground. This pin is the ground reference points for analog circuitry on the ADS-EP. Refer all analog input signals and any external reference signal to this AGND voltage. Connect the AGND pin to the AGND plane of a system. The AGND and DGND voltages should ideally be at the same potential and must not be more than.3 V apart, even on a transient basis. SIN Positive Analog Input of Differential SIN/SINLO Pair. The input range is.3 V p-p to. V p-p. SINLO Negative Analog Input of Differential SIN/SINLO Pair. The input range is.3 V p-p to. V p-p. 3 AVDD Analog Supply Voltage,.75 V to 5.5 V. This pin is the supply voltage for all analog circuitry on the ADS-EP. The AVDD and DVDD voltages ideally should be at the same potential and must not be more than.3 V apart, even on a transient basis. COSLO Negative Analog Input of Differential COS/COSLO Pair. The input range is.3 V p-p to. V p-p. 5 COS Positive Analog Input of Differential COS/COSLO Pair. The input range is.3 V p-p to. V p-p. REFBYP Reference Bypass. Connect reference decoupling capacitors at this pin. Typical recommended values are μf and. μf. 7 REFOUT Voltage Reference Output. RES Resolution Select. Logic input. RES in conjunction with RES allows the resolution of the ADS-EP to be programmed. Rev. A Page 9 of

10 ADS-EP Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA = 5 C, AVDD = DVDD = VDRIVE = 5 V, SIN/SINLO = 3.5 V p-p, COS/COSLO = 3.5 V p-p, CLKIN =.9 MHz, unless otherwise noted. HITS PER CODE HITS PER CODE CODE Figure 3. Typical -Bit Angular Accuracy Histogram Of Codes,, Samples CODE Figure. Typical -Bit Angular Accuracy Histogram of Codes,, Samples, Hysteresis Disabled 95- HITS PER CODE HITS PER CODE CODE Figure. Typical -Bit Angular Accuracy Histogram of Codes,, Samples, Hysteresis Disabled CODES Figure 7. Typical -Bit Angular Accuracy Histogram of Codes,, Samples, Hysteresis Enabled 95-7 HITS PER CODE HITS PER CODE CODES Figure 5. Typical -Bit Angular Accuracy Histogram of Codes,, Samples, Hysteresis Enabled CODE Figure. Typical -Bit Angular Accuracy Histogram of Codes,, Samples, Hysteresis Disabled 95- Rev. A Page of

11 Data Sheet ADS-EP HITS PER CODE ANGLE (Degrees) ANGLE (Degrees) CODES Figure 9. Typical -Bit Angular Accuracy Histogram of Codes,, Samples, Hysteresis Enabled 3 3 TIME (ms) Figure. Typical -Bit Step Response TIME (ms) Figure. Typical -Bit Step Response ANGLE (Degrees) ANGLE (Degrees) ANGLE (Degrees) TIME (ms) Figure. Typical -Bit Step Response TIME (ms) Figure 3. Typical -Bit Step Response TIME (ms) Figure. Typical -Bit 79 Step Response Rev. A Page of

12 ADS-EP Data Sheet 5 -BIT 5 ANGLE (Degrees) MAGNITUDE (db) BIT -BIT -BIT TIME (ms) Figure 5. Typical -Bit 79 Step Response k k k FREQUENCY (Hz) Figure. Typical System Magnitude Response BIT ANGLE (Degrees) PHASE (db) -BIT -BIT -BIT TIME (ms) Figure. Typical -Bit 79 Step Response 95- k k k FREQUENCY (Hz) 9 Figure 9. Typical System Phase Response 95- ANGLE (Degrees) TIME (ms) Figure 7. Typical -Bit 79 Step Response 95- TRACKING ERROR (Degrees) ACCELERATION (rps ) Figure. Typical -Bit Tracking Error vs. Acceleration 95- Rev. A Page of

13 Data Sheet ADS-EP 9 9 TRACKING ERROR (Degrees) TRACKING ERROR (Degrees) ACCELERATION (rps ) Figure. Typical -Bit Tracking Error vs. Acceleration 95- ACCELERATION (rps ) Figure 3. Typical -Bit Tracking Error vs. Acceleration TRACKING ERROR (Degrees) ACCELERATION (rps ) Figure. Typical -Bit Tracking Error vs. Acceleration 95- Rev. A Page 3 of

14 ADS-EP Data Sheet OUTLINE DIMENSIONS PKG VIEW A ROTATED 9 CCW REF SEATING PLANE MAX COPLANARITY SIDE VIEW. MAX VIEW A COMPLIANT TO JEDEC STANDARDS MS--BBC SQ. TOP VIEW.5 BSC Figure. -Lead Low Profile Quad Flat Package [LQFP] (ST-) Dimensions shown in millimeters SQ. ORDERING GUIDE Model Temperature Range Package Description Package Option ADSSST-EP-RL7 55 C to +5 C -Lead LQFP ST- ADSSSTZ-EPRL7 55 C to +5 C -Lead LQFP ST- Z = RoHS Compliant Part -7--A Rev. A Page of

15 Data Sheet ADS-EP NOTES Rev. A Page 5 of

16 ADS-EP Data Sheet NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D95--5/(A) Rev. A Page of