A Highly-efficacious Self-compensation Means to Reduce Variations due to Bending

Transcription

1 A Highly-efficacious Self-compensation Means to Reduce Variations due to Bending

2 Outline Need for Bending Variations of TFTs, Passives and Circuits when bent Mitigation of variations due to bending Reported Means Proposed Self-Compensation Means NTU Printed Electronics Fully-Additive, All-Air, Low Temp Process Process Development Kit Co-design: Materials, Printing and Circuit Design 2

3 Need for Bending: Substrate Flexibility J. Zhou, T. Ge, and J. S. Chang, Printed Electronics: Effects of Bending and a Self-Compensation Means, IEEE Trans. Circuits Syst, I, 2017 J. Chang, A. F. Facchetti, and R. Reuss, A Circuits and Systems Perspective of Organic/Printed Electronics: Review, Challenges, and Contemporary and Emerging Design Approaches, IEEE Journal on Emerging and Selected Topics in Circuits and Systems,

4 What are the variations when TFTs are bent? J. Zhou, T. Ge, and J. S. Chang, Printed Electronics: Effects of Bending and a Self-Compensation Means, IEEE Trans. Circuits Syst, I, 2017 J. Chang, A. F. Facchetti, and R. Reuss, A Circuits and Systems Perspective of Organic/Printed Electronics: Review, Challenges, and Contemporary and Emerging Design Approaches, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2017 J. S. Chang, T. Ge, T. Lin and J. Zhou, PE: Effects Of Bending And A Self- Compensation Means, Singapore Provisional Patent Q, Jul

5 Major Variations when TFTs are Bent Printed Transistors: Bending w/o Compensation Bent Concavely Flat Bent Convexly Bending Radius = 1.1cm, Variations are 40% to 115% 5

6 What are the variations when Passives are Bent? Printed Capacitor Printed Resistor Up to 3% variations Up to 14% variations 6

7 What are the variations when Circuits are Bent? Frequency Variations 46.2% Gain Bandwidth Variations 63.6% 7

8 Reported Means to Reduce Variations due to Bending Deposit overlay top layer with same substrate thickness Use very thin substrate Overlay top layer Shortcomings Overly frangible Difficult to handle Limited applications M. Kaltenbrunner, et al. An ultra-lightweight design for imperceptible plastic electronics Nature, 2013 Shortcomings Neural stress line not necessarily at mid of thickened substrate Overall substrate may be too thick Top overlay layer and substrate may have different properties Limited applications T. Sekitani, Flexible organic transistors and circuits with extreme bending stability, Nature Materials,

9 Proposed Novel Compensation Method (Patent Pending) Conventional Proposed J. Zhou, T. Ge, and J. S. Chang, Printed Electronics: Effects of Bending and a Self-Compensation Means, IEEE Trans. Circuits Syst, I, 2017 J. S. Chang, T. Ge, T. Lin and J. Zhou, PE: Effects Of Bending And A Self-Compensation Means, Singapore Provisional Patent Q, Jul

10 Our Novel Compensation Method (Patent Pending) to mitigate Variations due to Bending J. Zhou, T. Ge, and J. S. Chang, Printed Electronics: Effects of Bending and a Self-Compensation Means, IEEE Trans. Circuits Syst, I,

11 Variations of TFTs: Bending with Compensation Flat Compensated Compensated Flat Bending Radius = 1cm, Variations now reduced to 2% to 20% (from 40% to 115%) ~5.7x reduction 11

12 Passives: Bending w/o and with Compensation Printed Capacitor Printed Resistor W/o compensation: 3.00% variations With compensation: 0.27% variations 11x reduction W/o compensation: 14.0% variations With compensation: 1.8% variations 8x reduction 12

13 Printed Circuits: Bending w/o and with Compensation 8x W/o compensation: 46.2% With compensation: 5.8% W/o compensation: 63.6% 6x With compensation: 10.7% 13

14 Variations of TFTs, Passives & Circuits due to Bending: Conventional vs. Proposed Compensation J. Zhou, T. Ge, and J. S. Chang, Printed Electronics: Effects of Bending and a Self-Compensation Means, IEEE Trans. Circuits Syst, I, 2017 J. S. Chang, T. Ge, T. Lin and J. Zhou, PE: Effects Of Bending And A Self-Compensation Means, Singapore Provisional Patent Q, Jul

15 NTU s Printed Electronics Process and Design Full-fledged Electronics Green, Low-Cost, On-Demand, Scalable Process Fully-Additive, All-Air, Air Stable, Low Temp, Low Process Variations One of the few, if not only, Fully-Additive Printing Process capable of printing full-fledged circuits and systems Novel Compensation Method to mitigate effects of Bending Process Development Kit for EDA tools for Printed Electronics Esoteric Circuit Design and Co-design with Materials and Printing J. Chang, et al., Organic Electronics: Materials, Physics, Chemistry and Applications, pp , Mar

16 NTU s Printed Electronics Process and Design Designability Process Development Kit (PDK) includes: New TFT models to account for - carrier mobility due to layout, - leakage current, - cut-off region, and - parasitics Printing Process Variations Variations due to Bending Precise Prediction of Circuit Performance Prediction of Aging Monte Carlo Simulations T. Ge, and J. Zhou, An Open Platform for Fully-Additive Printed Electronics, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Mar

17 NTU s Co-Design: Materials, Printing and Circuit Design Analog Circuit Design Designs not applicable to silicon Unique positive-cum-negative feedback Very high gain without compromising gain bandwidth Common-mode immunity to Process Variations Digital Circuit Design Clockless design methodologies Two proposed design methodologies immune to process variations Proposed PCSL and SAHB: >6x improvement over reported designs for Power-Speed-Area Figure-of-Merit Synchronous-Logic Clocking timing assumptions required; Operational robustness is challenging Asynchronous-Logic Digital Logic Design Approaches/Signalling Protocols Delay-Insensitive (DI) Quasi-Delay-Insensitive (QDI)/ Speed-Independent (SI) Matched-Delay (MD) Asynchronous-Logic Approaches/Protocols Impractical Timing assumptions required; Operational robustness is challenging Dynamic-Logic Static-Logic Pass Transistor- Logic Logic Families Not robust for PE Not robust for PE J. Chang, et al., Fully Printed Elect on Flexible Substrates: high gain amplifiers and DAC, Organic Electronics: Materials, Physics, Chem and App, pp , Mar 2014 J. Chang, et al., US Patent No J. Chang, et al., US Patent No Delay- Insensitive- Minterm-Syntheis (DIMS) NULL- Convention-Logic (NCL) Block-level async QDI approaches Pre-Charged-Static- Logic (PCSL) Direct- Static-Logic- Implementation (DSLI) Sense-Amplifier- Half-Buffer (SAHB) Gate-level async QDI approach Static QDI Logic Design Styles 17

18 March 2017 Special Issue 18

19 Conclusions Bending induces severe variations intractable? Quantified: Variations of TFTs, Passives and Circuits when bent Proposed Self-Compensation Means: Mitigation of variations due to bending by up to 108x better NTU Fully-Additive, All-Air, Low Temp Printing Process Process Development Kit Co-design and co-optimization: Materials, Printing and Circuit Design Novel and Esoteric Circuit Design 19