Characterization of Copper-doped Silicon Dioxide. Programmable Metallization Cells. Sarath Chandran Puthen Thermadam

Transcription

1 Characterization of Copper-doped Silicon Dioxide Programmable Metallization Cells by Sarath Chandran Puthen Thermadam A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy Approved January 2011 by the Graduate Supervisory Committee: Michael Kozicki, Chair Rodolfo Diaz Dieter Schroder Terry Alford ARIZONA STATE UNIVERSITY May 2011

2 ABSTRACT follow Programmable Metallization Cell (PMC) is a resistance-switching device based on migration of nanoscale quantities of cations in a solid electrolyte and formation of a conducting electrodeposit by the reductions of these cations. This dissertation presents electrical characterization results on Cu-SiO 2 based PMC devices, which due to the nature of materials can be easily integrated into the current Complimentary metal oxide semiconductor (CMOS) process line. Device structures representing individual memory cells based on W bottom electrode and n-type Si bottom electrode were fabricated for characterization. For the W bottom electrode based devices, switching was observed for voltages in the range of 500mV and current value as low as 100 na showing the electrochemical nature and low power potential. The ON state showed a direct dependence on the programming current, showing the possibility of multi-bit storage in a single cell. Room temperature retention was demonstrated in excess of 10 5 seconds and endurance to approximately 10 7 cycles. Switching was observed for microsecond duration 3 V amplitude pulses. Material characterization results from Raman, X-ray diffraction, Rutherford backscattering and Secondary-ion mass spectroscopy analysis shows the influence of processing conditions on the Cu concentration within the film and also the presence of Cu as free atoms. The results seemed to indicate stress-induced void formation in the SiO 2 matrix as the driving mechanism for Cu diffusion into the SiO 2 film. Cu/SiO 2 /nsi based PMC devices were characterized and were shown to have inherent isolation characteristics, proving the feasibility of such a structure for a passive array. The inherent isolation property simplifies fabrication by avoiding the need for a separate diode element in an array. The isolation characteristics were studied mainly in terms of the leakage current. The nature of the diode interface was further studied by extracting a barrier potential which shows it can be approximated to a Cu-nSi metal semiconductor Schottky diode. i

3 To my parents, friends and all my teachers who taught me ii

4 ACKNOWLEDGEMENT follow First of all, I would like to thank my advisor Prof. Michael N. Kozicki with whom I have been working for almost five years now. I was fortunate to get the chance to do a PhD under him. He genuinely cares for his students and has supported me through all the ups and downs. I thank Prof. Dieter K. Schroder, who through his excellent courses was instrumental in initially creating a spark of interest in me to pursue studies in the area of semiconductor devices. I was fortunate to be able to take five courses under him in the last five years and have to say that he is by far one of the best teachers I have met in my life so far. His patience towards students and the simplicity and clarity of the concepts that he explains are few of the qualities I would like to imbibe in me moving forward in life, and more so if I am ever to pursue a teaching career. I was also fortunate to collaborate with him in the last one year for my research and he was of great help in working towards publishing some of my key results. I thank Muralikrishnan Balakrishnan, my mentor in the group during the early days of my research career. Throughout the last five years, he has always been there just a phone call away to offer me any advice when I need it. I thank Christina Schindler, a visiting PhD student from University of Aachen-Germany in 2006, with whom I was fortunate to collaborate for a few semesters and working with her in the early stage of my research career gave me a good direction to proceed. I thank Prof. Maria Mitkova of Boise State University, with whom I collaborated for a part of my research and whose profound knowledge of material properties of thin films helped my analyze and publish some of my results. I thank Prof. Terry Alford and his student Shekhar Bhagath (currently a Senior Yield Engineer at Intel, Oregon) for running the X-ray Diffraction experiments and helping me analyze it. I thank my group mates Deepak, Sunil and Ming Han for their occasional inputs and willingness to share some work load when there was a need. I thank the staff at the Center for Solid State Engineering and Research (CSSER) and Center for Solid State Sciences (CSSS) for their technical iii

5 support. I would like to thank all the teachers who taught me right from my kindergarten days. Its the knowledge they passed on to me and the advices they gave me that helped me reach at this stage of my academic career. Finally, I would like to thank all my friends and family. Friends, for giving me a life beyond the academics and filling it with fun and energy. Family, for supporting me all these years and being there with me for all my decisions. iv

6 TABLE OF CONTENTS Page TABLE OF CONTENTS v LIST OF FIGURES vii CHAPTER Introduction Scaling Resistance-swtiching memory Programmable Metallization Cell Crossbar architecture Metal-semiconductor interfaces Barrier formation Current transport mechanism Breakdown mechanisms Report Outline Device characterization Device fabrication Substrate preparation Bottom electrode (Cathode) definition Top electrode (Anode) definition PMC stack depostion Experimental setup Voltage sweep measurements Data retention measurements Speed Measurements Endurance Cycling Results v

7 CHAPTER Page

8 LIST OF FIGURES Figure Page 1.1 (a) Transistor/chip and (b) Memory cell/logic gate size trend over the years[1] Schematic of the PMC cell showing electrodeposition process Generalized cross-point structure with one bit of array consisting of a memory element and a switch element [2] (a). SEM micrograph of two layers of memory cells in a passive crossbar array. (b). TEM cross-section showing the integration of the crossbar array[3] Band diagram of a metal-semiconductor interface when a). they are separated. b). after the interface is formed. c). a positive polarity is applied on the metal. d). a negative polarity is applied on the metal Band diagram showing Thermionic field emission and Field emission in (a). forward biased and (b). reverse biased Schottky barrier. [4] Band diagram showing a). avalanche breakdown by impact ionization and b). zener breakdown by band to band tunneling in pn junctions[5] Schematic of a PMC test device layout. Diameter, D defines the electrolyte area that contacts the bottom electrode forming the active device area Schematic cross section of the 8 inch wafer obtained from Qimonda AG, Munich, Germany, used for PMC fabrication. Tungsten layer acts as the bottom electrode and vias are already etched in the wafer PMC fabrication process steps Top view of the wafer, a single die and a single via PMC test structure Photograph of the probe station setup used for electrical testing of the PMC devices Schematic of the circuit used for PMC speed testing measurements vii

9 Figure Page

10 Figure Page

11 Figure Page

12 Figure Page

13 Chapter 1 Introduction 1.1 Scaling For more than four decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in its products. From the consumer s point of view, improvements were seen in cost (more functionality at same or lower cost), portability (smaller and lighter products but same or more functionality), speed (faster microprocessors), power requirements (better battery life for mobile phones, portable media players, laptops etc.). This resulted principally from the industry s ability to exponentially decrease the minimum feature sizes used to fabricate integrated circuits, with an added but more significant benefit of decreasing cost-per-function. This is the process of scaling. It was initially formulated as a simple prediction by Gordon Moore in 1965[8] and due to the powerful economic cycle, of investment and profits leading to more investments. that it unleashed, it came to be known as the Moore s law. It predicted that the number of devices that can be integrated on a chip of fixed area would double every 12 months (later amended to months). A more significant but less quoted part of the prediction was the decrease in cost with more functionalities in the same area, which is what drives the economy. The process of scaling was more formally addressed by Dennard s law[9], calling for the coordinated miniaturization of a small set of device parameters, which together dictates the overall performance. The same factors of cost reduction and more storage capacity in same or less area has driven the non-volatile memory business for the last two decades. The lower cost lead to new market and applications yielding more revenue and thus driving the economic cycle. Non-volatile memory is now ubiquitous in cell phones, music players, USB drives, embedded memory chips etc. The non-volatile memory (flash memory) price dropped from about $80,000/GB in 1987 (for a 256Kb unit) to less than $1.50/GB in late 2008 (for a 16 Gb Multi-bit unit). The economic drive boost obtained from the 1

14 (a) (b) Figure 1.1: (a) Transistor/chip and (b) Memory cell/logic gate size trend over the years[1]. popularity of mobile applications has elevated the NAND flash memory to status of the technology/cost-reduction driver, a position held by DRAM until few years ago. Fig. 1.1 shows the transition of the technology driver status in terms of the functionality and cell-size clearly. This relentless pace of scaling in the area of non-volatile memories 2

15 was made possible by innovations along multiple fronts starting with better lithographic capabilities which defines each new technology node. On the device front, the advent of NAND flash memory for high volume and less critical applications, self-aligned technologies for source and floating-gate, wafer-size increase from 150 mm to 300 mm, introduction of multi-level (multi-bit) cell technologies were some of the innovations which carried the flash memory so far into the technology landscape with 50 nm NAND flash being in full production in These innovations are discussed in more detail in [10]. Similar challenges, now in a more critical scale due to device dimensions involved, is present for scaling into the sub-40 nm node. On the lithography front, the conventional lithography with immersion technology is affected by a manufacturing limit at approximately 40 nm. New techniques such as self-aligned double patterning have been reported with ability to define features to nearly 20 nm (demonstrated for 30 nm)[11]. The true limiters for cell-size reduction involves electrical and reliability requirements on the device front. NOR flash memory, due to its reliance on creation of hot carriers in the channel for programming, is limited by the gate-length which can withstand the drain-source voltage (greater than 4 V) required for creating the hot carriers energetic enough to cross the 3.2 ev Si-SiO 2 barrier. Three-dimensional cell structures are one proposed way to address the gate length scaling constraints. Due to the extension of the channel length constraint into the Z direction, further area scaling could be possible while maintaining the total channel length required. Silicon fin structure and hemi-cylindrical transistor structures (HCFET) have been reported [11]. The scaling of the inter-poly dielectric(ipd) has neared its physical limits due to reliability concerns on reducing the leakage from the floating gate. However, with the scaling of the other dimensions in the device, scaling of the IPD is required to maintain the same voltage coupling ratio between the two gates. One potential solution is use of high-k dielectrics, however one additional constraint of using high-k dielectrics for memory cell is optimizing for even lesser leakage current than transistor gates with high-k di- 3

16 electric. On the other hand, the tunnel oxide seems to have already hit the scaling limit at 6-7 nm due to similar reliability concerns. One potential scaling solution proposal involves the use of composite films with different barrier heights to give desired tunneling properties[12]. Another scaling limit involves the interference between the cells due to capacitive coupling, as dimension become smaller. The interference increases with scaling and is expected to approach 50% of the total V t shift at the 20 nm node[13]. One promising approach being proposed to solve this is replacement of the conductive polysilicon floating gate with insulating gate with charge traps or conducting islands which is expected to reduce the capacitive coupling between adjacent cells[14]. This could also prevent charge leakage to some extend due to any localized defect in the tunnel oxide or IPD. This is not however applicable for NOR flash because NOR flash memory relies on a conducting floating gate to redistribute the charge injected in the drain area. Another concern towards using such charge trap structures is the constraint of error margin for distinguishing between different stored states. Smaller device dimensions due to scaling has resulted in decrease in the cell capacitances and hence the charge stored. The number of stored electrons is approximately 500 for NAND flash in 45 nm node[13]. In a 2-bit multi-level cell NAND, that would correspond to approximately 100 electrons for each state. With localized charge trap structures, this number for each state could reduce further. All the challenges described above in further scaling the conventional floating gate memories into the sub-40 nm regime opened up possibilities and opportunities for new memory technologies. It is possible that in spite of known solutions to any current issue, the additional investment that it demands may not justify going for it unless there is a corresponding expansion in revenue generation by finding new markets. This is another reason for the industry s widespread interest in emerging low-cost alternative memory technologies. 4

17 1.2 Resistance-swtiching memory Resistance-switching memory devices, are generally known as resistance switching RAM, or RRAM. It basically involves, an electrically stimulated change in resistance of a metal-insulator-metal (MIM) two terminal structure. A high resistance state and a low resistance state are the two states corresponding to two bits in a memory cell. A wide variety of materials have been experimentally shown to show hysteretic resistance switching, in a MIM structure. The materials range from binary oxides like NiO[15], Nb 2 O 5 [16], Ta 2 O 5 [17], TiO 2 [18] and WO 3 [19]; multinary oxides like the perovskite-type oxides such as (Pr,Ca)MnO 3 [20] and SrTiO 3 [21]; chalcogenides like GeSe, GeS[22, 23] and Cu 2 S[24]; and polymeric or inorganic insulator films. The metal in the MIM structure is usually Cu, Ag or Pt. However, the structure need not be always symmetrical and one of the metals might be more electrochemically inert like W or even doped Si. The switching mechanism is in general found to be dominated by any one of the following three effects: 1. Thermal effect - The switching here is is initiated by a voltage-induced dielectric breakdown in which the material in a discharge conducting filament is modified by Joule heating. A weak conductive filament with a controlled resistance is formed by setting a compliance current. Based on the switching material this filament could be electrode metal transported into the insulator, carbon from residual organics or decomposed insulator material such as sub-oxides. During the the reset transition this conductive filament is again disrupted thermally because of high power density of the order of W cm 3 generated locally. This mechanism is also referred to as the fuse-antifuse type. NiO is one candidate switching material which falls in this category[25]. 2. Electronic effect - The models developed to explain this effect varies with ma- 5

18 terials. According to charge-trap model[26], charges are injected by Fowler- Nordheim tunnelling at high electric fields and subsequently trapped at sites such as defects or metal nanoparticles in the insulator. This modifies the electrostatic barrier character of the MIM structure and its resistance. Some examples are gold nanoclusters incorporated in either polymeric or inorganic insulator films[27]. In perovskite-type oxides an insulator-metal transition model is proposed, in which electronic charge injection acts like doping to induce the transition from insulator to metal[21]. 3. Ionic effect - This effect is a combination of ionic transport in the insulator and electrochemical redox reactions. Devices showing this effect falls into two classes : the ones showing switching due to cation migration and the ones showing switching due to anionic migration. An example for anionic migration is MIM structure based on transition metal oxides, such as TiO 2. This involves creation of an oxygen deficient region by an electroforming process and migration of these deficiencies of vacancies towards the top electrode (anode). The transition metal cations accommodate for this vacancy by a reduction reaction involving trapping of electrons from the cathode. This reaction is believed to turn the oxide into a metallically conducting phase which grows towards the anode finally forming a conducting low resistance path. Filamentary switching has been established in these since switching in general has been found to be independent of the via/plug size of the device and added evidence was obtained from conductive AFM studies. Even then this class of ion migration device is comparatively less well understood in terms of the microscopic details of ion transport, defect structure, electronic charge transport properties of the conductive channels etc. The more well understood cationic migration based switching is seen in the chalcogenide based devices and also oxides like WO 3. It is explained in detail in the next section and is believed to be the switching mechanism present in the 6

19 materials being studied in this report. 1.3 Programmable Metallization Cell Programmable Metallization Cell (PMC) is the term used in general to refer to the RRAM devices with switching based on cation migration. It is also known as conductivebridging RAM (CBRAM). The successful results reported so far in these switching devices involves the use of chalcogenides like germanium selenide or germanium sulfide as the solid electrolyte [28], [23]. These devices consist of the solid electrolyte sandwiched between an anode which is an oxidizable metal like silver (Ag) or copper (Cu) and a cathode which is usually an comparatively inert metal like tungsten (W). Before the deposition of the top anode electrode, the solid electrolyte is doped with Ag or Cu by the process of photodissolution [29]. Photodissolution converts the binary base glass which is germanium selenide or germanium sulfide, into a uniform ternary electrolyte by adding or diffusing Ag into it[30], [31]. It has been established that in the case of Ag-doped germanium selenide and germanium sulfide materials, the resulting ternary takes the form of a continuous glassy Ge-rich backbone and a dispersed nanoscale Agrich superionic phase[32, 33, 34]. The same nano-morphology is assumed to exist in the case of Cu-doped films. In these devices when a positive voltage in the range of few hundred mv is applied on the anode and the cathode is grounded, the electric field in the electrolyte drifts the Ag ions existing in the Ag-rich superionic phases towards the cathode. The electron current from the cathode reduces these Ag ions and thus a Ag electrodeposit is formed at the cathode. This electrodeposit grows into the electrolyte as more and more Ag ions are reduced. To maintain the charge neutrality in the electrolyte, Ag ions are replenished in the electrolyte by the oxidation of Ag atoms in the anode. Once the electrodeposit reaches the anode, the device switches into a low resistance state. This switching can be achieved in few tens of nanoseconds depending on the thickness of the film[22]. This fast switching is achieved due to a coordinated motion of ions in the 7

20 electrolyte. An ion from the anode doesn t have to diffuse all the way till the cathode for electrodeposition. The ion existing in the superionic phase which is closest to the cathode, diffuses under the influence of the electric field towards the cathode and gets reduced. The other ions lying upstream will move by a step to fill the vacancy until the last vacancy near the anode is filled by an incoming ion from the anode. The electrodeposition process is reversible by changing the polarity of the applied bias. If the electrodeposit is made positive with respect to the original oxidizable electrode, it becomes the new anode and will dissolve via oxidation. These oxidized ions gets electrodeposited back onto the place on the top electrode from where the excess metal for electrodepostion came in the first place. The original electrodeposition under positive voltage will have left a low density region at this electrode and this region will favor redeposition without extended growth back into the electrolyte. Once the electrodeposit has been completely dissolved, device switches back to high resistance. A schematic of the switching process is shown in Fig The process shown in the figure can be briefly explained as : (a). No bias. (b). Forward bias: A very small bias rapidly injects excess ions into the electrolyte which gets reduced by the electron current and forms a stable electrically neutral deposit in the electrolyte. (c). The electrodeposition stops when a conductive link is formed and the voltage drop across the deposit falls to the minimum drop required to sustain the electrodeposit. (d). Reverse Bias: A very small negative bias can dissolve the electrodeposit via oxidation and remove the excess ions from the electrolyte and deposit them back onto the anode. These devices have shown reduction in resistance of at least an order of magnitude for a write energy as low as 24 nj[35], good endurance up to over cycles and retention for 10 years[36], [28], [22]. These desirable characteristics are preserved in highly scaled devices[37] with sub-20 nm devices being demonstrated to date[38]. Integration capability was also demonstrated by integrating Ag/GeS x /W cells into a 90 nm CMOS technology[39]. 8

21 Figure 1.2: Schematic of the PMC cell showing electrodeposition process. The chalcogenide based PMC s shows very impressive scalability and electrical characteristics required for an alternate memory technology, but in spite of these it is of considerable interest to investigate materials which are already present in the CMOS process line as electrolytes and electrodes in the PMC devices. The obvious reason for this is the ease and low cost of integration. As a first step, Cu-doped WO 3 has already been investigated to a great extent[19]. Tungsten is extensively used in the via plugs that connect different levels of metal in CMOS circuits and so its stable oxide, WO 3, was a reasonable choice as a base glass for the solid electrolyte. Furthermore, WO 3 is used in photo- and electro-chromic systems, which has resulted in a considerable understanding of its role as an ion transport medium[40]. PMC devices formed from a Cu doped WO 3 electrolyte have very promising characteristics as switching elements. The most stable device characteristics came from devices based on deposited 9

22 (rather than grown) WO 3. Copper was doped into the WO 3 films by a low temperature photo/thermal diffusion process. The resulting film contained unbound Cu that could take part in the formation of a metallic conducting filament on the application of an appropriate bias. The switching characteristics were very similar to those observed in the chalcogenide-based memory cells[19]. Going one step further in the attempt to stay close to the back-end-of-line compatible materials, SiO 2 is being investigated as the base glass material. This study concentrates on the study of Cu-SiO 2 based PMC devices, which is believed to present a low-cost option to integration into the CMOS process line due to the familiarity of the materials involved. 1.4 Crossbar architecture Apart from going into the third dimension in space at the device level as mentioned before, 3D architectures to add more memory layers are also being explored for scaling in the sub-20 nm regime for non-volatile memories. Different 3D architectures have been proposed by Samsung[41] and Toshiba[42]. However, these NAND 3D memories are complex structures possibly due to the 3 terminal nature of the basic floating gate cell. For a more cost effective solution for ultra-high density memory and solid state storage in the sub-20 nm regime, the industry has in general converged to the approach of a cross point memory [43]. Such systems have an extremely simple structure, with a compact two-terminal storage cell being located at each crossing point of multiple perpendicular (row and column) conducting lines. Not only is it possible to reduce cell area to its minimum possible value (4F 2, where F is the minimum feature size), it might also be feasible to construct multiple layers of cross-point devices, thereby attaining extremely high storage densities. A general structure schematic is shown in Fig Key point of this structure is that it scales directly with lithography without complex layout structure or transistor size limit as in NOR, NAND or even DRAM memories. Ultimately, the smallest memory device would be determined by memory and the switch- 10

23 Figure 1.3: Generalized cross-point structure with one bit of array consisting of a memory element and a switch element [2] ing material limitations. One key requirement of the memory storage element would be the capability to sustain through the processing temperature requirements of additional layers. Another requirement will be higher switching thresholds since there could be interference between cells in such a stacked 3D structure. Resistance-change memory devices with the right combination of active materials shows great promise as storage cells in these architectures. Their simple two terminal structure makes them inherently compatible with the crossbar architecture from a layout point of view. The main challenge in integrating a memory cell in a crossbar architecture is minimizing cross-talk via leakage paths, which is an inherent disadvantage of this architecture. An example of such a leakage path is when two adjacent cells in the same row are programmed to be in a low resistance state. Although the cells are in different columns by virtue of the crossbar architecture, their low resistance effectively links the columns together via the common row connection. Taking this to the worst case, low resistance cells could connect every row and every column in the array, making it difficult or impossible to access individual devices or, at the very least, severely limiting the size of the array. The obvious solution to this problem is to put an isolation device in series with the memory element at each cross-point. In current memory arrays, this device is typically a transistor which is fabricated in the silicon substrate (instead of thin film transistors in active matrix LCD displays) for reliable isolation of the memory cells. The high processing temperatures and difficulty in growing high quality epitaxial 11

24 silicon over metals reduces the ability for the active array to be fabricated in multiple layers in the upper levels of metal in the integrated circuit. Research in this area has therefore concentrated on simple thin-film diode elements in series with each cell, which in the example above will not allow column-to-column connection as one of the diodes will be reverse biased, cutting-off the current path. Such transistorless (at least at the memory cell level) diode-isolated architectures are typically called passive arrays. An SEM and TEM micrograph of such an array is shown in Fig The figures were originally from a work which demonstrated an array structure with p-i-n Polysilicon diode in series with SiO 2 antifuse element for stackable Field-Programmable ROM[3]. Following are some of the desired characteristics of the diode isolation element : 1. Process compatibility - Typically, a multiple level passive array will be integrated in the BEOL of the process. Hence, the interconnect lines should be able to withstand the processing conditions of the diode element. Thus, epitaxial Si based diodes are ruled out due to the high processing temperatures. 2. Rectification ratio - This is the ratio of the current or resistance for a particular magnitude of forward and reverse-bias voltage. Higher the magnitude, better will be the isolation provided by the diode in reverse-bias. 3. Current capacity - This value should be high enough to be able to write and erase the memory cell at reasonable voltages. Amorphous Si based diodes, in spite of its process compatibility due to low processing temperatures, is not preferred due to poor current capacity. Based on the above criteria heterojunction diodes based on oxides appear to be preferred over Si based diodes. A 2-stack 8x8 passive array based on Ti-doped NiO as the storage element and p-cuo x /n-inzno x as the diode element was demonstrated by Lee et.al [2]. The forward current density in these diodes were at 10 4 A/cm 2 and a rectification ratio high as 10 9 was reported for TiO 2 based diodes[44]. However, these 12

25 (a) (b) Figure 1.4: (a). SEM micrograph of two layers of memory cells in a passive crossbar array. (b). TEM cross-section showing the integration of the crossbar array[3]. 13

26 diodes involve deposition of multiple additional layers. Another approach is to use a memory element with inherent rectifying characteristics to simplify the fabrication process which in turn leads to lower fabrication cost, a critical factor in ultra-high density storage applications where the solid state system may be competing with the extremely low cost-per-bit of hard disk drives. Previously reported work concentrated on memory cells for write-once-read-many (WORM) applications, usually with a semiconductorinsulator-semiconductor or metal-insulator-semiconductor structure[45]. Electric fields in the range of a few MV/cm are applied to break down the insulator to form a rectifying junction. Since the programming process is irreversible, application has been limited to one-time programmable (OTP) memories but the approach has nevertheless demonstrated the feasibility of multi-layer crossbar memories. 1.5 Metal-semiconductor interfaces This section outlines some basic theory on metal-semiconductor interfaces and the current conduction mechanisms in such interfaces, relevant to the discussion of results in Chapter 4. Barrier formation When an interface between a metal and semiconductor is formed, an energy barrier is formed which controls current conduction across the interface. Fig 1.5 shows the band-diagram when an interface is formed between a metal and n-type semiconductor. In the case shown in the diagram, the work-function of the metal is greater than that of the semiconductor (φ m > φ s ) as shown in the band-diagram before the interface is formed in Fig 1.5a. After the interface is formed in Fig 1.5b, there is a barrier potential of φ bn from metal to semiconductor and φ bi from semiconductor to metal. The situation shown in the diagram is an ideal case, where there are no surface states on the semiconductor surface or interface states after forming the interface and the barrier formed is directly dependent on the work-function difference between the metal and semiconductor. However, in a real situation with surface states, the barrier formed 14

27 (a) (b) (c) Figure 1.5: Band diagram of a metal-semiconductor interface when a). they are separated. b). after the interface is formed. c). a positive polarity is applied on the metal. d). a negative polarity is applied on the metal. (d) becomes a function of the surface states as well. The surface states results in what is known as fermi-level pinning due to electron getting trapped in these surface states and and potential barrier is formed even if the metal work function is lower than that of the semiconductor work function. So the point being, irrespective of the type of metal, a barrier is always formed when a metal-semiconductor interface is fabricated. Fig 1.5 c and d shows the band bending and the direction of the flow of electrons for a negative and positive bias on the metal, respectively. The Fig 1.5c is the reverse-bias case, where irrespective of the voltage applied the electrons see a barrier of φ bn going 15

28 towards the semiconductor. Hence, the current tends to saturate and in an ideal case for moderately doped semiconductors (< cm 3, stays flat at a value called the reversebias saturation current (I SAT ). In the forward-bias case shown in Fig 1.5d, the barrier for electron flow from semiconductor to metal decreases with the applied voltage and thus the current increases (exponentially) with the applied voltage. Current transport mechanism The current conduction mechanism shown in Fig 1.5 c and d, where the electrons go over the barrier in either direction is the dominant mechanism in moderately doped semiconductors (< cm 3 ). Its called thermionic emission, based on the theory by Bethe[46] who assumed that the barrier height is the limiting factor for current conduction and calculated a net current flow by superimposing the current in both directions. The final equation for the current density in such an interface due to thermionic emission alone is : J TE =(AT 2 e qφ B qv kt )(e kt 1) (1.1) The constant A in 1.1 is the Richardson constant for thermionic emission. Its primarily dependent on the effective mass of the electrons. For more heavily doped semiconductors and for operation at lower temperatures, tunneling of electrons through barrier becomes more significant. The mechanisms are thermionic field emission (TFE) and field emission (FE). Fig.1.6 a and b shows the band diagram corresponding to TFE and FE in a forward-biased and reversebiased junction respectively. For doping densities in Si, in the range of cm 3 or higher, the tunneling of electrons directly from the conduction band of semiconductor into the metal or vice versa contributes to the current. At low temperatures and degenerately doped semiconductors ( cm 3 ), the tunneling is due to the electrons at bottom of the conduction band where the barrier is thin enough due to degenerate doping. This is called field emission. At intermediate temperatures, most of the electrons tunnel at an energy E m above the conduction band smaller than the energy E B of the 16

29 (a) (b) Figure 1.6: Band diagram showing Thermionic field emission and Field emission in (a). forward biased and (b). reverse biased Schottky barrier. [4]. 17

30 top of the barrier, as seen in Fig.1.6. This is called thermionic field emission. The relative contributions of the three type of current transport mechanisms mentioned above depend on both the temperature and doping level. A rough criteria is set by comparing the thermal energy kt to E 00 which is defined as: E 00 = qh 2 N m ε (1.2) The important variable in the above equation is N, which is the doping concentration. When kt >> E 00, TE dominates. When kt << E 00, FE dominates and TFE dominates when kt E 00. The derivation and analytical expressions for the current in TFE and FE mechanisms was first derived by Padovani [4]. The TFE equation relevant for the calculation of barrier potential in Chapter 4 is as follows : J s = J = J s e ( V E 0 ) (1 e qv kt ) (1.3a) E 0 = E 00 coth( qe 00 kt ) AT 2 e ( qξ kt ) kt cosh( qe 00 kt )e (φ b ξ ) E 0 (1.3b) (1.3c) In the above equations, φ b is the barrier potential and ξ is the position of the fermi-level with respect to the conduction band. Breakdown mechanisms Breakdown mechanisms in Schottky diodes while in reverse-bias is largely similar to that of p-n junctions. Two kinds of breakdown mechanisms exist in Schottky diodes or p-n junctions. The predominance of one mechanism over the other is determined by the doping concentration of both p and n sides for the pn junction and that of the semiconductor side for the Schottky diode. The mechanisms are as follows: 1. Avalanche breakdown - This dominates in reverse-biased junctions which are moderately or lightly doped (<10 17 cm 3 ) and the barrier width (or space charge region width) is higher so that TFE (for Schottky diodes) or band to band tunneling (for p-n junctions) is insignificant. The mechanism was first explained by 18

31 McKay for Si based diodes[47]. The breakdown was found to be a direct result of multiplication of carriers by collision and ionization, a mechanism called impact ionization. The energetic carriers in the reverse-biased space charge region collide with electrons in the valence band (bonded electrons) and excite them to the conduction band. These electrons gets accelerated resulting in further collision and ionization, resulting in a chain effect of avalanche breakdown. Generally, breakdown mechanism seen at voltages higher than 5 V or so, is believed to be due to avalanche breakdown. 2. Zener breakdown - This mechanism dominates in reverse-biased junction which are heavily doped (>10 17 cm 3 ) and the barrier width (or space charge region width) is thin enough for the TFE (for Schottky diodes) or band to band tunneling (for p-n junctions) is significant. In p-n junctions the electrons in the valence band on the p-side tunnels to the conduction band in the n-side under the influence of high electric fields ( 10 6 V/cm) and a thin space charge region ( 10 nm or lesser) which is due to the heavy doping on both sides. In the Schottky diodes the tunneling electrons are from the metal, which can be approximated to a degenerately doped semiconductor, to the conduction band of the semiconductor. 1.6 Report Outline Chapter 2 of the report presents the electrical characterization results obtained on Cudoped SiO 2 based PMC devices with W bottom electrode. The results involved switching characteristics to slow voltage sweeps, speed and endurance testing, potential for multi-bit storage etc. Chapter 3 of the report discusses the material characterization results obtained on Cu-doped SiO 2 films which gives some understanding as to switching mechanism and the composition of the Cu-SiO 2 matrix. Chapter 4 summarizes the results on the Cu/Cu-SiO 2 /W PMC devices and discusses some of the possible future work in this. Chapter 5 discusses switching characteristics of Cu/Cu-SiO 2 /nsi devices which shows inherent isolation and proves its feasibility for use in passive arrays. 19

32 (a) Figure 1.7: Band diagram showing a). avalanche breakdown by impact ionization and b). zener breakdown by band to band tunneling in pn junctions[5]. (b) 20

33 Chapter 2 Device characterization 2.1 Device fabrication The device structure schematic of a typical PMC device is shown in Fig It consists of an electrolyte layer sandwiched between a top oxidizable electrode and a bottom inert electrode. The width of the via hole (D) in the dielectric separating the top and bottom electrode is the device diameter, which is the active area as electrodeposition occur in the electrolyte in this region. The bottom electrode can be any inert material like tungsten, platinum, nickel etc. The dielectric layer which isolates one PMC from the other and also defines the active PMC layer can be any isolation layer like Si 3 N 4, PMMA or other inter level dielectrics like BPSG, FSG etc. All the samples of the Cu-doped SiO 2 PMC devices based on W bottom electrode were fabricated on substrates procured from Qimonda AG, Munich, Germany. The wafer has 100 nm PECVD nitride deposited on top of 450 nm W metal film. The substrates contain 200 nm Oxide and a TiN/Ti (80nm/25nm) double layer which acts as an adhesion promoter and a diffusion barrier beneath the W electrode. A schematic of various layers in the wafer used for fabrication is given in Fig. 2.2 All the wafers have the vias already patterned on them by Qimonda. The via Figure 2.1: Schematic of a PMC test device layout. Diameter, D defines the electrolyte area that contacts the bottom electrode forming the active device area. 21

34 Figure 2.2: Schematic cross section of the 8 inch wafer obtained from Qimonda AG, Munich, Germany, used for PMC fabrication. Tungsten layer acts as the bottom electrode and vias are already etched in the wafer. sizes range from 5 µm to 180 nm. Further processing steps which involves the substrate preparation, cathode definition, PMC layer deposition and anode patterning yields the PMC devices. These steps were performed in the Center for Solid State Engineering and Research (CSSER) cleanroom in ASU. The steps are outlined in the following sections and a schematic of these steps are shown in Fig Substrate preparation The wafers obtained were 8 inch wafers. Since the processing tools were not compatible with 8 inch wafers, they were diced into samples of about 5 cm x 5 cm size. These samples were rinsed thoroughly in deionized (DI) water and blow-dried using N 2 jet. The DI water lacks cations such as sodium, calcium, iron, copper and anions such as chloride or bromide, which are undesirable impurities in silicon processing. Bottom electrode (Cathode) definition This involves a lithography step using the cathode mask provided by Qimonda AG, Munich, Germany. About 3-4 ml of hexamethyldisilazane (HMDS), an adhesion promoter and AZ 3312 positive photo resist were spun at 3500 rpm for 30 seconds using a standard photo resist spinner. This yields a uniform resist film of 1 µm thickness. The samples were then soft baked at 100 o C on a hot plate to evaporate off the excess 22

35 solvent from the photoresist. The samples were exposed using the cathode mask (dark field) in the Karl Suss MJB3 UV300 mask aligner for 18 seconds. The lamp power is in the range mw/cm 2. The samples were then developed in AZ 300 MIF developer for 40 seconds. They were then hard baked on a hot plate at 110 o C for 1 minute. The hard bake solidifies the resist to make it a more durable protecting layer in the following etching step. The cathode mask exposes square patterns on the resist and these square patterns are transferred on to the Si 3 N 4 dielectric underneath by etching which opens up the bottom W electrode for probing. Etching was carried out in an Oxford Plasmalab 80Plus reactive ion etching tool in a 50 sccm CHF 3 and 5 sccm O 2 plasma. After the etching process the left over resist on the sample is stripped using acetone. Top electrode (Anode) definition This involves a similar lithography process as in the previous step, but this time using another mask which exposes anode pad regions and aligns it to the vias. Resist is not stripped after exposure and developing as the pad patterns on the deposited metal is obtained through a lift-off process in the end. PMC stack depostion The deposition tool for all the Cu doped SiO 2 PMC devices was a Torrvac VC-320 electron beam evaporator. For the first batch of samples (Batch A) the process was carried out in similar lines to the chalcogenide based PMC s or the Cu doped WO 3 PMC devices which involves a photodissolution step as mentioned in section??. However, much thinner films were used as the electrolyte. 12 nm thick SiO 2 and then 20 nm of Cu was deposited in that order without breaking the vacuum in the e-beam evaporator. The samples were removed from the deposition system and then exposed to broadband ( nm) UV light at a dose of 2 J/cm 2 (calibrated at 365 nm) for the photodissolution process. It was then returned to the evaporation system and an additional 33 nm of Cu was deposited to make sure there is enough copper on the top to act as the oxidizable 23

36 anode. It also ensures electrical continuity while probing. The stack is patterned using a liftoff process which defines the electrolyte and the anode regions. During the electrical characterization of Batch A devices, they didn t show any switching for quasi-static voltage sweeps. This is expected, because, the photon energy of the UV light used for photodissolution is 3.39 ev (for λ = 365 nm) and the bandgap of SiO 2 is 9 ev. Photodissolution process is believed to involve formation of charged defects in the case of chalcogenides and hosting of the mobile ions in these voids or defects[48]. Thus the photon energy is just not enough to create this charged defects by breaking the bonds in the SiO 2 network. This along with the highly rigid network of the SiO 2 can limit Cu photodiffusion to a great extent. Thus thermal annealing was adopted to drive the Cu atoms into the oxide. The concept behind the process of thermal doping of Cu in SiO 2 for PMC devices has been discussed in more detail in the next chapter dealing with material characterization. The Batch A samples were annealed at 610 o C for 15 mins in a flowing N 2 ambient. 250 nm SiO 2 was deposited as a protective layer on the samples before the annealing. This protective layer was etched off using 20:1 BOE solution before electrical characterization. These annealed devices showed resistive switching. To test whether it was a combined effect of photodissolution and thermal annealing that resulted in resistive switching in Batch A samples, another batch (Batch B) samples were prepared without a photodissolution step. In this batch, 12 nm thick SiO 2 was deposited followed by 33 nm for Cu without breaking the vacuum. Annealing under similar conditions as that of Batch A was performed after depositing the protective layer. Resistive switching was again observed in this case, from which we concluded that photodissolution is not necessary. Since the processing sequence followed for the Batch B samples was adopted as the standard for all the future batches, all the electrical results presented here are from Batch B or a batch with similar processing conditions. Fig. 2.3 (a-n) shows the step-by-step schematic of the PMC fabrication process. 24

37 a).substrate prepared for processing. b).az 3312 photoresist spun and soft baked at 100 o C for 1 min. c).cathode pad lithography done. Figure 2.3: PMC fabrication process steps. 25

38 d).si 3 N 4 dielectric etched using RIE. e).photoresist stripped using acetone. f).az 3312 Photoresist spun and soft baked at 100 o C for 1 min. Figure 2.3: PMC fabrication process steps (cont.). 26

39 g).anode stage lithography done. h).12 nm of SiO 2 (solid electrolyte) and 20 nm of Cu deposited. i).photodissolution process in UV light. This step is skipped in Batch B samples. Figure 2.3: PMC fabrication process steps (cont.). 27

40 j).33 nm of Cu (top electrode) deposited. k).liftoff done in acetone. l).250 nm of SiO 2 (protective layer) deposited. Figure 2.3: PMC fabrication process steps (cont.). 28

41 m).thermal annealing done at 660 o C for 15 mins. n).sio 2 (protective layer) etched off using 20:1 BOE solution. Figure 2.3: PMC fabrication process steps. 29

42 Figure 2.4: Top view of the wafer, a single die and a single via PMC test structure. Fig. 2.4 shows the wafer, a single die and the top view of a single via PMC test structure. The Cu anode is the top oxidizable electrode and the W cathode is the bottom inert electrode. 2.2 Experimental setup Voltage sweep measurements The basic switching characteristics were studied by taking the current-voltage (I-V) and resistance-voltage (R-V) measurements of the devices by giving slow voltage sweeps using Agilent Semiconductor Parameter Analyzer (4155B SPA). The electrode pads of the devices were connected to the 4155B SPA via tungsten probes held in micro manipulators in a probe station as shown in Fig

43 Figure 2.5: Photograph of the probe station setup used for electrical testing of the PMC devices. given: The 4155B was set in the sweep mode and in general two types of sweeps were 1. Write: Double sweep starting from zero to a positive value and back to zero. Erase: Double sweep starting from zero to a negative value and back to zero. 2. A double sweep starting from a negative value through zero to a positive value and back to the initial negative value. This is used for simplicity as both write and erase is performed in this single double sweep. However, in this setting both the write and erase sweeps have to performed with same compliance current setting. A compliance current (programming current, I prog ), usually in the order of 31

44 A, was set for the basic I-V and R-V plots. The 4155B limits the maximum current through the device to the programmed compliance current once the device switches ON to a low resistance state. All these measurements were done in room temperature. Data retention measurements Date retention measurements were carried out to measure the memory cell s ability to retain data over time. 4155B SPA was used to do these measurements. The device was initially written by giving a slow voltage sweep as explained in the previous section. 4155B SPA was then setup in the sampling mode, in which it applies a constant voltage (read voltage) across the device and takes measurements at specified regular intervals of time. The read voltage amplitude was chosen so as not to disturb the present state of the memory cell. The OFF state retention as well as the ON state retention of the devices were measured in room temperature. Typical testing time was around 30 hours and the ON or OFF resistance vs time data is plotted. Speed Measurements Speed test gives an idea as to how fast the device can switch from high resistance OFF state to low resistance ON state. Write pulses were given using the Sony-Tektronix Arbitrary Waveform Generator AWG The circuit used for this measurement is given in Fig. 2.6 In the circuit shown in Fig. 2.6, the pulse generator, oscilloscope and the resistor makes up the writing section. The pulse generator was connected in parallel to the oscilloscope, which is a Tektronix Four-Channel Digitizing Oscilloscope (TDS 540B), to display the single write-pulse waveform being given to the PMC. The connection between the write part of the circuit and PMC was established by closing the switch S1. The switch S2 was open, so that the 10 kω resistance gets introduced into the writing circuit to control the current through the PMC. 4155B SPA forms the read section of the circuit. For reading the data (resistance) a read voltage was given to the PMC and 32

45 Figure 2.6: Schematic of the circuit used for PMC speed testing measurements. the I-V and R-V measurements are recorded. The read voltage magnitude was small enough so as not to disturb the present (written or unwritten) state of the PMC. The switch S3 and S2 was closed and S1 was open during the reading operation. The 10 kω resistance gets shorted out by closing S2 before the read operation, because it will act as a series resistance to the PMC and affect the I-V and R-V measurements. Before the writing operation, a read sense voltage of 200 mv amplitude was given to the PMC to make sure the device was in the high resistance OFF state. The AWG 2021 was programmed in the trigger mode. In this mode, whenever a trigger is given, a single pulse of specified width and amplitude is applied across the PMC device. The TDS 540B was set up in the persistence time mode to capture the write pulse whenever it is applied. After applying the write pulse across the PMC, the 4155B SPA was connected and a 200 mv sense signal was given to measure the resistance of the PMC device. If there is a significant change in resistance from the initial OFF resistance value, by at least 2 orders of magnitude, the device is considered to be written. The width of the read pulse given gives the time taken by the device to undergo this transition, thus giving an idea of the speed of the device. 33

46 Endurance Cycling Endurance cycling test is done to know how many write and erase cycles the device can survive before it fails. Fig. 2.7 shows the circuit used for the endurance cycling tests. Figure 2.7: Schematic of the circuit used for PMC endurance cycling measurements. The AWG 2021 was used to give the write and erase pulses of programmable width and amplitude. It was connected in parallel to the channel 1 of the oscilloscope TDS 540B. A resistance of 10 kω was connected in series to the PMC device to limit the ON current through the PMC. The output was taken across this resistance which serves as an output load resistance and the output signal was viewed in the channel 2 of the oscilloscope. The input signal which is a continuos waveform going from positive (write) to negative (erase) and with a programmed frequency was applied at the anode of the PMC. During the positive going cycle of the input signal the PMC switches to the low resistance ON state and depending on the current in the circuit a particular voltage is dropped across the load resistance. This can be viewed in the oscilloscope channel 2. On the negative going cycle of the input signal the PMC switches to the high resistance OFF state and little or no voltage drop will be seen across the load resistance. The device can be considered failed if the output voltage is just a scaled down version of the input voltage, which means that the PMC device is not erasing properly and in some cases has shorted out completely. In some other cases, the output voltage can 34

47 drop to very low values which means that device is not being written properly and the ON current through the circuit is very less to give any significant output voltage. In this case also the device is considered to have failed. During the endurance cycling experiments, the devices tend to show one of these two failure characteristics at the beginning of the test itself. Mostly, this was not a real failure but it just meant that the input signal was not optimized enough in terms of it amplitude and frequency to write and erase the PMC device properly. This was overcome by tweaking the input signal to get that optimum value in terms of write pulse amplitude and width and also erase pulse amplitude and width, once this was achieved the devices are found to cycle consistently till a real failure is seen. The number of cycles the device has survived was taken as the time to failure divided by the total pulse width. 2.3 Results Typical switching characteristics Figure 2.8 shows typical switching characteristics of Cu doped SiO 2 based PMC for a slow voltage sweep. This particular device has a 1 µm via diameter and a 12 nm thick Cu-SiO 2 electrolyte. The sweep direction is labelled with numbered arrows to help better understand the sequence of events in such a voltage sweep. The voltage sweep shown here is a double sweep starting at -1V going to 1V and back to -1V. In the region 1 and 2 the device is at high resistance state (OFF) and the resistance recorded at any specific read voltage in this region can be defined as the R off. At region 3, the device switches to a low resistance state (ON). This voltage, at which a device initially in the high resistance state switches to a low resistance state is defined as the primary switching threshold (V t1 ). The R off to R on ratio is usually taken as at least 10 2 for being considered as a successful turn-on. The V t1 in this case is around 400 mv for three consecutive sweeps. The current in the region soon after this switching (4 and 5) is limited to a compliance value (I prog ) of 10µA in this case. The significance of this compliance current or programming current is explained in a later section. The resistance shown 35

48 (a) (b) Figure 2.8: (a) Current Voltage and (b) Resistance Voltage Curve of 1 µm diameter via,12 nm thick Cu-SiO 2 electrolyte (Batch B) device for a programming current limit of 10 µa. Double sweep from -1 V to 1 V and back to -1 V. 36

49 in the R-V curve in region 4 and 5 is an artifact of the compliance current limit setting enforced by the instrument and is not a true representation of the device resistance after switching. At V t1, a conducting link is formed between the top and the bottom electrode by the Cu electrodeposit. Once this link is formed, the voltage drop across it decreases to a minimum value required to sustain the electrodeposit. This value is shown as the secondary threshold value (V t2 ). Note that the voltage on the X-axis, is the applied voltage and not the actual voltage drop across the device. When the reverse voltage sweep decreases below the V t2 value, the device shows ohmic characteristic in this region (6). This region represents the resistance of the electrodeposit (R on ) formed at this compliance current. From the IV graph it can be seen that, V t2 /I prog =R on. In this case V t2 is approximately 150 mv, giving an R on = 15 kω. The device switches back to the high resistance state in the region 7, at a negative voltage less than 100 mv in this case. The current value and voltage value which initiates this low to high resistance switching is defined as the erase initiation current (I ers ) and erase initiation voltage (V ers ) respectively. Switching for different via diameters Figure 2.9 shows a comparison of the switching characteristics shown by devices of via diameters 5 µm, 2.5 µm, 1 µm and 0.5 µm. From the Figure 2.9 a) it can be seen that the primary threshold is in the range 0.33 V to 0.49 V. However, there is no trend in this variation of the primary threshold which can be related to the variation in via diameters. The variation in the primary switching threshold usually centering around 500 mv is seen across different devices in various samples processed under similar processing conditions. This variation seems to be due to the existence of Cu as free atoms in the SiO 2 matrix. This is explained in more detail in chapter 3. The R on of these devices is at an average value of 14 kω for an I prog of 10 µ, shows no significant variation with the different via diameter. The R off, however shows a significant decreasing trend with increase in the via diameter as can be seen in Figure 2.9. This behaviour of constant R on 37

50 a b Figure 2.9: (a). Resistance-Voltage plots of devices with different via diameters, for a programming write current of 10 µa. (b). R off and R on for the devices with different via diameter. 38

51 for a particular value of I prog irrespective of the via diameter and decreasing R off with increase in via diameter is shown by the chalcogenide and WO 3 based PMC devices as well. Similar behaviour is shown by other binary oxide based resistance switching devices, like TiO 2, NiO. In all these devices the conduction mechanism in the ON state is believed to be formation of a filamentary conduction path independent of the size of the via/pad[17]. Similar to the other cationic migration based resistance switching devices, the switching mechanism in Cu doped SiO 2 is believed to involve the formation of a nanoscale electrodeposit link between the anode and cathode. In the PMC devices, even though there can be many sites on the cathode where the dendrite growth can happen. Due to the randomness of this growth process, one of the dendrites will be favoured to complete the link between the cathode and anode. If one dendrite is slightly longer than the others, the electric field between the anode and its tip will be higher favouring a faster growth of this dendrite. The average diameter of such a single dendrite which determines the R on will not depend on the total via cross-section. It will however depend on the total charge being transferred during the electrochemical reduction process as shown in the next section. Since R off is the resistance of the device when there is no electrodeposit formed, it depends on the Cu-doped SiO 2 electrolyte bulk according to the relation R off = ρl/a. Here ρ is the resistivity of the Cu-doped SiO 2 electrolyte, L is the thickness of the electrolyte which is 12 nm in this case and A is the area of the via cross-section which increases with the via diameter and thus decreasing the R off. Switching for different programming currents The process of formation of the electrodeposit is believed to involve the reduction of Cu n+ ions by the electron current from the bottom electrode, similar to the process shown in Fig Hence, a larger electron current should result in the reduction of more number of Cu n+ ions forming an electrodeposit with larger cross-secitonal area. 39

52 Fig is the switching characteristics shown by a 1 µm diameter device, for different values of I prog. In the I-V plot, the slope of the curve between 0 V and the V t2 gives an idea of the R on. There is a consistent increasing trend in the slope with higher values of I prog, which corresponds to decrease in resistance. The I prog values used were 5 µa, 1 µa, 500 na, 250 na and 100 na. The R on values obtained were 30 kω, 129 kω, 250 kω, 392 kω and 1.2 MΩ respectively. Data obtained by C. Schindler [6]. This Figure 2.10: Current Voltage plot of a 1 µm diameter via, 12 nm thick Cu doped SiO 2 electrolyte device for different programming current limits. Voltage sweeps are double sweeps from -1 V to 1 V. Data obtained by C. Schindler [6]. dependence of the R on to the I prog is shown by the chalcogenide glass based PMCs as well[22, 36]. This strongly suggests that the switching mechanisms in all the PMC devices are the same and is indeed due to the formation and removal of a conductive link formed and removed by an electrochemical process between the anode and cathode. The electrochemical process is the reduction of the Cu ions by the electron current from the cathode. Once that initial link is established the current rises to the I prog and the electron current now is proportional to this value of I prog. Higher the I prog, higher is the electron current and more Cu ions will get reduced and electrodeposited on the 40

53 already existing link. Thus the electrodeposit becomes thicker (larger cross-sectional area) and its resistance drops. So different values of I prog can yield different R on values, each being unique to the particular I prog. This feature of the PMC device can be used in implementing a Multi-bit cell memory (similar in principle to an MLC flash memory cell). A particular memory cell can be programmed into any of say 4 resistance values by using one of the 4 predetermined values of I prog. A read voltage which is small enough so that it won t rewrite the device, can be used to sense the resistance to which the cell has been programmed to. Each of the 4 resistances can correspond one of the 4 digital data, 00,01,10 or 11. Fig gives a more statistical idea of the spread of the R on obtained for two different programming currents, 25 µa and 250 µa. Data shown here was obtained from 18 different devices, 9 for each programming current and 3 consecutive program-erase voltage sweeps on each. Each data point is the median value of R on obtained for the 3 sweeps on that device. The error bar shown is the median value of the absolute deviation of each data point. It is calculated as given Figure 2.11: R on across different devices for two different write programming currents. Each point corresponds to the median value of R on for 3 consecutive voltage sweeps on a particular device. 41

54 below : Median of absolute deviation = median i ( X i median j (X j ) ) (2.1) It has to be noted that these devices were programmed using slow voltage sweeps with a compliance current setting in The compliance control of 4155 is not necessarily accurate across different sweeps and there are also possibilities of voltage spikes at the beginning or ending of a sweep which could affect the states and result in inconsistency between different sweeps. However, the potential for multi-bit programming can be proved using these results. The control of the variation in the programmed states between multiple cells for the same programming conditions is important for reliable sensing in a memory array. In the current Flash memory cells, based on charge storage in a floating gate, this involves the control of the threshold voltage distribution for the same amount of charge stored in the oxide. To achieve such control, the program/erase operation in actual memory arrays are not simple voltage pulses of predetermined amplitude and time. Rather, its a combination of a program-and-verify scheme along with a staircase voltage ramp, called Incremental Step Pulse Programming [49]. Similar programming schemes may have to be used in a PMC array as well to achieve control of the resistance states, more so, if its being programmed into more than two states for multi-level cell operation. Erase characteristics As explained before, the erase process involves electrochemical oxidation of the Cu atoms in the electrodeposit. This process is indeed believed to be the dominant factor when the erase initiation current is in the range of few ten s of micro amperes or less and the R on value of the programmed state is in the kiloohms range or higher. Lower the R on value (higher the I prog ), higher is the current required in the reverse direction to produce enough voltage drop across the electrodeposit to result in the oxidation of the Cu atoms and removal of the electrodeposit. Fig shows the variation in the erase initiation current with the programming current for I prog in the range less than 1µA. The 42

55 Figure 2.12: R on and I ers as a function of the write current for a 12nm Cu doped SiO 2 device with a diameter of 5 µm. The R on falls and the I ers rises with increase in I prog. erase initiation voltage remains in the range of 40 mv and the erase initiation current varies from 10 na to 160 na for this range of low programming currents. These low current and voltage values required for erase initiation indeed points towards a dominant electrochemical process. Fig shows the erase initiation current and voltage for 25 µa and 250 µa programming currents. Data shown here was obtained from 18 different devices, 9 for each programming current and 3 consecutive programerase voltage sweeps on each. Each data point is the median value obtained for the 3 sweeps on that device. The error bar shown is the median value of the absolute deviation of each data point and calculated as shown in equation 2.1. It is seen that the erase initiation current for 250 µa programming current is consistently at least an order of magnitude higher which is consistent with the one order of magnitude increase in the programming current. The erase initiation voltage shown in Fig. 2.13b does show an increase by a factor of 3 (at the maximum) between the two programming currents, which however doesn t bear a direct relationship to the one order of magnitude increase 43

56 (a) (b) Figure 2.13: (a). Erase initiation current (b). Erase initiation voltage for programming currents, 25 µa and 250 µa. Each point corresponds to the median value for 3 consecutive voltage sweeps on a particular device. 44

57 in the programming current. It is believed that the Cu atoms in the electrodeposit begins to oxidize when the voltage drop across the electrodeposit reaches a threshold value of few tens of millivolts, whatever be the programming current. So a higher programming current written electrodeposit will require a higher erase initiation current (an order of magnitude higher in this case) due to its lower resistance (an order of magnitude lower in this case). The reason for the apparent higher erase initiation voltage in the case of 250µA programming current, is believed to be due to plating of Cu at the bottom electrode which is quite possible in the slow voltage sweeps at such high programming currents. Influence of annealing conditions It has been observed that an annealing temperature less than 500 o C hardly yields any significant number of switching devices in a sample. To understand the influence of the annealing temperature on the switching characteristics, three samples were prepared using the same process flow explained before. Each of the three samples were annealed at 3 different temperatures, 560 o C, 660 o C and 720 o C. The annealing time was kept constant at 15 mins in a flowing liquid N 2 ambient. The parameter observed during testing was the primary switching threshold of the devices. Fig shows the primary switching threshold of the first voltage sweep after processing. The switching in the first sweep is observed here because it is believed to be directly influenced by the annealing conditions. Since each write and erase cycle involves the formation of and removal of an electrodeposit, the device characteristics tend to be history dependent. Hence, the subsequent sweeps might be influenced by how well the device has been erased in the previous sweep. This is evident in Fig where multiple sweeps shows a decreasing trend in the primary switching threshold, especially in the 560 o C annealed sample where the average value has decreased by almost 100 mv. Fig shows a clear decrease in the average switching threshold by about 250 mv between the annealing conditions of 560 o C and 660 o C. Another important trend observed is the decrease 45

58 Figure 2.14: Primary switching threshold Vs Annealing temperature of the first voltage sweep on the device after processing in the spread of the switching threshold after anneal at 660o C. This points towards a more optimum composition of Cu in the SiO2 matrix. The data obtained is from at least 15 different devices and is believed to be representative of Cu-SiO2 based PMC devices in general. These experiments were conducted along with the material characterization of Cu-SiO2 blanket film substrates processed at the same annealing conditions, to understand the behavior of Cu in the SiO2 matrix. A more detailed discussion is given in the next chapter and the switching threshold results presented here are revisited during that discussion. Unipolar switching Unipolar switching involves the formation and removal (write and erase) of the electrodeposit using the same voltage bias polarity. In this case, the device is written using a positive voltage sweep as before with a particular programming current. The erase sweep in this case is also a positive sweep. From a circuit design point of view, ability to switch device in unipolar mode might make things simpler by avoiding negative voltage swings. It also has its implications in a memory array based on diode isolation 46

59 Figure 2.15: Primary switching threshold variation with multiple sweeps on Cu-SiO2 PMC devices annealed at three different temperatures. (passive array), which will be discussed in chapter 4. One major difference compared to the bipolar switching is the much higher erase initiation current required for the unipolar erase. The erase initiation currents were generally found to be in the milliamperes range for the Iprog values tested (50 µa and above). The high erase initiation currents combined with a voltage polarity which opposes any electrochemical dissolution of the Cu electrodeposit, points towards an erase mechanism initiated by joule heating in the electrodeposit. Fig shows a unipolar write-erase cycle. The IV curve in Fig. 2.16a shows only the erase sweep, since the Iprog was 75µA and not clearly visible in this scale. The Fig. 2.16b shows the write sweep (black). In the erase sweep, it can be seen that the device switches back to the high resistance state with an erase initiation current of approximately 2.75 ma and at 0.9 V. Similar to the erase characteristics shown in the bipolar switching of these devices, when written with a higher Iprog the Iers was also higher. Fig shows the trend in Iers based on the Iprog. Joule heating is directly proportional to the square of the current passing through a conductor and also to the resistance of the conductor. In this case the conductor is the Cu electrodeposit in 47

60 (a) (b) Figure 2.16: (a). Current Voltage plots and (b). Resistance Voltage of the Unipolar switching shown by a 12 nm thick Cu-doped SiO 2 device with diameter 2.5 µm. I prog is 75 µa. 48

61 the PMC device. The Cu electrodeposit link has been shown to give lower resistance (R on ) for higher I prog (Fig. 2.10). It means that an electrodeposit of lower resistance (higher I prog ) will be subjected to less joule heating for the same current compared to one with higher resistance (lower I prog ). Thus a higher I ers will be required to produce enough thermal energy to rupture the dendrite. Even though the erase initiation current shows an increasing trend with the increase in programming current, there could be discrepancy in the exact range of the erase initiation current due to an overwrite effect in the erase sweep. In Fig. 2.16b, there is a drop in resistance between region 2 and 3, which means that the initial electrodeposit formed during the write sweep with and I prog of 75 µa is now being overwritten due to the positive polarity of the erase sweep and higher compliance current setting. So a much higher erase initiation current is required for this rewritten state than it would have taken for the original written state. Figure 2.17: I ers measured for I prog values 50 µa, 75 µa, 1 ma, 2 ma and 5 ma. Just like the erase characteristics in bipolar switching, the I ers increases with an increase in the I prog 49

62 Reverse bias writing effect Some of the devices, mostly the one annealed at 720 o C tend to show symmetric write and erase switching in both polarities. Fig shows the IV curve of one such device after annealing at 720 o C. Three consecutive voltage sweeps starting from V to 1.5 V and back is shown and as seen the switching characteristics is very consistent across the three sweeps. Its seen that the characteristics are very symmetric, with a high resistance to low resistance switching happening at ±0.3 V and the low resistance to high resistance switching happening at ±0.15 V. This symmetric nature of the switching points towards a symmetric device structure as well. Its possible that instead of a Cu/SiO 2 /W structure, there exists a Cu/SiO 2 /Cu structure in these cases. This is possible if Cu diffuses all the way to the bottom SiO 2 /W interface and gets accumulated there. The fact that this is seen more in the higher temperature annealed samples strengthens the case. This type of switching is revisited in the next chapter with some evidence from the material characterization samples. Figure 2.18: I-V device characteristic of a Cu-SiO 2 device annealed at 720 o C showing symmetric unipolar switching 50

63 Retention Charactertics Data retention measurements were done with 4155B SPA as described in the experimental setup section at room temperature. Data from two different devices are shown in Fig A read voltage of 300 mv was used in the case of Fig. 2.19a and 50 mv was in the case of Fig. 2.19b. This value is comparatively lower than the secondary threshold voltage of these devices and hence shouldn t disturb the written state. Both devices showed similar retention characteristics, in the range of to 10 5 seconds as shown in Fig The experiment was stopped after around 10 5 seconds due to tool availability constraints. The Fig. 2.19a shows a sudden increase in the R on by approximately one order of magnitude after around 10 4 seconds. However, the resistance dropped back to the initial R on after about seconds. This could be a partial failure in the electrodeposit link, since this device is subjected to a low but constant stress voltage of 300 mv (sampling mode of 4155B SPA). This partial break or maybe localized thinning of the electrodeposit could have resulted in a local higher voltage drop across this failure region due the higher resistance in this region and thus resulting in a redeposition of the electrodeposit in that particular region. Apart from this partial self-healing failure the R on and R off for both devices don t show any visible trend in resistance variation. The ON state retention data in Fig. 2.19b was obtained by C. Schindler [6] Speed Testing The circuit setup used was described in the experimental setup section. Good writing effect was observed for pulse widths as low as 1 µs. The magnitude of the pulses given is important to get a stable write. The writing effect was stable for pulse magnitudes of 3 V. Lower magnitude pulses of the same frequency didn t show good writing effect. The 3 V magnitude for which good writing effect was observed is high compared to the V t1 shown by the devices during quasi-static measurements, but its necessary to 51

64 (a) (b) Figure 2.19: (a). ON state retention characteristics of a 1 µm via diameter device with 300mV read(stress) voltage. (b). OFF and ON state retention characterstics of a 1 µm via diameter with 50 mv read(stress) voltage. 52

65 overcome the effect of parasitic capacitance in the test setup and also to make sure that the device is properly written. Fig shows resistance before giving the pulse (R off ) and the resistance after giving the pulse (R on ) for read voltages upto 200 mv. Figure 2.20: Resistance Vs Read Voltage plot for a 12 nm thick Cu-doped SiO 2 device with a diameter of 500 nm switched using a 3 V pulse of 1 µs length. Endurance Cycling Endurance cycling was done on a 350 nm via diameter device. The experiment was started off by giving a standard pulse of +1 V to -1 V amplitude and the write pulsewidth and the erase pulse-width being few microseconds. An optimized write pulse of 1.98 V amplitude and 7 ms width and an erase pulse of -260 mv amplitude and 3 ms width was found to be writing and erasing the device properly. The amplitude of the write pulse is higher than the primary threshold shown by these devices and is long enough to properly write the device. The erase pulse is also high enough to properly erase the device as these devices had shown a typical erase threshold less than 100 mv (Fig. 2.8). Fig shows the screenshots from the TDS 540B oscilloscope at 53

66 Figure 2.21: Endurance cycling data after (a) and (b) cycles. In each figure the top trace is the input signal from the Waveform Generator and the bottom trace is the output signal taken across the 10 kω load resistor. 54

67 Figure 2.22: Test circuit current through the device in the ON state during the endurance cycling test as a function of number of cycles. two different times during the endurance cycling test. In each figure the top trace is the input signal from the waveform generator and the bottom trace is the output signal taken across the 10 kω resistor. Fig. 2.21a is the screenshot after cycles and Fig. 2.21b is the screenshot after seconds. Even after the device is clearly ON or written when the input signal is high, as the voltage drop across the resistance is 24 mv which means around 2.4 µa of current is flowing through the device. The device seems to be completely erased when the input voltage is negative, as the voltage drop across the resistance is zero which indicates only negligible current is flowing in the circuit. Note that the output voltage after was 56 mv, which means that there is a decreasing trend in the output voltage and hence the circuit current. Fig shows the decreasing trend in the test circuit current. This effect has to be investigated further because knowledge of performance variation of the devices over time after many write erase cycles is an important factor. 55

68 Chapter 3 Material characterization To understand the switching mechanism in the Cu-doped SiO 2 based PMC devices and to understand the parameters which could affect the switching characteristics and hence help in optimizing the performance of the devices it is necessary to understand the compositional characteristics of the Cu-doped SiO 2 film. Understanding the optimum compositional characteristics will also help optimize the device processing conditions. So, it is necessary to understand how the Cu interacts with the SiO 2 matrix once introduced into it by thermal annealing. Various material characterization experiments were done of Cu-doped SiO 2 samples at different processing conditions. A summary of the results and related discussion are presented in the following sections of this chapter. 3.1 Sample fabrication All material characterization experiments were performed on blanket films of Cu-doped SiO 2 on TiN/Si substrate. The TiN layer formed a diffusion barrier for Cu and prevented Cu diffusion into the Si substrate. In this manner, any opportunity of contact between diffused Cu and the Si substrate was avoided. Such contact could lead to additional reactions and complicate the analysis for the results. The SiO 2 and Cu films were deposited using a Torrvac VC-320 electron beam evaporator at an average evaporation pressure of 4 x 10 4 Pa and 0.2 nm/sec deposition rate. In the first batch (A) of samples, 350 nm thick Cu film was deposited on the TiN/Si substrate and 750 nm thick SiO 2 on top of it. So the material stack was SiO 2 -Cu-TiN-Si from top to bottom. The thickness of the SiO 2 film was expected to accommodate for the input signal penetration into the film, so that the underlying Cu film doesn t contribute to any of the output signal obtained, especially during the Raman and X-Ray diffraction (XRD) analysis. However, the X-Ray diffraction results from these samples showed very sharp peaks characteristic of Cu even before any thermal processing. This had to be due to the underlying Cu film. The XRD results from these samples had to be discarded because the signal from 56

69 Figure 3.1: Schematic of the film stack (Batch B) used for material characterization the underlying Cu film was found to overwhelm the signal from the Cu diffused into the SiO 2 film after thermal processing. However, no such discrepancy was observed for the Raman analysis results. Thus the Raman analysis results presented here were obtained from Batch A samples. A second batch (B) of samples were prepared for further material characterizations. The film stack sequence from top to bottom for this batch of samples was as follows : 750 nm SiO 2 ; 350 nm Cu and 550 nm SiO 2 on TiN/Si substrate. The top SiO 2 film was used to prevent the oxidation of the Cu film during the thermal processing of the samples. The high temperature thermal doping of SiO 2 was carried out in a Lindberg Tube Furnace in a N 2 flowing ambient. The stacks were split into several groups, each one annealed at 560 o C, 660 o C, or 720 o C for 15 min, 1h or 2h respectively. It has to be noted that the thermal doping conditions were similar for samples from both the batches. After the thermal doping process of the batch B samples, the top SiO 2 layer was etched off using a buffered oxide etchant (a 20:1 volume ratio solution of ammonium fluoride (buffering agent) and hydrofluoric acid. To exclude the interference of the top Cu film, it was etched off with a standard Cu etchant 49-1 from Transene Company, Inc., a citric acid based etchant with an estimated etch rate of 22 57

70 Å/s at 30 o C. Fig. 3.1 shows the batch B stack before and after dissolution of Cu. 3.2 Experimental setup X-ray diffraction analysis (XRD) - A one degree glancing scan XRD was performed using a Phillips X pert MPD diffractometer. Cu Kα radiation was used as the source and samples were investigated over an angle range of o with 0.01 o step size and 1 s time per step. The voltage and current settings were 45 kv and 40 ma respectively. In the glancing scan XRD analysis, the angle of source from the sample surface if fixed at a lower value (1 o in this case) while the detector scans across an angle range (5-100 o ). In a θ-2θ geometry scan, the angle of incidence is always equal to the angle of exit. Hence, at higher angles to detect higher plane reflections, the penetration depth of X-rays may be greater than the thickness of the film being characterized resulting in unwanted substrate peaks and noise. Glancing angle XRD reduces the penetration depth to a great extent. It also provides larger signal interaction volume for the same penetration depth compared to θ-2θ scan. Raman analysis - Raman spectra were recorded using a Raman spectroscopic system, Horiba Jobin Yvon T64000, in backscattering geometry. The nm laser line of the helium-cadmium continuos wave laser (Kimmon Koha Co., Ltd. IK G) at a power of 83 mw was used for the excitation at an acquisition time of 1 min. The signal was analyzed with a thermoelectrically cooled CCD camera. Rutherford backscattering spectrometry (RBS) - RBS was performed using a 2.0 MeV He + + ion beam at a tilt of 8 o in General Ionex Tandetron accelerator. A tilt of 50 o was used as well to improve the depth resolution and verify the Cu distribution in the film. A computer program RUMP was used to simulate RBS spectra REFERENCE. Secondary ion mass spectrometry (SIMS) - SIMS was done in a Cameca IMS 3f magnetic-sector SIMS instrument. O ions at 17 kev and 50 na ion current were used as the primary ions since their application minimizes the charging problems in the SiO 2 films. Positive ion mass spectra and depth profile were obtained. The depth scale of the 58

71 depth profile was determined from Tencor stylus profilometer linescan measurements across the sputter crater. 3.3 Results The results from the SIMS analysis obtained from two samples, one annealed at 560 o C for 2 hours and the other at 720 o C for 15 mins are shown in Fig The concentration in atomic percent plotted in the y-axis of the figure is calculated from the raw data of counts/sec. The calculation is based on the assumption that the ion yield of Cu + and heavily oxidized silicon is approximately the same (within a factor of 5). Based on that 100 counts/sec of Cu + signal corresponds to 15 ppm of Cu. There is approximately three orders of magnitude difference in the amount of diffused Cu for the two temperatures studied: approximately 1 at.% at 720 o C and around 10 3 at.% for at 560 o C. The gradual variation in the profile towards the surface is an indication that the interdiffusion starts even during the time of the copper film deposition. The spectra follows the standard Cu + 63 and Cu+ 65 isotope ratio nicely[50]. Fig. 3.3 shows the RBS spectra Figure 3.2: SIMS profiles of Cu in SiO 2 films for different diffusion conditions 59

72 taken from Cu doped SiO 2 /TiN structure shown in Fig The Cu diffused in the SiO 2 film after annealing at 560 o C could not be detected in this experiment since it is below the sensitivity limit of the technique. For the sample annealed at 720 o C, two separate spectra were obtained. One with the incident beam at 90 o angle and the other at 50 o angle. The 50 o angle analysis revealed a peak which was otherwise masked in the 90 o angle analysis. Based on comparison with simulated graphs, it can be suggested that the peak near channel 350 is from Cu accumulation at SiO 2 /TiN interface. The signal near channel 430 reveals a surface nature, since it didn t show any significant shift in the x-axis after a tilt in the incident beam. It can attributed to Cu near the surface. As seen from the SIMS data in Fig. 3.2 the concentration of diffused Cu drops by almost an order of magnitude within a depth of 100 nm into the film. This could be the reason why presence of Cu in the film (other than the surface and the bottom interface) is not being detected in the RBS data even at the higher temperature anneal. Fig.3.4 shows the XRD data collected from these samples. The peaks characteristic of all the participating elements and compositions can be seen. However, the important thing which can be observed are peaks of crystalline Cu which are the only peaks related to this element, i.e., these results show that Cu remains in the elemental form after the thermal doping process. Supplementing the SIMS data, the intensity of the peaks which corresponds to Cu concentration in the SiO 2 matrix increases with increasing temperature. The Raman results shown in Fig.3.5 shows the dependence of the film characteristics upon the annealing conditions. The Raman mode intensity characteristic for the SiO 2 film decreases with increasing annealing time or temperature and no new features occur with the extension of the annealing conditions. There is a strong decrease in the Raman activity with temperature caused by annealing at 660 o C. A similar decrease is seen for the 560 o C processed sample when annealed for 2 hours. The band near 440 cm 1 arises from the symmetrical stretching modes of Si-O-Si bonds principally 60

73 (a) (b) Figure 3.3: RBS spectra of Cu-doped films a). After annealing at 560 o C for 2h. b). After annealing at 720 o C for 15 min. 61

74 Figure 3.4: X-ray diffraction data from sample with no thermal annealing of Cu and samples in which thermal doping was done at 560 o C for 2h and 720 o C for 15 min respectively involving motion of the oxygen atom. The broad range of this intertetrahedral angle (from 120 o to 180 o, with a most probable value of 144 o ) is seen in the broadness of the band at 440 cm 1 [51]. The peaks seen near 510 cm 1 and 640 cm 1 were initially attributed to defects due to broken bonds or wrong bonds [52]. However, when models were considered which go beyond the short range order of intratetrahedral and intertetrahedral angles, an intermediate range order consisting of closed rings of atoms emerged [53]. These bands could then be attributed to three- and four- membered ring structures embedded in the network[54]. There are some weak features at higher wavenumbers which are not presented here because of their low relevance and clearer presentations of modes at lower wavenumbers. Cu is not expected to appear on these spectra since its Raman silent but its presence in the films can be inferred from the reducing Raman activity of the hosting film due to its increased conductivity because of the Cu inclusion[55]. If Cu oxidation occurred during the annealing process, features could be expected in the cm 1 region[56]. 62

75 (a) (b) Figure 3.5: Raman spectroscopy data for a Cu-doped SiO 2 film for different doping conditions a). 560 o C for 15 min, 1h and 2h and b). 1 h at 560 o C, 660 o C and 720 o C. 63

76 3.4 Discussion The SiO 2 film used in the fabrication of the PMC devices and the material characterization experiments were grown by e-beam evaporation. The very nature of the process of physical vapor deposition results in a disordered structure resulting in voids in the SiO 2 network. Propagation of defects from the underlying film, either polycrystalline W or polycrystalline TiN, can also aid in the creation of the voids. Compared to that a thermal oxide grown on single crystalline Si has much lesser number of defects, which is why its a good gate insulator in MOS transistors. Cu has a relatively high diffusivity in SiO 2 and isotope tracking analysis shows that it can penetrate far into an SiO 2 film[57]. The latter study also shows that Cu can move bidirectionally (in and out of the oxide film) which is an indication that it does not chemically react with SiO 2 matrix. This is in good agreement with the RBS data presented here which shows the presence of Cu at the SiO 2 /TiN interface as well as near the Cu in the SiO 2 film. A similar distribution has also been reported by Sun et.al.[58]. Temperature related changes of silicon oxides has been studied in detail by Kopylov et. al. [59]. It has been found that by increasing the temperature there is higher efficiency in transformation of vibrational (thermal) excitation into electronic excitation. Electronic excitation is equivalent to loosening of bonds. Eventually, an accumulation of these electronically excited states has been observed which results in an additional energy reservoir favorable for the diffusion process at increased temperatures. Moreover, the dynamic exchanges in the structure of the hosting SiO 2 film leads to formation of films with increased porosity. It is for this reason, and the others given above, that the Cu diffusion is significanlty accelerated at higher temperature. Evidence of this increased diffusivity is seen in the Raman spectra where at increased annealing time and temperature the intensity of the Raman modes decreases due to the higher conductivity of the material with higher metal concentration. Another factor to be considered when dealing with a multilayer film and high 64

77 temperature doping is thermal stress and residual strain-induced effects. An interesting study, by Dallaporta et.al.[60], noted that the void formation rate in SiO 2 with a Cu metal film deposited on top increases with increase in temperature. In other words, presence of a metal film enhances the void formation rate compared to a bare SiO 2 film. In general due to the difference in the thermal expansion coefficients of the different films in the stack, significant stresses are expected to occur in the hosting medium. The slight shift of the Raman modes in Fig. 3.5 compared to the relaxed SiO 2 [51] is an indication of the strain occurring in the material. Stress- or point-defect relaxation can occur at any of the studied temperatures and this is an additional reason for the enhancement of the diffusion process. The study by Pan et.al. [61] shows an enhanced precipitation of Cu nanoparticles in SiO 2 after high temperature annealing in areas were compressive and tensile stress was induced with the help of indentation on the surface. They noted an optimum temperature of 600 o C as the annealing temperature for enhanced Cu nanoparticle precipitation. The Raman analysis results presented here show a drastic decrease in the intensity of the Raman breathing modes after annealing at 660 o C compared to those annealed at 560 o C. This is quite possibly due to the enhanced Cu diffusion and precipitation in this temperature regime. From the XRD results, it can be seen that Cu does not react with the constituents of the SiO 2 network and remains in elemental form when diffused into the SiO 2 film. The lack of formation of CuO or other oxides, silicates or silicides was also demonstrated in the Raman spectra. The results are in good agreement with the data reported by Dallaporta et.al[60]. The results contradict the data described by Cao et. al. who suggest the formation of Cu 3 Si in their study of the diffusion processes in the Cu/SiO 2 /Si system at temperatures over 450 o C. It is possible that their result is a consequence of Cu, due to its high diffusivity in SiO 2, has reached the SiO 2 /Si interface as discussed earlier and forms silicides by reacting with pure Si. At this point, the the primary switching threshold variation results presented in 65

78 Fig and Fig can discussed in more detail. As noted above, annealing at higher temperatures results in much more Cu being introduced into the SiO 2 due to the larger number of voids formed compared to the lower temperature annealing cases. The enhanced Cu nanoparticle precipitation observed above 600 o C by [51] and shown by significant reduction of the Raman intensity modes presented in Fig.3.5, points towards an optimum condition of Cu concentration within the SiO 2 matrix which seems to reflect as less variation in the primary switching threshold of the devices annealed at 660 o C. This is believed to be close to an optimum condition for solid electrolyte formation in the Cu-SiO 2 PMC devices. In the lower tempearature annealed sample, the less than optimum concentration of the Cu nanoclusters along with comparatively lesser porous structure are believed to be the reason for the higher primary switching threhsolds. The chemically stable but open structure facilitates the transport of Cu ions to form a complete electrodeposit link between the two electrodes. However, it does not create conditions for the chemical stabilization of Cu as oxide within the glassy structure. The fact that Cu does not form chemical bonds with the SiO 2 host could be the main reason for the fluctuations in the switching threshold between different devices obtained for the same programming conditions and during multiple sweeps, as the unbound Cu can readily be thermally (during processing) or electrically (during programming) redistributed within the film. The decrease in the average switching threshold voltage with consecutive sweeps, particularly evident in the case of the samples annealed at 560 o C which have the lowest initial (as-processed) Cu content, could very well be indicative of a type of conditioning effect. Such a large drop in threshold voltage is not seen in the samples which have been annealed at the highest temperature and therefore have the highest as-processed Cu content. The electrical conditioning which leads to the drop in threshold voltage is due to the net addition of Cu during cycling (fewer Cu ions are removed from the SiO 2 during the erase than are introduced 66

79 during the write), so that the Cu concentration is brought closer to an equilibrium level with increasing sweep number. The samples annealed at higher temperature are already closer to this equilibrium level following processing and therefore do not exhibit such a strong threshold effect. The presence of devices which exhibit symmetrical unipolar switching after annealing at higher temperatures as shown in Fig can be understood by considering the RBS results shown in Fig This is related to the fact that in some instances, Cu diffuses across the entire thickness of the SiO 2 film to the SiO 2 /W interface, thus forming a symmetrical Cu-SiO 2 -Cu structure which leads to programming or erasing in either direction. 67

80 Chapter 4 Inherent isolation in PMC Section 1.3 discussed the importance of the passive memory arrays based on a crossbar architecture for scaling non-volatile memories in the sub-20 nm regime. Two approaches at the individual cell level to implement such an array would be to fabricate a diode (isolation element) and the memory cell in series or to have a memory cell with inherent isolation characteristics. The latter being the simpler approach from a fabrication point of view. Also, a generally accepted view was that the memory element has to show unipolar switching characteristics. A series diode with a high reverse resistance would not allow a sufficient bias across the memory element to permit the erase operation with negative polarity (bipolar operation). PMC devices can be switched between the two resistance states in unipolar operation as seen in section 2.3. However, that would typically require a high current for erase, thus increasing the power requirements of an array. 4.1 Discrete zener diode isolation To be able to switch the memory element in a passive array in the bipolar mode, it is therefore necessary to use a Zener or a soft-breakdown diode with reverse-bias breakdown voltage in the range of 5 V or lesser. The basics of the breakdown and the current transport mechanism in such diodes has been discussed in section 1.4. To assess the viability of using a bipolar device with a series diode, a discrete Zener diode with a -3.3 V reverse breakdown voltage was connected in series with a well-characterized Ag/Ag-Ge-S/W cell[23] and the I-V plot for this combination is given in Fig As is evident from the plot, the device switches to its compliance current-limited written state at nearly 1 V, which is considerably higher than the 450 mv write threshold without the diode. Thus its evident that the turn-on voltage of the diode leads to the increase in the device switching threshold. Once the device is written, the series combination shows the forward bias diode characteristics (region 5). As expected, even though the device 68

81 Figure 4.1: Current-voltage plot for a series combination of a Ag/Ge-S/W memory cell and a discrete Zener diode. is in its low resistance state, the current flow under negative bias is small (<10 na at -1.5 V) due to the influence of the diode but rises rapidly when the bias approaches its breakdown voltage at -3.3 V, at which point the diode conducts and the memory cell switches to its high resistance state. This series combination could be written at 1 V and read between the knee voltage of the diode and the programming voltage (e.g., at 0.7 V) so that the off- and on-states may be readily distinguished without disturbing the off-state. The above result indicates that a separate Zener diode can be used to provide current blocking at low voltage, i.e., at the voltages used for writing or reading devices, but will still allow the erase operation to occur at higher bias. The next step was to create a built-in diode as part of the cell and this involved a modification to the inert electrode material. Specifically, n-type silicon (n-si) rather than tungsten was used as the bottom electrode (cathode) in a Cu/Cu-SiO 2 /n-si device to produce a rectifying effect. The proposed principle was simple; the interface between the Cu filament in the on-state of the PMC device and the n-si electrode would 69

82 Cu Cu-SiO2 Al n-si n-si n-si Figure 4.2: The schematic of a Cu/Cu-SiO 2 /n-si Programmable metallization cell. The inset shows the schematic view of the Cu filament formed after WRITE step. constitute a Schottky diode with soft reverse breakdown without the need for additional device layers. Based on that principal the breakdown voltage of such a Schottky diode would be influenced by the doping concentration of the n-si bottom electrode. The intent was not to create a crossbar array at this time but to assess the feasibility of this approach and characterize the diode element formed. Fig. 4.2 shows a schematic of the device with the proposed Cu filament forming an interface with the n-si shown in the inset. 4.2 Device Fabrication The devices fabricated had a material stack, Cu-SiO 2 -nsi with the Cu film as the top electrode and the n-si as the bottom electrode. Two batches of samples were fabricated, Batch A with the bottom electrode doping density in the range of cm 3 and Batch B with a bottom electrode doping density in the range of cm 3. The fabrication sequence is as follows: 1. Dielectric growth nm of SiO 2 was grown on the Si substrate by wet oxidation process in a furnace. The dielectric would serve as the isolation between devices or the contact pads. 2. Via patterning and etch - A 1 µm AZ 3312 resist was spun and exposed under a via mask in 5 mw/cm 2, 436 nm UV light. The resist was then developed using 70

83 an AZ 300MIF developer. The via patterns were transferred into the dielectric by a wet etch process in 6:1 buffered oxide etchant solution. The left-over resist was not removed at this stage. The via dimension ranges from 2 µm 2 µm to 10 µm 10µm. 3. Film deposition - A 15 nm thick SiO 2 and 30 nm thick Cu film was deposited by a thermal evaporation process in a Torrvac e-beam evaporator. The deposition conditions were similar to that of the Cu/SiO 2 /W PMC s. 4. Lift-off patterning - The wafer was dipped in Acetone which removes the resist which was left-over after developing in step 3. When the resist is removed, the SiO 2 and Cu gets removed as well from all regions except the vias. 5. Top electrode patterning - A lithography process similar to step 2 was carried out using a mask for the top electrode pads. The pad patterns were aligned to the vias. The presence of the Cu metal film inside the vias give enough contrast for the via to be seen under the microscope and thus helps in the alignment with the pads. 6. Film deposition and patterning - 30 nm thick Cu film was deposited by a similar thermal evaporation process and it is expected to form a continuos conducting film with the Cu already existing inside the vias. The pads were patterned by a lift-off process in acetone. 7. Thermal doping of SiO 2 - The 15 nm thick SiO 2 film which is the active area for the device structure is doped with Cu by annealing the samples at 660 o C for 15 min. The annealing was done in a flowing N 2 ambient in a Lindberg funrace and the top Cu film was protected from oxidation damage by depositing a passivation SiO 2 layer. The passivation layer was removed by a wet etch process after the annealing step. 71

84 8. Contact to n-si bottom electrode - The SiO 2 dielectric from the edge of the samples were etched off using a 6:1 buffered oxide etchant based wet etch process to expose the bottom n-si substrate. Al was then deposited in this exposed region using a shadow mask to give a good contact to the bottom electrode. Two control samples A and B were also fabricated. The control samples had Cu film directly deposited on top of the n-si substrate in the vias. So, effectively the control samples are Cu-Si metal-semiconductor interfaces with an interface area determined by the via dimensions mentioned before. These samples were made for comparison of the leakage characteristics with the actual device samples. The control sample A had the highly doped n-si substrate and the control sample B had the low doped n-si substrate. 4.3 Device characterization setup The devices were characterized in a similar setup to that of the Cu/SiO 2 /W PMC devices, in a probe station connected to an Agilent 4155C semiconductor parameter analyzer. Separate WRITE (0 to 6.5 V and back to 0 V), READ (500 mv) and ERASE (0 to -6.5 V) sweeps were used to record the switching characteristics. During the WRITE sweep and READ operation, the Cu top electrode was positively biased compared to the n-si bottom electrode and vice versa during the ERASE sweep. The compliance current (programming current) setting in the 4155C was used to limit the current passing through the device after the device was written. Measurements were made at 5 o C, 15 o C, 25 o C and 35 o C. 4.4 Results and discussion Switching characteristics Fig.4.3 and Fig.4.4 shows typical WRITE and ERASE switching characteristics of two Cu/Cu-SiO 2 /n-si based cells with the two different n-si bottom electrode doping densities (Batch A and Batch B) measured at room temperature. The voltage sweep direction and sequence of events are shown by numbered arrows. In Fig.4.3a and Fig.4.4a, both devices are initially in their high-resistance state (R E ) in region 1 of the WRITE sweep. 72

85 Figure 4.3: Switching characteristics (current vs voltage) of Cu/Cu-SiO 2 /n-si devices with two different doping densities for the bottom electrode. (a) 0 V V WRITE sweep (b) 0 V - (-6.5 V) ERASE sweep. 73

86 Figure 4.4: Switching characteristics (resistance vs voltage) of Cu/Cu-SiO 2 /n-si devices with two different doping densities for the bottom electrode. (a) 0 V V WRITE sweep (b) 0 V - (-6.5 V) ERASE sweep. 74

87 As shown in Fig.4.4a, R E for the Batch A device is in excess of 10 8 Ω and the Batch B device has R E above Ω (which is above the limit of the measurement apparatus). The higher R E for the devices in Batch B is due to a combination of factors such as a higher series resistance due to the lightly doped electrode and also a larger barrier for electron tunneling at the SiO 2 /Si interface. The band bending at the interface is expected to be higher for the highly doped n-si substrate, resulting in a narrow barrier for electrons to tunnel and leading to a lower resistance. The switching to the lowresistance state is seen at region 2. The initial switching threshold (V t ) is in the order of 3.75 V and 3.25 V for the Batch A and B devices, respectively. The V t values did not show any significant trend between the two sets of samples and the recorded values from multiple devices typically lay within a ±10% range from a mean value. Similar variation, albeit at a lower threshold voltage, was observed in Cu/Cu-SiO 2 /W based cells as shown in Fig.2.14 and is believed to be due to variations in free Cu concentration in the SiO 2 matrix. The programming (compliance) current limit (I prog ) in both cases was 50µA and the current through the devices remains at this value in regions 3 and 4, indicating that the memory cells are in their low resistance state (R F ). The actual value of R F is masked by the current limit circuitry in the semiconductor parameter analyzer, which manifests itself as the rising R-V curves at higher voltage in the inset. However, the lowest R F values observed were around 10 kω and 50 kω for the heavy and light doped Si cases respectively, more than four orders of magnitude lower than R E. Region 5 is where the voltage drop across the devices is low enough to cause the current to decrease below the compliance limit. Both devices show distinctly nonohmic characteristics in this region, which is quite different than the Cu/Cu-SiO 2 /W device of Fig.2.8, which shows ohmic characteristics for the on-state due to the metal bottom electrode. These non-ohmic I-V characteristics are expected in a rectifying contact and also add an additional series resistance component, which doubtless leads to the higher R F in the lightly-doped Si case. During the ERASE sweep, the devices 75

88 behave like a rectifier in reverse bias, a further indication that an inherent diode structure has been formed in the on-state. The rectification action can be seen in region 6 in Fig 4b. The Cu/Cu-SiO 2 /W device in Fig.2.8 shows no such current blocking in the equivalent region. Rectification ratio One of the desired characteristics for a diode in a passive array, as mentioned in section 1.4, is the rectification ratio. From Fig. 4.4, this ratio is on the order of 10 4 for V = 500 mv for the Cu/Cu-SiO 2 /n-si based device from Batch A. The Batch A device begins to conduct in region 7 and then switches back to the high resistance state at region 8 in a similar fashion to the discrete Zener diode case shown in Fig. 4.1 but in this case, the ERASE voltage is closer to V. Note that R E for a negative bias beyond the ERASE voltage is in the order of 10 7 Ω. This value is lower than the forward bias R E, measured at around 500 mv, due to the leaky nature of the off-state device at these relatively high voltages. Interestingly, the Batch B device does not conduct under negative bias and a transition to its high resistance state is not observed over the voltage range used (this will be discussed in more detail later). The rectification observed in these devices can be understood by considering the switching mechanism in a Cu-based PMC device. In a Cu/Cu-SiO 2 /W device, the low-resistance state formed by the electrodeposition of a Cu filament results in a Cu-W contact at the lower electrode which leads to the observed ohmic characteristics in Fig.2.8. However, in the case of the n-type Si device, a metal-semiconductor junction is formed at the bottom electrode. The forward-bias characteristic of a device from the Batch A after the Cu electrodeposit is formed, as shown in Fig. 4.5, reasonably fits the Schottky diode equation with a non-ideality factor n of The decrease in the current from ideal can be observed at voltages of around 300 mv and higher, and is most likely due to the series resistance in the circuit. The series resistance extracted from this difference in current is approximately 4 kω, which is in the range of the expected on-state resistance (filament resistance) of the 76

89 Figure 4.5: Forward-bias curve obtained from a Cu/Cu-SiO 2 /n-si device after forming the filament with a WRITE sweep. The curve is fitted to an ideal-diode equation with a non-ideality factor, n device for the programming current used (Fig.2.11). During the ERASE sweep, the device from Batch A behaves like a reversebiased Schottky diode. The increase in current for higher negative bias voltage resembles the soft breakdown characteristics shown by Schottky devices on highly-doped semiconductors. The substrate doping density is in the range of cm 3 for which the onset of soft breakdown is expected at around 3 V[5] which is consistent with the results shown in Fig. 4.3b. Based on this, we propose that the current in this regime is mainly due to tunneling of electrons across the metal-semiconductor barrier leading to the soft Zener breakdown. When the current and resultant voltage drop across the cell is sufficiently high, the dissolution process of the electrodeposit is initiated. This erase process is believed to be similar to that of a metal bottom electrode device but occurs at a much larger voltage due to the influence of the reverse-biased Schottky junction which limits the current flow until it breaks down. However, once the electrodeposit is dissolved, the diode is disassembled and the device behaves as a normal PMC 77

90 element in its off-state. The reverse breakdown voltage for the n-si electrode that was doped to cm 3 is expected to be in excess of 100 V [5]. Consistent with this, the Batch B devices showed very low conduction in reverse bias and no breakdown characteristics were observed up to -40 V (the maximum that could be applied due to equipment limitations). This high breakdown voltage is the reason these devices could not be erased in the same voltage range as their more heavily-doped counterparts. The rectification ratio was not measured in this case as the conduction at -500 mv was below the resolution limit of the equipment but it was clear that the rectification ratio was much higher than that of the Batch A devices. The voltage sweep switching characteristics shows the significance of the doping concentration of the bottom electrode. An obvious conclusion is higher rectification ratio with lower doping in the bottom electrode, leading to better leakage characteristics (discussed in detail in the following sections). However, the compromise as seen here is the erase voltage in the bipolar switching operation. In the extreme case, of very low doped substrate which is shown here, it seems to be impossible to erase the device at reasonable values of negative voltage. In such cases, the device would be limited to a one-time programmable cell for bipolar operation, similar to a memory cell in series with a non-zener type diode with very high breakdown voltage. Filament resistance Fig. 4.7 shows a simple circuit model of the erased and written states of a Cu/Cu- SiO 2 /n-si memory cell. As mentioned before the Cu electrodeposit filament resistance shows up as a series resistance in the I-V characteristics of the written device, shown in Fig.4.5, from a diode point of view. However, from a memory cell point of view, this series resistance or the filament resistance (R F ) is the resistance we would like to measure to detect the written state. Hence, its important that the read voltage be high enough so that its comfortably in the region not limited by the diode forward-bias 78

91 Figure 4.6: The resistance of a written device from Batch A measured at different read voltages, showing the diode dominated and filament resistance dominated regime. characteristics. Fig. 4.6 shows the apparent values of R F measured at different read voltages for multiple devices. It can be seen that for voltages below 500 mv or so, R F varies exponentially (linear in log plot) with the read voltage which is similar to that of a diode behaviour. So, in this region the current conduction is dominated by the forward-bias sub-threshold characteristics of the diode element. Any effort to read the written state in this region will give abnormally high values of resistance, which in extreme cases could even result in detecting a high resistance state when the device is actually in the low resistance state. The variation tends to approach linearity for voltages greater than 500 mv or so and the R F values measured in this regime is in few tens of kilo ohms. This is the expected range of resistance of the filament as observed in a Cu/SiO 2 /W based PMC which shows purely ohmic characteristics. Leakage characteristics Referring to Fig.4.7 in the erased state, the off-state resistance R E is determined by the Cu-doped SiO 2 electrolyte and its interfaces with the electrodes. R E will generally scale as the inverse of the device area which is determined by the size of the via in the dielectric. In the written state, R E is still present but it is now in parallel with the 79