CONTINUOUS-TIME sigma-delta (ΣΔ) modulators

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1 506 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 61, NO. 7, JULY 2014 General Analysis of Feedback DAC s Clock Jitter in Continuous-Time Sigma-Delta Modulators Alexander Edward, Student Member, IEEE, and Jose Silva-Martinez, Fellow, IEEE Abstract This brief describes a framework for the analysis of continuous-time sigma-delta (ΣΔ) modulators (CTSDM) in the presence of a feedback digital-to-analog converter (DAC) s clock jitter using the discrete-time Volterra series. A time-domain mixing operation between jitter and CTSDM s digital output sequence is modeled with a second-order Volterra operator. The resulting closed-form jitter-induced CTSDM s output power spectral density is simple and includes the effects of the following: 1) quantization noise power; 2) input signal power and frequency; 3) CTSDM s quantization noise transfer function; 4) DAC s pulse shape; and 5) colored jitter. A third-order CTSDM is analyzed as a test bed. Excellent agreement between theoretical predictions and behavioral simulations is observed. Index Terms Analog-digital conversion, jitter, nonlinear network analysis, sigma-delta (ΣΔ) modulation, Volterra series. I. INTRODUCTION CONTINUOUS-TIME sigma-delta (ΣΔ) modulators (CTSDMs) have emerged as a popular choice for implementing analog-to-digital converters (ADCs) for wireless applications [1]. Their inherent alias rejection, ease of programmability, and oversampling potentially reduces the system cost, complexity, and power consumption. To take full advantage of these properties, CTSDM must be able to process more hostile input signal compared to that of conventional Nyquist ADC with anti-alias filtering. On the other hand, CTSDM is known to be more jitter sensitive compared to its discrete-time counterpart [2], [3]. CTSDM s feedback digital-to-analog converter (DAC) s clock jitter mixes with quantization noise and strong interferers, the reducing system s sensitivity [4]. In this brief, we present a unifying procedure to obtain jitterinduced CTSDM s output power spectral density (PSD) using a discrete-time Volterra series. A systematic methodology is proposed to quantify DAC and loop filter s jitter sensitivity by computing their jitter impulse response (JIR). This results in a compact closed-form PSD expression that extends the results of previous works [2] [8] typically done for specific assumptions in modulator s topology and clock jitter s spectrum. The results derived here are general and found to be accurate for both inband and out-of-band computations. This brief is organized as follows. Section II provides the rationale behind the procedure using discrete-time Volterra series analysis. Section III applies the procedure to a third-order Manuscript received March 28, 2014; accepted May 26, Date of publication May 29, 2014; date of current version July 16, This brief was recommended by Associate Editor L. H. Corporales. The authors are with the Analog and Mixed-Signal Center, Texas A&M University, College Station, TX USA ( aedward26@tamu.edu; jsilva@ece.tamu.edu). Color versions of one or more of the figures in this brief are available online at Digital Object Identifier /TCSII Fig. 1. Frequency-domain model of CTSDM with rectangular pulse DAC [includes both non return-to-zero (NRZ) and return-to-zero (RZ) DAC]. CTSDM and compares its results to behavioral simulations. Section IV concludes this work. II. CTSDM JITTER ANALYSIS Fig. 1 shows a mathematical model of CTSDM as a starting point of our analysis. The output bitstream d out [n] represents sampled values of the loop filter s output v lf [n] added with white quantization noise q[n]. This digital output is translated into its continuous-time version by the DAC. The error between CTSDM s input v in (t) and DAC s output v dac (t) is processed by the loop filter, which provides correcting input to the quantizer. Because of a periodic sampling operation in the loop, the feedback operates in discrete time with period T s. Thus, the feedback path containing the quantizer s latency, DAC, loop filter, and sampler can be replaced by an equivalent discretetime transfer function H(z) [9] given by H(z) =z 1 (1 z 1 H fb (s) ) (1) st s n= s=j(ω nωs ) for the special case of CTSDM with one clock cycle latency (γ =1)and NRZ DAC (α =0and β =1). (See Fig. 1.) The infinite series in (1) is the impulse invariant transformation for H fb (s)/(st s ) [10]. This transformation enables designers to analyze CTSDM using linear z-domain loop analysis to obtain the quantization noise transfer function (NTF). Correspondingly, the in-band quantization noise power N 2 q can be computed as a function of NTF, quantization noise power Q 2, and oversampling ratio (OSR) of the CTSDM. We will show that similar loop analysis can be performed to obtain the jitter transfer function (JTF) and its corresponding PSD using the discrete-time Volterra series. In this way, the analysis is flexible and can accommodate any changes in modulator s topology. A. Jitter Impulse Response (JIR) of CTSDM Here, we examine the physical process in which jitter affects CTSDM s time-domain behavior. Let us define jitter j[n] as a IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 EDWARD AND SILVA-MARTINEZ: GENERAL ANALYSIS OF FEEDBACK DAC S CLOCK JITTER IN CTSDMs 507 Fig. 2. Fig. 3. Time-domain representation of NRZ DAC with jitter. Setup to obtain JIR of CTSDM s loop filter with NRZ DAC. discrete-time sequence of clock transitions timing errors. It is normalized by the clock period T s. In NRZ DAC, jitter varies the position of DAC s output pulse transitions in a random manner. In Fig. 2 we express NRZ DAC waveform v dac (t) as the superposition of the ideal and error waveforms without a loss of generality. This error waveform e(t) takes the shape of a rectangular pulse train. The pulse s width and amplitude are proportional to jitter j[n] and output bitstream s transition d out [n] d out [n 1], respectively, which are discrete-time quantities. It can be mathematically represented as e(t) = n= (d out [n] d out [n 1]) j c (t, n) (2a) j c (t, n) =u (t + j[n]t s nt s ) u(t nt s ). (2b) Because the loop filter is a linear time-invariant (LTI) system, its response to the error waveform e(t) can be analyzed independently of the main signal. Let us calculate the response of a first-order low-pass filter to a single error pulse j c (t, 0). Fig. 3 shows the setup of this thought experiment. Since the loop filter s output is sampled, we are only interested in the waveform at the sampling instance v lf,j (t)= {( 1 e ω p T s j[n] ) e ω pt u(t) j[n] 0 ( 1 e ω p T s j[n] ) e ω pt u(t T s ) j[n]<0. Applying a Taylor series expansion to 1 e ω pt s j[n] in (3), we see that timing disturbance is similar to the case of nonlinear amplitude disturbance. Assuming that jitter is much smaller than the loop filter s time constant, this timing to amplitude conversion looks linear. It can also be shown that this argument is valid for most practical loop filter transfer functions. The loop filter s error response v lf,j (t) can therefore be normalized to jitter j[n]. The sampled version of this normalized response is termed as the jitter impulse response (JIR) of the CTSDM. The z-transform of JIR for common loop filter transfer functions is given in Table I for NRZ/RZ DAC. This is useful for computer-aided design (CAD) applications in which the loop filter s parasitics need to be considered. JIR for DACs whose waveforms can be analyzed using impulse invariant transform can also be obtained. For example, consider the switched-capacitor resistor (SCR) DAC with (3) falling edge clock jitter (around βt s ) [11]. The jitter error pulse in (2b) can be replaced by j c (t, n)(scr DAC) =e ω scr(t αt s ) (u(t βt s nt s ) u(t + j[n]t s βt s nt s )). (4) The Laplace transform of (4) can be substituted by the block Jitter Pulse shown in Fig. 3. It can be shown that JIR(z)NTF(z), a metric for DAC and loop filter s jitter sensitivity that will be discussed later, is approximately ω scr T s e ω scrt s (β α) for SCR DAC and the integrator type loop filter. Using the approach discussed here, it is possible to reobtain the entries in Table I for SCR DAC. B. Discrete-Time Volterra Series Analysis From a theoretical point of view, JIR allows us to perform linear timing to amplitude error conversion at the sampled loop filter s output. The resulting model incorporating JIR is shown in Fig. 4 for CTSDM with NRZ DAC. The feedback path is discretized in time and is broken into ideal and jitter feedback paths. DAC s characteristic is modeled by a transfer function D(z), which has a value of 1 z 1 for NRZ DAC and 1 for RZ DAC. For RZ DAC, the model in Fig. 4 can be changed by modifying D(z) and adding an additional jitter feedback path due to falling edge clock jitter. For finite-impulse response (FIR) NRZ/RZ DAC [12], instead of adding jitter feedback path for each DAC, D(z) can be modified by multiplying the original D(z) by the FIR s transfer function. This assumes all the DACs see equal jitter. We postulate that the CTSDM s digital output bitstream can be represented using a discrete-time Volterra series as d out [n] = ntf[k 1 ]q[n k 1 ] k 1 = + jtf qj [k 1,k 2 ]q[n k 1 ]j[n k 2 ] (5) when the input signal is nulled. The second-order Volterra kernel jtf qj [k 1,k 2 ] represents the mixing between jitter and quantization noise. Once it is found, CTSDM s output autocorrelation and PSD due to this mixing can be calculated. Similar to the derivation in [13] in which the output PSD of second-order nonlinear continuous-time system due to white noise is determined, we derive the CTSDM s output PSD due to jitter mixing with quantization noise given by Φ qj (ω)= 1 π π JTF qj (Ω,ω Ω)Q(Ω)J(ω Ω) 2 dω (6) where JTF qj (z 1,z 2 ) is the 2-D z-transform of the secondorder Volterra kernel jtf qj [k 1,k 2 ] given by JTF qj (z 1,z 2 )= jtf qj [k 1,k 2 ]z k 1 1 z k 2 2 (7) where z 1,2 = e jω 1,2T s, ω =(ω 1 + ω 2 )T s, and Ω=ω 1 T s. Before we proceed, consider the generalized jitter feedback path in Fig. 5 where c[n] is added to model colored jitter.

3 508 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 61, NO. 7, JULY 2014 TABLE I Z-TRANSFORM OF JIR FOR CTSDM WITH NRZ/RZ DAC which can be solved by substituting the postulated solution in (5). Equating terms containing q[n k 1 ] and applying the z-transform, we obtain the NTF of CTSDM. Equating terms containing q[n k 1 ]j[n k 2 ] and applying the 2-D z-transform, we obtain the JTF of CTSDM given by JTF qj (z 1,z 2 )=JIR(z 1 z 2 )NTF(z 1 z 2 )NTF(z 1 )D(z 1 )C(z 2 ). (11) Fig. 4. Frequency-domain model of CTSDM with NRZ DAC including jitter. Substituting (11) into the PSD expression in (6) for the case of NRZ DAC (D(z) =1 z 1 ), the CTSDM s output PSD due to jitter mixing with quantization noise is obtained as Fig. 5. Generalized time-domain model of the jitter feedback path in CTSDM. The output of the jitter feedback path can be written as v lf,j [n] = h j [k 1,k 2 ]d out [n k 1 ]j[n k 2 ] (8) where the second-order Volterra kernel h j [k 1,k 2 ] and its 2-D z-transform H j (z 1,z 2 ) are given by h j [k 1,k 2 ]= k= jir[k]d[k 1 k]c[k 2 k] H j (z 1,z 2 )=JIR(z 1 z 2 )D(z 1 )C(z 2 ). (9a) (9b) C. CTSDM s Output PSD Due to Jitter Quantization Noise Next, we write the time-domain equation for the CTSDM s model in Fig. 4 with zero input signal as d out [n] =q[n] + k 1 = h[k 1 ]d out [n k 1 ] h j [k 1,k 2 ]d out [n k 1 ]j[n k 2 ] (10) Shape of Φ qj (ω) {}}{ Φ qj (ω) =Q 2 J 2 JIR(ω)NTF(ω) 2 1 π 2 D(Ω) Colored Jitter {}}{{}}{ NTF(Ω) (1 e jω ) C(ω Ω) dω π }{{} Jitter Quantization Noise Penalty (12) where Q 2 is the quantization noise power and J 2 is the meansquared normalized jitter to clock period. DAC and loop filter s jitter sensitivity is represented by the term JIR(z)NTF(z) 2. Since it directly affects the shape of the PSD, it is a good metric to compare different DAC s pulse shape. For CTSDM with NRZ DAC, this metric is almost unity in-band since JIR(z) approximates H(z) for the high gain loop filter s transfer function (see Table I). We denote the last term as a noise penalty incurred by the mixing effect. For white jitter, this penalty is a constant given by the total area under NTF(z)D(z) 2. It can be minimized by either optimizing NTF(z) [6]or modifying D(z) [12]. For colored jitter, this penalty becomes frequency dependent. It can be determined by performing the convolution between NTF(z)D(z) 2 and C(z) 2. This result has been approximated in [2] and [5], and was experimentally verified in [14] for CTSDM with NRZ DAC and white jitter. The approximation in [5] has good accuracy for practical design purpose. Equation (12) is more general since it takes into account DAC s type and colored jitter.

4 EDWARD AND SILVA-MARTINEZ: GENERAL ANALYSIS OF FEEDBACK DAC S CLOCK JITTER IN CTSDMs 509 Fig. 6. CTSDM s signal path processing steady-state sinusoid input. Fig. 7. Modelling early/late effect into CTSDM s jitter feedback path. Fig. 8. CTSDM using third-order feedforward loop filter and 3-bit quantizer. H fb (s) = (( (s/ω o))/(s 2 + ωo 2 )) + (14/s) ω o =(π/16) (3/5) for OSR =16. D. CTSDM s Output PSD Due to Jitter Input Signal When an input signal is present, it can raise in-band noise floor due to the same mechanism in which jitter and quantization noise mix. The same analysis framework can be applied to this case by solving the time-domain equation for the CTSDM s model shown in Fig. 4 with zero quantization noise. Illustrated in Fig. 6, the sampled loop filter s output response for a sinusoid input is a discrete-time sinusoid v lf,ff [n]. We can replace Q(Ω) 2 in (6) by the PSD of v lf,ff [n] and solve for the CTSDM s output PSD due to jitter mixing with input signal, which yields Φ sj (ω) =A 2 J 2 JIR(ω)NTF(ω) 2 1 ( C(ω + ω o ) 2 + C(ω ω o ) 2) } 2 {{} Jitter Modulated by Input Signal STF(ω o ) D(ω o T s ) {}}{{}}{ H ff (ω o )NTF(ω o T s ) (1 e jω ot s ) 2 }{{} Jitter Input Signal Penalty (13) where A 2 = A 2 /2 and ω o are the input sinusoid s power and frequency. The penalty is now dependent on the input signal s frequency. In addition, low frequency jitter and clock spurs are visible as skirts around the input signal [8]. For NRZ DAC, D(z) =1 z 1 is a differentiator. The noise penalty is minimal for a low-input signal. This is not the case for RZ DAC where D(z) =1is unity. Intuitively, a large DC input signal V in,dc forces the RZ DAC to toggle between 0 and V in,dc, allowing jitter to leak to the loop filter. If low-frequency jitter is dominant and large in-band input signal is applied, we can see that the modulated jitter power will also be concentrated in-band. This is not the case for white jitter in which the noise is spread across the whole Nyquist band. These two cases can lead to large discrepancy to the observed in-band noise power [7]. E. Early/Late Jitter PSD Correction Note that early and late jitter can yield two different JIRs as indicated by Table I b. This phenomenon only affects CTSDM whose DACs are clocked almost exactly at the same time as the sampling time of the quantizer. Shown in Fig. 7, white jitter is broken into early and late jitter having half-normal distribution. Their auto and cross- Fig. 9. (a) NTF and JIR NTF. (b) STF and noise penalty ratio. correlation functions can also be calculated. Utilizing these results, we replace JIR(ω) 2 in (12) by JIR el (ω) 2 = ( ) 1/l JIR i (ω) /l JIR i (ω)jir 1 i(ω). (14) Because of the DC component in early/late jitter, the term in (15) should also be added to the PSD in (12). This DC component, when convolved with the input signal, produces a harmless tone at the input frequency Φ qjel (ω) =Q 2 J 2 JIR dc el (ω) 2 NTF 2 (ω)d(ω) 2 (15) JIR el (ω) 2 + JIR dc el (ω) 2 = 1 2 1/l JIR i (ω) 2. (16) III. EXAMPLE THIRD-ORDER CTSDM ANALYSIS The analysis procedure is illustrated for a third-order CTSDM with NRZ DAC whose schematic is shown in Fig. 8. The equivalent z-domain NTF and JIR NTFareplottedin Fig. 9(a). The NTF is expected to have 80.8 dbfs in-band quantization noise power with 3-bit quantizer. The penalty in (12) is determined to be 12.9 V 2 /V 2 or 11.1 db. The JIR includes the early/late effect. Designers can plot the ratio of penalty between jitter mixing with input signal (13) to that of jitter mixing with quantization noise (12) for white jitter. It is plotted in Fig. 9(b) for 0 dbfs input power and 3-bit quantization noise power. This ratio can also be plotted for the case when the input power is adjusted

5 510 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 61, NO. 7, JULY 2014 Fig. 10. Setup to extract CTSDM s output PSD due to jitter in which the loop filter and quantizer s output are postprocessed to cancel quantization noise. are used and the coefficient a is swept. A z-domain transfer function is placed before the quantizer during simulations to keep NTF constant. This might not be practical in practice due to STF peaking but nevertheless is useful for this discussion. We see that the agreement with theoretical prediction in (17) with modified D(z) is good. Note that J 2 =20mUI rms, which is 20 db higher than previous simulations to keep jitter-induced noise, dominates for a large value of a where improvement around 7.9 db is expected. IV. CONCLUSION The effects of feedback DAC s clock jitter in CTSDM are analyzed using a discrete-time Volterra series. CTSDM s jitter transfer function and PSD are derived. This method is flexible to changes in modulator s topology, DAC s pulse shape, and the colored jitter spectrum. A comparison between theoretical prediction and behavioral simulation results validates accuracy of the proposed analysis. Fig. 11. (a) Simulated CTSDM s output PSD for ideal and with white jitter (J 2 =2mUI rms). Extracted CTSDM s output PSD due to jitter for (b) inband and (c) out-of-band input showing in-band noise level of 74.7 dbfs and 65.6 dbfs, respectively. (d) Simulated CTSDM s in-band noise level versus FIR DAC coefficient a with white jitter (J 2 =20mUI rms) for in-band input FFT Points 64 Averaging. Hanning Window (NBW =1.5). to reach 0 dbfs at the output. In this case, the penalty ratio is independent of the signal transfer function (STF). Spectre transient simulations were performed using the verilog-a behavioral-level model of the CTSDM. The setup in Fig. 10 is used to remove the quantization noise component from the CTSDM s output PSD. Simulations were done for two cases of input signal: 1) 6 dbfs in-band signal and 2) 12.8 dbfs at f s /2 outof-band signal, which yields 6 dbfs at the output due to feedforward STF peaking. Hand calculation proceeds as Nqj 2 = Q2 J 2 OSR 1 π π NTF(Ω)(1 e jω ) 2 dω (17) Nsj 2 = A2 out J 2 OSR 1 e ω o T s 2 (18) which yields a noise level of 74.7 dbfs and 66.0 dbfs, respectively, for Q 2 = 19.8 dbfs, A 2 out = 6 dbfs, J 2 = 2 mui rms / 54.0 db, and OSR =16/12.0 db. Fig. 11 shows the simulated results and comparison with the theoretical spectrum. The simulated in-band noise level are 74.7 dbfs and 65.6 dbfs, respectively, for the two cases, which agrees extremely well with the theoretical prediction. Fig. 11(d) shows results for sweep simulations in which firstorder FIR DACs with transfer function (1 + az 1 )/(1 + a) REFERENCES [1] J. Silva-Martinez, A. I. Karsilayan, and H. M. Geddada, Blocker and jitter tolerant wideband ΣΔ modulators, in Proc. IEEE 55th Int. MWSCAS, 2012, pp [2] J. A. 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