Low Power Circuit Design Techniques: A Survey

Transcription

1 International Journal of omputer heory and Enineerin ol. 7 No. 3 June 205 Low Power ircuit Desin echniques: A Survey Nikhil Raj Ashutosh Kumar Sinh and Anil Kumar Gupta Abstract his paper presents a detail on various techniques to realize low voltae low power circuit. he techniques discussed are conventional ate-driven () floatin ate () quasi-floatin ate (Q) bulk-driven () and -Q. he comparative analysis results in best performance achieved by -Q approach. As circuits are well known approach for low power desin the combined effect Q in bulk driven circuit results in enhanced performance. he complete analysis has been carried out in industry specific node UM 0.8 micron technoloy with the help of HSpice simulator. Index erms Quasi-floatin ate bulk-driven bandwidth power. I. INRODUION Low power and efficient portable equipments deman are risin in day-to-day life. Moreover a lare number of research articles can be found to meet these oals specially when talkin about medical equipments. he common trend for analyzin low power circuits is the lowerin of supply voltae []. But the threshold voltae of metal-oxide-semiconductor (MOS) transistor acts as a main obstacle in lowerin of voltae supply after certain limit. he supply must be at least equal to or reater than the threshold of MOS transistors used in circuit realization. he rapid scalin of MOS processes in nanometer demand low supply which helped diital circuit realization at very low power consumption but it is not true for analo circuit realization. he associated drawback is short channel effect which results in offset low ain staes decreased impedance etc. onfiurin the whole system both diital and analo on sinle chip requires different levels of biasin currents which is fulfilled via current mirrors. o desin efficient current mirror with standard ate driven MOSFE that to at low power supply is not possible. o overcome several non-conventional metho like level shifter sub-threshold Q bulk has been proposed [2]. Every technique has its advantae and disadvantaes. Amon all the bulk driven MOS transistors are encouraed for realizin the low power circuits. In bulk-driven MOS transistors the ate terminal is biased by dc potential to turn on the MOSFE whereas the sinal is applied between the bulk and the source of the MOS transistor and causes the drain-to-source current flow. he problems associated with bulk as processin input is its lower transconductance and moreover requires a twin-well process for fabrication. he effect of decreased transconductance is visible by poor open-loop ain and hence the unity-ain bandwidth. In this Manuscript received March ; revised May Nikhil Raj Ashutosh Kumar Sinh and Anil Kumar Gupta are with the National Institute of echnoloy Kurukshetra Haryana India ( nikhilpub@mail.com ashutosh@nitkkr.ac.in akupta@nitkkr.ac.in). respect the most find suitable approach which is ainin interest nowadays is the combined effect of bulk with Q MOS transistors. he approach is named as -Q technique [3]. his approach not only work well at low supply but do not require increased the chip area as like MOS and QMOS. he objective of this paper is on emphasizin the interest to use -Q transistors which results in enhanced small sinal parameter for analo circuit realization. he advantae of the technique is exploited by comparin it with different low power techniques throuh an example of common source amplifier. Further a current mirror is also proposed. he HSpice results confirm the -Q to be a better option for low power application. he paper is oranized as follows: Section II of the paper covers the summary of low power techniques. Section III comprises the current mirror realization usin techniques detailed in Section II. he simulation results in HSpice on 0.8 m technoloy are detailed in Section I. Section concludes the conclusion of paper. II. LOW POWER EHNIQUES A. Floatin Gate () and Quasi-Floatin Gate (Q) MOS and QMOS [4] based circuits can operate at much lower supply. he advantae of these approaches lies in terms of linearity as the input couplin capacitor divider makes input sinal to attenuate and increases the linearity. he architecture of N-channel MOS (M) is shown in fi. (a). Under D analysis the ate of M is at floatin potential. he input capacitance is formed by second layer of ploy silicon over the poly layer of ate. he input capacitor formed is named as poly-poly layer (PIP) capacitor. Usin the law of chare conservation at floatin ate the floatin ate voltae is iven as IN GSS D GBB Q0 () where GS GB GS GB are the parasitic capacitance associated the floatin ate node and Q is the initial chare trapped in the floatin ate durin 0 fabrication. he trapped chare Q0 at floatin ate [5] and attenuation of effective ate input voltae due to input capacitor divider were the main obstacles with MOS. Many research articles came to overcome these issues at the expense of extra circuitry. Later with introduction of QMOS (architecture similar to MOS) associated drawbacks of MOS were no more issues. he schematic of QMOS (M) is shown in Fi. (b). he only difference DOI: /IJE

2 International Journal of omputer heory and Enineerin ol. 7 No. 3 June 205 lies in convertin of floatin ate in quasi mode by employin a lare valued resistor R lare realized by reverse biased junction of P-type MOS transistor (MP) operatin in cut-off reion. he effective quasi floatin ate voltae under ac input in s-domain is expressed as sr Q lar e Q IN GS S D GB B srl ar e where GS GB 0 (2) is the total capacitance and is the parasitic capacitance of transistor workin in cut-off reion attached to Q node. he equation (2) represents a hih pass filter with its cut-off frequency iven by R. By selection of proper R lar e 2 l ar e the cut-off frequency can be made very low (even less than Hz) mostly required by bio-amplifiers [6]. So it can perform as weihted averae of ac input voltaes from very low frequency to hih frequency without affectin the required results till it remains lare enouh. he only related issue left with these and Q approach was lower transconductance and transient frequency compared to conventional approach. Moreover with these architectures the D converence has been a continuously encountered problem by currently available spice simulators. Fi.. N-channel: (a) and (b) Q MOS transistor. Several based applications can be found out of which few are related to desin of multiplier transconductor filter I- converter M with wide dynamic rane and enhanced bandwidth and many other concerned to low voltae applications such as M with enhanced bandwidth [7] M with enhanced characteristics [8]. akin advantae of capacitor divider property some Q based transistors were used for desin of very linear prorammable MOS OA [9] which further used to implement tunable MOS resistors [0] and also GM- filter []. Other recent published articles are based on current conveyor [2] M havin low input compliance voltae [3]. he experimental verification of Q based circuits in literature proved to be a better technique for realizin low voltae power circuits. B. Bulk-Driven () he conventional MOS transistor is a four terminal device whose fourth terminal the bulk is usually connected either neative/positive supply for N-channel/P-channel transistor respectively or to their source terminal. But by usin the bulk-terminal as a sinal input instead of connectin it to any of the supply voltaes or source terminal the threshold voltae limitation can be removed. Based on this technique was first reported in [4]. he operation is similar to operation of a junction field effect transistor (JFE). he most sinificant issue related to the bulk-driven is its small body transconductance he relation of iven as mb and transient frequency with ate transconductance mb 2 2 mb m m where is the body effect co-efficient f Fermi-potential SB f SB m f. is (3) is the is the source-to-bulk potential. he normal rane of varies from 0.2 to 0.4. Since the is much sensitive to device mismatch and process variation positive feedback increases the chances of stability issues at input. Moreover increased impedance by loop ain affects the non-dominant pole thereby deradin the frequency response of amplifier. A numerous circuits based on this technique tareted to achieve low power can be found. Few are based on op-amp desin [5] hih ain op-amp [6] hihly linear OA [7] etc.. Bulk-Driven Quasi-Floatin Gate (-Q) Usin the toether with Q MOS transistor enhanced small-sinal characteristics like transconductance and bandwidth over separate and Q-based circuits can be achieved. he approach is introduced with the name -Q technique. he latest related research article usin this technique can be seen in desin of differential difference current conveyor [8]. his technique is helpful for battery-operated portable devices since its bulk-input processin demand maximum supply not more than a BJ junction turn-on potential to prevent latch-up. Under D analysis it works as simple technique whereas for ac analysis it combines the effect of and Q. he resultant is an improved frequency response over. Fi. 2. N-hannel: (a) and (b) -Q MOS transistor. III. URREN MIRROR urrent mirror (M) is a circuit whose function is to copy currents to various blocks in the circuit. A most common example can be found in biasin blocks for operational transconductance amplifier op-amps stabilization current amplification active loadin and level shiftin [9]. he desin parameters affectin functionality of current mirror are input/output compliances voltae limits small sinal input/output impedances and bandwidth [20]. For supply 73

3 International Journal of omputer heory and Enineerin ol. 7 No. 3 June 205 below threshold voltae of standard MOS transistors the conventional current mirror unfit due to its deraded parameters like hih input resistance low output resistance bandwidth. he analysis of small-sinal parameters of current mirror usin the discussed low power techniques is shown below (able I): ABLE I: OMPARISON OF AFFE ON PARAMEERS WIH LOW POWER EHNIQUES hreshold Q th th th Q ransconductance m th m th m removed -Q removed A. Gate Driven (): onductance m 0.7 m f ransient frequency f f f f. Quasi-Floatin Gate (Q) Driven M: Input Resistance R Fi. 5. N-hannel Q current mirror. in Q k Output Resistance R 2 urrent ain A I Dominant pole s Q m Q out Q Q km 2 ( (2 s 2 d MP )) s k ( (2 )) m s2 d MP k m2 2 s2 d MP where k is the effective capacitance ratio of input to D. Bulk Driven () M. Fi. 3. N-hannel current mirror. Input Resistance R in m Output Resistance Rout 2 urrent ain A I Dominant pole s 2 s 2 2 m2 s2 m s2 m2 s2 B. Floatin Gate () Driven M Input Resistance R Fi. 4. N-hannel current mirror. in k Output Resistance R 2 urrent ain A I Dominant pole s m out km2 ( 2 s 2 ) s k ( 2 ) k 2 m s2 m2 s2 where k is the effective capacitance ratio of input to. Input Resistance R Fi. 6. N-hannel current mirror. in mb Output Resistance Rout 2 urrent ain A I Dominant pole s 2 s 2 2 mb2 sb2 mb sb2 mb2 sb2 E. Bulk Driven Quasi-Floatin Gate (-Q) Driven M Fi. 7. N-hannel -Q current mirror. 74

4 International Journal of omputer heory and Enineerin ol. 7 No. 3 June 205 A Input Resistance R in Q Output Resistance R 2 urrent ain I k out Q m mb km 2 mb2 ( 2 (2s 2 2 sb 2 d MP )) s k ( (2 2 )) m mb 2 s2 sb2 d MP Fi. 9 and Fi. 0 respectively. Dominant pole s Q k m2 mb 2 (2 2 ) 2 s2 sb2 d MP omparin the small-sinal parameters of the stated techniques it if found that For input resistance Fi. 8. omparison of D transfer characteristics. Rin Q Rin Q Rin Rin Rin (4) For output resistance R R R R R (5) out out Q out out Q out For bandwidth BW Q BWQ BW BW BW (6) From (4) (5) and (6) it can be easily noted that the best condition which is required by ideal current mirror is fulfilled via -Q technique. Fi. 9. omparison of input resistance. I. SIMULAION RESULS he current mirror is simulated on 0.8 m mixed-mode twin-well technoloy provided by UM with the help of HSPIE simulator. he circuit has been desined with four different LP techniques and compared with the conventional current mirror. he W/L ratio of MOS transistors used for desin of current mirror is shown in able II. he values of other parameters assumed for analysis is also listed in able II. ABLE II: W/L RAIO OF MOS RANSISORS USED IN M OA m ransistors W m L M Fi. 0. omparison of output resistance. Form the response the -Q approach proves to be a better option for realizin current mirror. he frequency response shown in Fi. reveals the hihest bandwidth achieved by -Q technique. M MP MP dd/ss= 0.3==2=pf Ibias=65uA he D transfer characteristics are shown in Fi. 8. he input current is swept for 50uA. It can be observed that techniques other than bulk-driven perform better in current copyin. his is due to non-linear behavior of MOS under bulk as processin input in sub-micron channel lenth. o suppress the offset current and minimize the non-linear characteristics can be achieved by usin an offset current at the output node and use of hih dimension MOS device. he input resistance and output resistance plot for current mirror realized under different low power techniques is shown in Fi.. omparison of bandwidth. he comparative analysis effect of all techniques on current mirror is summarized in able III. It results easily reveals the advantae of -Q not only in terms of parameter enhancement but consumes the low power. 75

5 International Journal of omputer heory and Enineerin ol. 7 No. 3 June 205 ABLE III: OMPARAIE ANALYSIS OF PERFORMANE MERIS OF M echnique Rin (ohm) Rout (ohm) Bandwidth (HZ) Power ( w ) k 3.35G k 3.2G 97 Q 48 4.k 4.64G 97.85k.8k.67G 60 -Q 292.5k 5.7G 59. ONLUSION In this paper different low power techniques have been discussed. o verify the advantae and disadvantaes of such techniques is done with the help of current mirror. Amon the discussed approaches the bulk-mode bein a low power option encouraes the -Q approach. he enhanced small-sinal parameter of current mirror like input/output resistance and bandwidth can be useful for hih frequency application. he desins have been implemented usin 0.8 m twin-well process throuh HSpice simulator. REFERENES [] B. J. Blalock P. E. Allen and G. A. Rincon-Mora Desinin - op amps usin standard diital MOS technoloy IEEE ransactions on ircuits and Systems II: Analo and Diital Sinal Processin vol. 45 no. 7 pp [2] F. Khateb S. B. A. Dabbous and S. lassis A survey of non-conventional techniques for low-voltae low-power analo circuit desin Radioenineerin vol. 22 no. 2 pp [3] F. Khateb Bulk-driven floatin-ate and bulk-driven quasi-floatin-ate techniques for low-voltae low-power analo circuits desin AEU - International Journal of Electronics and ommunications vol. 68 no. pp [4] J. Ramirez-Anulo A. J. Lopez-Martin R. Gonzalez-arvajal and F. M. havero ery low voltae analo sinal processin based on quasi floatin ate transistors IEEE Journal of Solid State ircuits vol. 39 pp [5] E. Rodriuez-illeas M. Jimenez and R. G. arvajal On dealin with the chare trapped in floatin- ate mos (MOS) transistors IEEE ransaction on ircuits and Systems-II: Express Briefs vol. 54 no. 2 pp [6] R. R. Harrison A low-power low-noise MOS amplifier for neural recordin applications in Proc. IEEE International Symposium on ircuits and Systems (ISAS 02) 2002 vol. 5 pp. v97-v200. [7] S. Sharma S. S. Rajput L. K. Manotra and S. S. Jamuar MOS current mirror: Behaviour and bandwidth enhancement Analo Interated ircuits Sinal Processin vol. 46 no. 3 pp [8] A. Kumar Split lenth MOS MOS cell: a new block for low voltae applications Analo Interated ircuits and Sinal Processin vol. 75 no. 3 pp [9] J. M. A. Miuel A. J. Lopez-Martin L. Acosta J. Ramirez-Anulo and R. G. arvajal Usin floatin ate and quasi-floatin ate techniques for rail-to-rail tunable MOS transconductor desin IEEE ransaction on ircuits and Systems I: Reular Papers vol. 58 no. 7 pp [0] A. orralba. Luja n-marti nez R. G. arvajal J. Galan M. Pennisi J. Ramirez-Anulo and A. Lo pez-martin unable linear MOS resistors usin quasi-floatin-ate techniques IEEE ransaction on ircuits and Systems II: Express Briefs vol. 56 no. pp []. Garcia-Alberdi A. Lopez-Martin L. Acosta R. G. arvajal and J. Ramirez-Anulo unable class AB MOS Gm- filter based on Quasi-Floatin ate techniques IEEE ransaction on ircuits and Systems I: Reular Papers vol. 60 no. 5 pp [2] H. Moradzadeh and S. J. Azhari Low-voltae low-power rail-to-rail low-rx wideband second eneration current conveyor and a sinle resistance-controlled oscillator based on it IE ircuits Devices & Systems vol. 5 no. pp [3] R. Gupta and S. Sharma Quasi-floatin ate MOSFE based low voltae current mirror Microelectronics Journal vol. 43 no. 7 pp [4] A. Guzinski M. Bialko and J.. Matheau Body driven differential amplifier for application in continuous-time active -filter in Proc. ED Paris France 987 pp [5]. Stockstad and H. Yoshizawa A rail-to-rail MOS operational amplifier IEEE Journal of Solid-State ircuits vol. 37 no. 3 pp [6] L. Zuo and S. K. Islam Low-voltae bulk-driven operational amplifier with improved transconductance IEEE ransactions on ircuits and Systems I: Reular Papers vol. 60 no. 8 pp [7] J. Gak M. R. Miuez and A. Arnaud Nanopower OAs with improved linearity and low input offset usin bulk deeneration IEEE ransactions on ircuits and Systems I: Reular Papers no. 99 pp [8] F. Khateb W. Jaikla M. Kumnern and P. Prommee omparative study of sub-volt differential difference current conveyors Microelectronics Journal vol. 44 no. 2 pp [9] P. E. Allen and D. R. Holber MOS Analo ircuit Desin Second Edition Oxford University Press [20] H. Hedayati A low-power low-voltae fully diital compatible analo-to-diital converter in Proc. he 6 th International onference on Microelectronics (IM 2004) 2004 pp Nikhil Raj was born in India in 983. He received his M.ech deree in electronics and communication enineerin with specialization in LSI desin from National Institute of echnoloy Kurukshetra Haryana India in He served as an assistant professor in NI Kurukshetra for 2 years from and later joined as a PhD scholar in the same institute. urrently he is on leave from NI Kurukshetra and workin as a research assistant under MOSI (Malaysian Govt.) project in the Department of Electrical and omputer Enineerin urtin University Malaysia. His area of interest is in low power bio-inspired circuits. He is currently involved in low power circuit desin. Ashutosh Kumar Sinh was born in India in 975. He obtained his PhD deree in electronics enineerin from Indian Institute of echnoloy BHU India and Post Doc from Department of omputer Science University of Bristol UK. urrently he is workin as Professor in department of omputer Application NI Kurukshetra Haryana India. He also served as an associate professor and the head of the Electrical and omputer Enineerin Department urtin University Malaysia. He has more than 3 years research and teachin experience in various Universities of the India UK and Malaysia. His research area includes multi aent system verification synthesis desin and testin of diital circuits. He has published more than 90 research papers till now in different journals conferences and news maazines and in these areas. He had delivered the invited talks and presented research papers in several countries includin Australia UK South Korea hina hailand India and USA. urrently he is an editorial board member of International Journal of Networks and Mobile echnoloies International journal of Diital ontent echnoloy and its Applications. Also has shared his experience as a uest editor for Pertanika Journal of Science and echnoloy chairman of USE International onference 20 and as editorial board member of UNIAR e-journal. Presently he is leadin two research rants and supervisin five hiher deree research students. Anil Kumar Gupta was born in India in 95. He received B.ech. (EE) from G.B.Pant University of Ariculture and ecnoloy in 972. He received M.ech. and PhD derees in electrical enineerin from Indian Institute of echnoloy Kanpur in 974 and 985 respectively. He served as an assistant station enineer in All India Radio from 974 to 978. Since 985 he is with National Institute of echnoloy Kurukshetra where he is presently servin as a professor of electronics and communication enineerin for the last thirteen years. His areas of interest are semiconductor devices and technoloy embedded systems instrumentation and LSI. 76