The Design and Optimization of MOSFET Driving Circuit based on Parasitic Parameter

Transcription

1 International Journal of omputer Applications ( ) The Desin and Optimization of MOSFET Drivin ircuit based on Parasitic Parameter Wei Hon Shanhai University of Enineerin Science Sonjian Shanhai 0160, hina Yuchen hen * Shanhai University of Enineerin Science Sonjian Shanhai 0160, hina Zhenmin Li Shanhai University of Enineerin Science Sonjian Shanhai 0160, hina ABSTRAT Accordin to the parasitic parameter which was produced by the PB line of MOSFET's drivin circuit, this paper will analyze the circuit principle of drivin circuit, and then uses the software Saber to stimulate the circuit, finally verifies the stimulate results and formula under the experimental waveforms and statics. General Terms Stimulation and Hardware Desin Keywords Saber stimulation; Miller effect; drivin circuit; parasitic parameter; MOSFET 1. INTRODUTION With the development of power electronics technoloy the Switchin power supply technoloy has matured, its hih conversion efficiency and hih level of stability and reliability make it radually replaced the traditional linear power supply. People usually pursue hih power density and hih efficiency switchin power supply. Usually there are two methods to increase power density and efficiency: one is to reduce the loss of switch topoloies, which reduces the volume of heat sink; the other is the means to realize hih frequency switch power supply, so as to reduce the volume of passive components. In practical applications, to the aim of easin the desin, people usually use the way to increase the frequency of switchin. In the switchin power PB s production, the drive circuit will inevitably produce parasitic parameters. When it is at a low switchin speed, these parasitic parameters may have little effect, but once in the hih-speed PB desin, parasitic parameters of circuit will cause some strane effect, it will not only reduce the electromanetic compatibility EM, but also reatly increase the switchin losses. Particularly is the drivin circuits and MOSFET structure alinment, these factors will affect reliable capability of switchin, and affect the overall stability of switchin power-supply system.. DESIGN AND ANALYSIS OF DRIING IRUIT U DS I DS t 1 t t 3 t 4 Fi 1: The drain-source voltae and current waveform when MOSFET turns on U G Q GD U s(th) t 1 t t 3 t 4 Fi : The ate-source voltae waveform when MOSFET turns on Stae 1(0-t 1 ): MOSFET accept the drive sinals, rise from zero to U GS (th), when at t 1 point I d, I d at t 1 point is 0. Stae (t 1 -t ): T 1 ate and the source reaches the threshold voltae U GS (th), I d started to increase, I d reached the maximum value. This time is called the current rise time. Stae 3(t 3 -t 4 ): Miller platform (t -t 3 ).At the T moment, between the source and drain voltaes U DS bean to decline, MOSFET can be considered turnin on radually, the drive circuit of the MOSFET' must chare the capacitance between drain, leadin to the Miller effect Stae 4(t 3 -t 4 ), Gate-source voltae increases until it reaches a pre-desined drive voltae., in order to let the MOSFET turnon reliably, the drivin voltae is usually desined about MOSFET s switchin speed is very fast, the MOSFET s drivin circuit needs instantaneous peak current, makes Miller platform delay time (t -t 3 ) as short as possible. The source of the drivin circuit is TMS30F81 DSP chip, The desin of drivin circuit is based on the optical couplin isolation. Because TMS30F81 DSP chip can approximately output about 4mA current, and the current of optical couplin isolation is about 0mA for the chip HNW01, so add the Darlinton interated chip ULN003. "Double-GND" principle can achieve the oal of sinal isolation, and it can effectively suppress hih frequency clutter sinal interference. In order to make reliable MOSFET switch, this desin uses the T440 driver chip, it contains two transistors, which can output a pulse whose peak current is 6A, it can meet the needs of the MOSFET s drive. 5

2 International Journal of omputer Applications ( ) When people study the effects of parasitic parameters of drivin circuit, people mainly consider two aspects: the one is parasitic resistance and parasitic inductance in the packain structure of the MOSFET; the other is parasitic parameters which caused by the PB wirin line. When considered the PB wirin line, the parasitic inductance is the main factor, self-inductance and mutual inductance can be obtained throuh empirical formula, the self-inductance L1: L ln K H 0.35 K H The unit is (H), u 0 is the permeability of vacuum. When the PB line is double parallel line, which will cause mutual inductance, the L by the followin formula: the lenth is c, distance is j, and the mutual inductance calculation formula is as follows [] : 0 J J L ln 1 1 J J Usually in practical application, in order to calculate PB cable inductance simplely, often use the formula: L3 Lenth 10 The unit is (nh). Lenth: PB-driven resistance R to the MOSFET, the unit is (mm). When the driver circuit turned on, circuit schematic can be turned into the followin fiure: Fi 3: Isolatin driver circuit schematic diaram 15 R Fi 4: The model of drivin circuit when it turns on L is the parasitic inductance, is the capacitance between GS and R is the drivin resistance such as R 6. Accordin to the fiure on the circuit, the current of drive circuit: Inductor s voltae: Resistor s voltae: Accordin to the KL: I L t t I L L t R I t t L R t t t The formula can be explained: 0 G LS S RS L L 1 This is a 3-step system, accordin to its zeros and Poles, several conclusions can be ot: (1) When the poles for 3 different real roots, it will produce over dampin vibration; 6

3 International Journal of omputer Applications ( ) () When the pole has two real roots, it will produce critical dampin vibration; (3) When there are some imainary numbers, it will produce less dampin shocks. When it causes dampin shocks, the MOSFET s ate source drive voltae waveform will produce shock, it will appear a short rise of pointed peak voltae, it can make switch tube failure, so you should brin it to a dampin or critical state. And: 1. R shock;. R S LS R S 1 L, the circuit is underdamped, circuit will L, the circuit is in the critical dampin States; L 3. R, the circuit is in a damp State, the circuit can work well. To make the drivin circuit shock does not occur, the circuit must be in a dampin condition, so et the drive resistor: R L R ( iss rs s) R is the drivin resistance, iss is MOSFET s input capacitance, rss is MOSFET s reverse transfer capacitance. Generally, with the combination of parasitic parameters in a practical application, time constant is calculated by the formula: R ( iss rs s) apacitance charin time is less than or equal, in order that to make MOSFET switchin loss not too lare, R : Ton _ min R iss rss 8 So you can obtain R the maximum value in the rane, but R s value is as small as possible, because it can reduce the MOSFET switchin Loss, thereby it can make the sink size small, but if the R is too small, it will result in the shock of drivin voltae, and make MOSFET break down. 3. SYSTEM FUNTION MODULE DESIGN The study uses a special simulation software for switchin power supply Saber, Saber simulation software is a software which is desined by the United States company Synopsys, it is an EDA software which is hailed as the world's most advanced simulation software, it now become the industry standards software for the simulation of mixed sinals, mixedtechnoloy of desin and verification tools. And a MOSFET is turned on at the Miller platform stae, risin response time can be calculated: Fi 5: Schematic diaram of Saber simulation Set the Input capacitance iss is 100(pF), Td(on) openin delay time is 900 (ns), Tr is 300 (ns), s is 15(), reverse transfer capacitance rss is 00 (pf). Saber simulation software occupies a very important role in the research of simulation because of its powerful waveform analysis. There are more than 10 special means of analyzin such as: D analysis, A small-sinal analysis, Time domain analysis and Frequency domain analysis. The simulation analysis of use ary embedded time domain analysis. In the desin of PB Board, the write line lenth between MOSFET and R is about 0mm, its parasitic inductance is 30nH, R is from 1 ohm to 8 ohm, the chane step is.5 7

4 International Journal of omputer Applications ( ) ohm, time of simulation is 0.5s, simulation time step is 1us and the drive voltae is 15, the switch tube drivin waveform showed by the fiure 6, specific numerical results shows by the table 1. Fi 6: Drivin waveform simulation From the fiure, when the parasitic inductance parameter is 30nH and the drive resistance is 10 Ohm, switch tube waveform shocks obviously, and appeared a peak voltae, its peak voltae s maximum value reached 19, with the increasment of R resistance, switch tube waveform shocks has slowed down, when the drive resistance R is 4 ohm, waveform becomes flat, and has no shocks, but risin speed of voltae is the slowest, this is due to switch tube MOSFET exists Miller effect (Fiure 1 Miller platform stae). If the voltae rises too slowly, it will sinificantly increase the switchin MOSFET's loss, whitch is also a very serious problem. Tab1: The peak value of shock voltae Drivin resistance Maximum voltae (v) The line lenth is 5mm, the parasitic inductance can be 35nH, R value is set from 3 ohm to 7 ohm, the chane step of R is 3 ohm, drive voltae is 15, the simulation time is 0.5s, simulation time step is 1us, you can et drivin waveform of switches in Fiure 7, table is the peak value of drivin voltae. Table drivin resistance under the drivin voltae spike peak Resistance Maximum voltae Resistance Maximum voltae From the fiure, when the parasitic inductance parameter is 35nH and the drive resistance R is 10 Ohm, switch tube waveform shocks obviously, and appeared a peak voltae, its peak voltae maximum value reached , with the increasment of R resistance, switch tube waveform shocks has slowed down, when the drive resistance is 7 ohm, waveform is flat, and has no shocks, but voltae rose slowly. ompared to the previous case, it shocks more severely, ompared two same R, the peak voltae increases about. because of the increasment of drivin resistance, the charin time of capacitance increases, 33 Ohm shows the effect in the inhibition of waveform shocks, but it will increase the MOSFET switchin losses. By the precedin switches voltae curves, in order to make the MOSFET present an ideal waveform, and to make it work well. The first thin is the attention should be drawn when draw the PB, the drive circuit s parasitic parameters can influence MOSFET s switch, the write line should be as short as possible. arious factors should be taken into account in selectin the drivin resistance, such as: inhibition of switchin waveform shocks, inhibition of spikin peak voltae, the MOSFET s minimum turn-on time. 4. SYSTEM TEST AND ANALYSIS FQA8N50 is used in this experiment, the specific parameters: input capacitance iss is 4300(Pf), Td (on) turnon delay time is 10 (ns), Tr is 50 (ns), s typical voltae is 15 (), reverse transfer capacitance rss is 80 (pf). The formula: Tr Tdon R 16 iss rss R 11.4 R L R.383 PB line lenth is 1mm, the output PWM s duty is 0.5, switchin frequency is 0KHz, the drivin resistances are 1 ohm, 10 Ohm, 15 ohms, 0 ohm, 50 ohm. Waveform analysis: Fi 7: Driver resistance switchin waveforms 8

5 International Journal of omputer Applications ( ) Fi 7: The drive waveforms when the R is 0 ohm Fi 8: The drive waveforms when the R is 50 ohm Tab 3: The peak value of drivin voltae under different value of R Resistance Peak voltae (v) ONLUSION From the analysis data in charts and tables, the switchin frequency is 0KHz, it will have a little shock when resistance is 50 ohm, but can be turned on for the lonest time; when the resistance R is1 ohm, it have the biest peak voltae spikes, but the time of openin is the shortest. ombined with the peak voltae spikes and turn-on switchin losses two factors, accordin to the above formula results R can be 11.4ohm, take the electromanetic interference EMI into account, the resistance is larer than 11.4 ohm. In order to finish a drivin circuit desin, first it must start with the principle of circuit, under different applications the drivin circuit s desin principles will be definitely different. When you select the MOSFET, it Should be combined with the circuit voltae and other specific parameters, different switch tube usually have different size of its ate source capacitance, so its correspondin drive resistance R is also different. it should be combined with the circuit s voltae and over current specific parameters such as size and enouh quantity of selected, different switches its mixed with varyin amounts of capacitance between ate and its correspondin driver resistance is also different. When people draw the PB Board, it should ive full attention to drivin circuit between the end line to the MOSFET's, its lenth should be as short as possible under PB layout allows, usually the lenth is about 10-15mm, so it can reduce parasitic parameters caused by PB. Different alinment, And different lenth of PB walk line, which has the correspondin matchin resistance, it is necessary to avoid the shock of the circuit and reduce the switchin loss, and achieve the optimization of drivin resistance, so as to achieve the purpose of optimizin the drivin circuit. 6. REFERENES [1] Wan Zhaoan, Liu March. Power electronics [M]. Beijin: hina machine press, [] Shi Xiude. Parasitic parameters of circuit for BOOST converter switches [D]. Harbin Institute of technoloy, 01:31 [3] Mei Jun, Zhen Jianyon. Saber simulation model and its application IGBT1 in the solid state switch [J]. Electric power automation equipment.005 (06): 53 [4] Yin Wenhun. D servo system Study on the application of PWM power amplifier [D].Graduate school of the hinese Academy of Sciences (hanchun Institute of optical precision machinery and physics), 004:9-3 [5] Mu Xinhua, Yan Zhiyon. Switchin power supply printed circuit board study on the effects of parasitic parameters[j]. Journal of electrical enineerin, 004,4 (11): [6] Xu hen min, Xu Dehon. Si MOSFET drive circuit and experimental analysis of [J]. power, 013 (05): 71 [7] Zhao Q, Stojcic G. haracterization of dv/dt induce power loss in synchronous buck D-D converters[]. Applied Power Electronics onference, Nineteenth Annual IEEE, 004, 1: [8] Ji Shenru, cauht up. MOSFET s isolated hih-speed drive circuit [J]. Electric weldin machine, 013 (37): 6-7 [9] NI Yon, Xu Zhen, etc. A parasitic parameter extraction model and optimization of PB desin [J]. the computer measurement and control, 010,18 (3): [10] ui Yonshen, Wan Shishan, On the effects of parasitic parameters on characteristics of EMI filter hih frequency output simulation [J]. hina electro-technical Institute of power electronics society 11th annual meetin, 008:1-5 [11] Wu Fenjian, Sun Li. Electromanetic interference and suppression of bride-type power MOSFET [J]. University of Aeronautics and Astronautics journal, 005,37 (1): 9-33 IJA TM : 9