2.4GHz Fast Hopping Frequency Synthesizer

Transcription

1 2.4GHz Fast Hopping Frequency Synthesizer A thesis submitted to The Hong Kong University of Science and Technology in partial fulfilment of the requirements for the Degree of Master of Philosophy in Electrical and Electronic Engineering. By Wong Ming Yip Wallace Department of Electrical and Electronic Engineering B.Eng (Elec) January, 1999

2 2.4GHz Fast Hopping Frequency Synthesizer Approved by: By Wong Ming Yip Wallace Dr. Jack Lau Thesis Supervisor Prof. Philip Chan Thesis Examination Committee Member (Chairman) Dr. Philip Mok Prof. Philip Chan Head of Department Department of Electrical and Electronic Engineering The Hong Kong University of Science and Technology January, 1999

3 2.4GHz Fast Hopping Frequency Synthesizer By Wong Ming Yip Wallace for the Degree of the Master of Philosophy in Electrical and Electronic Engineering at The Hong Kong of University of Science and Technology in January, 1999 Abstract A 2.4GHz frequency synthesizer is proposed as a part of a low cost RF front end for ISM band applications. The frequency synthesizer employed a new dual loop architecture to improve the settling time, while keeping a fine frequency resolution. With a settling time of 30µs, the frequency synthesizer is able to hop at 2k hop/s with less than 10% overhead. When utilized in a digital wireless system, the fast hopping rate is able to improve the efficient of the coding scheme and improve the performance of the system. The frequency synthesizer includes a monolithic LC tank VCO with a phase noise performance of dBc/Hz, dBc/Hz and -118dBc/Hz at 100kHz, 600kHz and 1MHz offset respectively, with an innovative varactor design, the VCO is able to achieve a tuning range of 600MHz, from 1.8GHz to 2.4GHz. When designed in a 0.35µm CMOS technology, the synthesizer drew 40mA from a 3V supply.

4 Acknowledgments The completion of this thesis would have been impossible without the intellectual and physical support from many individuals. During the last five years, I have been growing to be an educated as well as cultivated person. I have to thanks for every person who have shared their time, experience and knowledge with me. Firstly, I would like to thank my thesis supervisor, Dr. Jack Lau, not only for his technical and financial support, but also for sharing his valuable experience and his intellectual maturity with me. Next I would like to thank for the people in the Consumer Media Laboratory and UMAN group, who had discussed with me varies issues in related to my Thesis. Special thanks go to Frankie Hui, who had provided a great due of technical support during my research. I would also like to thank Prof. Philip Chan and Dr Philip Mok for sitting on my thesis committee. I would like to extend my appreciation to Mr Jack Chan and Mr Siu-Fai Luk for the help in layout submission to MOSIS, Mr Joe Lai for sharing his experience in using varies RF equipments. Last but not the least, I would like to thank my parents for their support and love.

5 CHAPTER 1 INTRODUCTION 1 Phase Locked Loop Frequency Synthesis 2 Frequency Hopping Wireless Audio System 4 Overview 6 CHAPTER 2 PHASE-LOCKED LOOP 7 Linear Model of Phase-locked Loop 7 Second order loop 9 Passive Loop filter 9 Active loop filter 10 Loop filter with charge-pumping phase detector 11 Closed-loop response 12 Frequency synthesizer 17 Dual loop architecture 19 CHAPTER 3 HARDWARE IMPLEMENTATION 23 Voltage Controlled Oscillator 23 Oscillator Theory 24 Spiral inductors 27 Varactor 30 Voltage Controlled Oscillator 41 Mixer 52 Prescaler 54 Phase detector 60 Loop Simulation 62 CHAPTER 4 CONCLUSION 63

6 REFERENCES 65

7 Figure 1. A general block diagram of a RF receiver 2 Figure 2. A block diagram of a phase-locked loop frequency synthesizer 3 Figure 3. The wireless audio system 4 Figure 4. Frame structure of the RS code 5 Figure 5. Linear model of a phase-locked loop 7 Figure 6. Passive lag-lead loop filter 9 Figure 7. Current feedback active loop filter 10 Figure 8. Passive loop filter to realize a) type I system and b) type II system 12 Figure 9. Open loop transfer function 15 Figure 10. Typical output spectrum of a PLL 16 Figure 11. Frequency divider in a VCO 17 Figure 12. Dual-loop architecture using vernier effect 19 Figure 13. Improved dual loop architecture 20 Figure 14. Matlab simulation result for the dual loop frequency synthesizer 22 Figure 15. An LC tank oscillator 25 Figure 16. Conversion of noise around integer multiples of the oscillating frequency into phase noise 27 Figure 17. A spiral inductor 28 Figure 18. Model of a spiral inductor 29 Figure 19. Substrate model 29 Figure 20. a) a PN junction varactor, b) an PMOS capacitor varactor and c) an accumulation -mode varactor 31 Figure 21. Cross-sectional view of the gated varactor 32 Figure 22. Simplified MEDICI simulation showing the carrier concentration under different gate bias 34 Figure 23. Simplified MEDICI simulation showing the carrier concentration under different drain bias 35 Figure 24. The carrier concentration of the varactor when reaching its a) maximum capacitance and minimum capacitance 37 Figure 25. Measured capacitance under different bias 39

8 Figure 26. Measured Q-factor of the varactor 40 Figure 27. VCO fabricated in HP 0.35mm process 42 Figure 28. Capacitance tuning characteristic 43 Figure 29. Tuning characteristic of the VCO with HP process 43 Figure 30. The output spectum of VCO with the HP process 44 Figure 31. Schematic of 2.4G Hz VCO with TSMC process 45 Figure 32. The measured impedence of the inductor a) real part, b) imginary part. 46 Figure 33. Measured Q factor of the inductor 47 Figure 34. Extracted inductance 47 Figure 35. Phase noise plot, carrier frequency = 2.419GHz 49 Figure 36. Phase noise plot, carrier frequency = 2.020GHz 50 Figure 37. Phase noise plot, carrier frequency = 1.770GHz 50 Figure 38. The tuning characteristic of the VCO 51 Figure 39. The die photo of the 2.4GHz VCO 51 Figure 40. Mesurement setup of the VCO 52 Figure 41. Gilbert Cell mixer 53 Figure to 768 programmable frequency divider 55 Figure 43. Timing diagram of a 8 to 12 divider 55 Figure 44. Divide 2/3 circuit 57 Figure 45. Implementation of NOR/flip flop in current steering logic 57 Figure 46. Differential to single end converter 58 Figure 47. D flip flop by TSPC logic 58 Figure 48. The digital comparator used in this work 59 Figure 49. Simulation of the divider 59 Figure 50. Phase/Frequency detector implementation 60 Figure 51. Charge pump circuit 61 Figure 52. Simulation output of the phase detector and charge pump circuit 61 Figure 53. Simulation of the dual loop architecture 62

9 Table 1. Summary of loop filter feedback and transfer function 11 Table 2. Summary of Second-Order Loop Equations 13 Table 3. Summary of Inductors used 46 Table 4. Phase noise measurement at 2.4GHz 48

10 CHAPTER 1 Introduction Since the first demonstration by Guglielmo Marconi in 1901, the wireless technology has been gone through dramatic changes in the past 20 years. The cost of the cellular phone has been lowered dramatically in the past decade. As the technology keeps on advancing, the wireless transmission is no longer limited to voice communications. There is an increasing popularity in wireless applications such as wireless Local-Area-Network, wireless printers and wireless speakers. The market is demanding for a lower cost and more integrated wireless devices. The motivation of this study is to design a CMOS frequency synthesizer for indoor wireless applications. The frequency synthesizer is designed to meet the needs of a 2.4GHz frequency hopping wireless audio system which transmits MPEG compressed audio sources with Reed- Solomon error protection coding scheme. 1

11 Phase Locked Loop Frequency Synthesis 1.1 Phase Locked Loop Frequency Synthesis LNA IF LO FIGURE 1. A general block diagram of a RF receiver Figure 1 displays a general block diagram of a receiver. The RF signal is picked up by an antenna. The signal is filtered and amplified by a RF filter and a low noise amplifier. The RF signal is then down converted to the an intermediate frequency (IF) for further filtering and down converting. The local oscillator (LO) signal which is used to down convert the RF signal to the IF signal is usually generated by a frequency synthesizer from a low frequency reference. Phase-locked loop frequency synthesizers have the advantages of low power, feasibility of monolithic implementation and phase coherence during frequency transitions[1]. 2

12 Phase Locked Loop Frequency Synthesis Reference Phase Detector e Loop Filter Synchronized Oscillator u /N FIGURE 2. A block diagram of a phase-locked loop frequency synthesizer Figure 2 shows a block diagram of a phase-locked loop frequency synthesizer. The synchronized oscillator is usually a voltage controlled oscillator (VCO). The phase detector compares the output of the frequency divider and the reference. The difference in their phases is computed as e, and the signal e is filtered to produce u which controls the oscillator. The loop provides a feedback to keep the frequency of the output of the synchronized oscillator N times the frequency of the reference. In a frequency synthesizer, the dividing radio, N, is usually variable. Variation in N allows the synthesizer to synthesis a LO signal of different frequencies of channel selection. 3

13 Frequency Hopping Wireless Audio System 1.2 Frequency Hopping Wireless Audio System Mpeg audio RS coding RF module Rayleigh faying channel Mpeg audio RS decoding RF module FIGURE 3. The wireless audio system The frequency synthesizer described in this thesis is designed as part of a frequency hopping wireless audio system. Audio data with data rate of kbps is compressed into MPEG audio with data rate of 128kbps. The MPEG audio is protected by RS code and transmitted through the wireless channel. The RS encoded data rate is kbps. The encoded data is framed. A frame consists of 819 bytes and with a duration of ms. 4

14 Frequency Hopping Wireless Audio System 63 columns. Test symbols 13 RS symbols FIGURE 4. Frame structure of the RS code In order to maximize the efficiency of the RS coding scheme, each frame is interleaved into 63 columns with each column contents 13 RS symbols and 2 test symbols. Each column is transmitted at a different frequency channel. This topology ensures not all the columns of a frame is transmitted through a deep fade channel or a channel which is occupied by interferences. The received data is reconstructed and the missing columns are recovered at the decoder from the received columns. With a frame rate of ms, the hopping rate, hrate, is calculated as ms hrate = hop/s 63 (1) The required settling time for the frequency synthesizer to translate from one frequency to another frequency has be to less than 1/10 of the frame duration in order to achieve less than 10% overhead, i.e., less than 50µs. 5

15 Overview The settling time of a phase-locked loop frequency synthesizer is inversely proportional to the loop bandwidth, which in turns limited by the frequency of the reference. However, the frequency of the reference is limited by the minimum frequency step of the output of the frequency synthesizer. A typical loop with a carrier frequency of 2.4GHz and a minimum frequency step of 200kHz requires a settling time of 150µs. 1.3 Overview A new architecture which allows fast frequency hopping is proposed, simulation shows that the architecture is able to achieve a settling time of 30µs. A 2.4GHz monolithic LC tank VCO is designed and fabricated. To overcome the problem of limited tuning range in LC tank VCO, a gated varactor, which has a wider tuning range than other existing implementations, is proposed. An intensive study in monolithic inductor is also conducted. The fabricated VCO achieved a tuning range of 600MHz from 1.8GHz to 2.4GHz and achieved a phase noise performance at 2.4GHz of -94.7dBc/Hz, -113dBc/Hz and -118dBc/Hz at 100kHz, 600kHz and 1MHz offset respectively. Besides, the VCO, others building blocks in the frequency synthesizer is also studied. A complete loop simulation has been performed. When designed in a 0.35µm CMOS technology, the synthesizer drew 40mA from a 3V supply. 6

16 Linear Model of Phase-locked Loop CHAPTER 2 Phase-locked Loop To understand the operation of a phase-locked loop frequency synthesizer, the basic of a phase-locked loop is described in this section. A phase-locked loop filters the frequency of a signal. A transfer function can be used to describe the transients and frequency response of the filter. The transfer function of a phase-locked frequency synthesizer can be obtain by replacing parameters in the transfer function of a phase-locked loop. 2.1 Linear Model of Phase-locked Loop θ i Kd F(s) Kvco s θ o FIGURE 5. Linear model of a phase-locked loop 7

17 Linear Model of Phase-locked Loop Figure 5 presents a linear model of a phase-locked loop. The input, θ i, of the phase-locked loop is the phase of the reference frequency. The output, θ o, of the loop is the phase of the oscillator of the phase-locked loop. The phase detector compares the input with the output and produces a signal by multiplying the difference of the two phases with the phase detector gain, K d. The phase detector converts the phase information into a voltage or a current. The signal produced by the phase detector is passed to the loop filter, which is usually a low pass filter. The characteristic of the phase-locked loop greatly depends on the loop filter. In later sections, we are going to discuss how the filter shape influences the loop performance. The voltage controlled oscillator transfers the voltage to frequency. By integrating the output frequency, we obtain the phase of the output. The VCO is modelled by a integrator, K vco /s. The VCO gain, K vco is in the unit of radian per volt. The closed-loop transfer function of the phase-locked loop is H( s) θ ---- o θ i = = Gs ( ) Gs ( ) (2) where Gs ( ) K d Fs ( ) K vco = (3) s Due to the 1/s in the VCO s linear model, a phase-locked loop is at least order of 1 and of type I. The loop order depends on the order of the loop filter. order of loop = order of loop filter +1 (4) First order loop provides only one degree of freedom for designers, hence, the second or higher order loop is usually preferred. 8

18 Second order loop 2.2 Second order loop As discussed in previous section, the order of the loop is determined by the loop filter. In this section, we are going to study some of the filter types. The loop filter of a second order phase-locked loop can be an active filter or a passive filter. Active filter allows the filter to provide DC gain and also allows the poles and the zeros to have wider range of value, while the passive filter has the advantage of simplicity. A charge-pumping phase detector allows a near integrator response while allows the filter to be implemented by passive components only. A phase-locked loop, due to the present of the VCO, is at least type I. Additional poles at low frequency may change the system type. The primary difference between type I and type II loop is the nature of the phase error. In response to a frequency step, the steady-state phase error of a type I loop will change but that of type II will not. In response to a frequency ramp, the type I loop has an ever increasing phase error and type II loop has a steady phase error Passive Loop filter u R1 v R2 C FIGURE 6. Passive lag-lead loop filter 9

19 Second order loop The general form of the passive filter is shown in Figure 6. The transfer function of the filter is shown in equation (5) to (6). Fs ( ) v = -- = u = 1 + R 2 Cs ( R 1 + R 2 )Cs s ω z s ω p (5) (6) The pole of the filter, ω p, is located at 1/(R 1 +R 2 )C, and the zero, ω z, is located at 1/R 2 C. The passive filter, while simple and easy to implement, cannot provide DC gain to the system, results a type I system Active loop filter The values for pole and zero in a passive filter are limited to have the pole higher than the zero. The active loop filter provides the possibility of providing gain and a wider range of values for the pole and zero. Z FB u R 1 G v FIGURE 7. Current feedback active loop filter 10

20 Second order loop The general block for a current feedback active loop filter is shown in Figure 7. G is the transconductance of the amplifier. Z FB is a generic feedback. The transfer function of the loop filter is shown in equation (7). Fs ( ) v = -- = u Z FB ( s) R G (7) Some implementations are summarised in Table 1 [2], when F(s) is the transfer function of the filter. Z FB F(s) ω p ω z Integrator 1 G (1+G)R 1 C Cs ( s ω p ) Integrator and lead 1 R Cs s ω z R 1 C s -- 1/R 2 C Lag R 1/R p C -- p R p R p Cs R sr p C Lag-Lead R (R 2 +R p )C R 2 C R p ( R ( Cs) ) p + s ω z R s ω p R p + ( R ( Cs) ) TABLE 1. Summary of loop filter feedback and transfer function Integrator and integrator and lead type loop filter result in a type II system due to present of additional integrator. While Lag-lead filter gives a similar system as the passive filter Loop filter with charge-pumping phase detector A charge-pumping phase detector provides a high output impedance. When the phase detector drives a capacitor, it produces a near integrator response. It provides a better approximation to an integrator than a active filter and provides infinite lock-in range to the loop. With a 11

21 Second order loop charge-pumping phase detector, the lock-in range is only limited by the tuning capability of the VCO. A charge-pumping phase-detector outputs a current rather than a voltage, the loop filter transfers the current input to a voltage output. The filters and their transfer functions to realize the type I and type II system are shown in Figure 8. I v I v C R1 a) C1 R1 b) C2 FIGURE 8. Passive loop filter to realize a) type I system and b) type II system The transfer function of the filter in Figure 8 a) is shown in equation (8). The transfer function of the filter in Figure 8 b) is shown in equation (9). V --- I = R sr 1 C (8) V --- I = sr C sc ( 1 + C 2 ) 1 + ( sr 1 C 1 C 2 ) ( C 1 + C 2 ) (9) integrator lead-lag filter Closed-loop response Given the loop filter response as equation (10). 1 + s ω z Fs ( ) = K LF s ω p The closed-loop transfer function of the PLL is given as equation (11). (10) 12

22 Second order loop 1 + s ω z H( s) = Kω p s 2 + sω p ( 1 + K ω z ) + Kω p (11) where K=K d K LF K VCO Comparing the denominator of H(s) with the denominator of a standard second order equation. s ζω n s + ω n = s 2 + ω p ( 1 + K ω z )s + Kω p (12) where ζ is the damping factor and ω n is the natural frequency. From this it is apparent that ω n 2 = Kω p (13) ζ = 1 -- ω p ω n ω n ω z (14) The equations can be further simplified by taking approximation. The results are summarized in Table 2[2]. Filter Type Lag Lag-Lead H(s) 2 1 ω n s ζω n s + ω n s ω x ω n s ζω n s + ω n Integrator and Lead ζ 1 -- ω p ω p ω n ω n ω n ω n ω z ω z ω n 2 Kω p K p K v R 1 C TABLE 2. Summary of Second-Order Loop Equations To provide an optimally flat frequency response, ζ is usually greater than 0.5 and preferably equal to 1 ( 2) [3]. The loop bandwidth, ω n, of a phase-locked loop is limited by the input 13

23 Second order loop frequency, it is shown in [3] that for type II phase-locked loops the loop bandwidth has to be limited to roughly 1/10 of the input frequency. The transfer function for the charge-pump type II system is a third order loop rather than a second order loop, the transfer function of the loop is different from a second order loop. The open loop gain of the loop is G(s)=K pd F(s)K vco, where K pd is the phase detector gain, K vco is the VCO gain and F(s) is given in equation (9). Define r 1 and r 2 as in equation (15)[5] and equation (16)[5] and, G(s) can be calculated in terms of frequency,ω,the filter time constant τ 1 and τ 2, and the design constants K pd and K vco as shown in equation (17)[5]. The phase margin is determined in equation (18)[5]. G( s) s jω C 1 C 2 τ 1 = R C 1 + C 2 K = = τ 2 = R 1 C 2 pd K vco ( 1 + jωτ 2 ) τ ω 2 C 1 ( 1 + jωτ 1 ) τ 2 φω ( ) = tan ωτ 2 tan ωτ (15) (16) (17) (18) 14

24 Second order loop 0dB ω p -90 Phase margin -180 FIGURE 9. Open loop transfer function The open loop transfer function is plotted in Figure 9. To maximize the phase margin, we want the unity gain frequency, ω p, to be at the inflection point of the phase plot. By taking the derivative and set the derivative to zero, we get equation (19)[5]. And the time constants can be expressed in terms of the phase margin and loop bandwidth as in equation (20)[5] and equation (21)[5]. By setting G(ω p )=1, the values of the R 1,C 1 and C 2 follow as equation (22) to equation (24)[5]. ω p = 1 ( τ 1 τ 2 ) (19) τ 1 = sec tanφ p φ p ω p (20) 1 τ 2 = ω 2 p τ 1 (21) K pd K vco τ 1 C 1 = ω 2 p τ ( ω p τ 2 ) ( ω p τ 1 ) 2 (22) τ C 2 = C τ 2 (23) 15

25 Second order loop τ R 2 2 = C 2 (24) The loop filter is completely specified by the two parameters, ω p and φ. The closed-loop response of the PLL is of low pass. As the input frequency varies slowly, the loop responses rapidly to the changes and tracks the variation. When locking to a clear reference, the phase-locked loop rejected the close-in phase noise of the VCO. A typical output spectrum of a PLL is shown in Figure 10. The close-in phase noise of the oscillator is suppressed by the loop. The phase noise of the output follows the VCO s phase noise as the frequency offset from the carrier increases. In practise, noise generates in the loop components raises the out band noise level by a few db. Phase noise is usually measured in dbc/hz, i.e. the noise power per hertz when compared with carrier power. Typical shapes of oscillator phase noise Phase noise of a closed loop ω n FIGURE 10. Typical output spectrum of a PLL 16

26 Frequency synthesizer Phase noise peaking occurs at frequency offset approximately equal to ω n. The peaking occurs due to the overshooting in a second order system. The overshooting can be reduced by increasing ζ to close to Frequency synthesizer The block diagram of the frequency synthesizer is shown in Figure 2. A phase-locked frequency synthesizer can be represented by substituting the circuit of Figure 11 for the VCO in the phase-locked loop. The output frequency, f out, is equal to the f fb N, and f fb is locked to the reference frequency. f out Kvco 1/N f fb Kvco=Kvco /N FIGURE 11. Frequency divider in a VCO For an integer-n frequency synthesizer, the output frequency is forced to be integer multiples of the reference frequency. Hence the reference frequency defines the frequency resolution of the frequency synthesizer which is usually the channel spacing. 17

27 Frequency synthesizer Another important feature of the frequency synthesizer is the transients response of the synthesizer. As the dividing radio, N, changes, the synthesizer takes a finite time for the output frequency to settle within an acceptable margin around the final frequency. The finite time is defined as settling time of the system. The settling time, t s, of the synthesizer is inversely proportional to the loop bandwidth, and the value is given in equation (25)[3], where α is the settling accuracy, and P is defined in equation (26)[3]. 1 P t s ln ζω n α 1 ζ 2 step size P = original frequency (25) (26) The loop bandwidth, as discuss in previous section, is defined by the frequency resolution. As a result the settling time is limited by the frequency resolution. It is desirable to increase the loop bandwidth of the loop. Higher the loop bandwidth allows a better noise suppression and improves the settling time. Another problem in integer-n synthesizer is the large dividing ratio magnifies the frequency offset of the reference by N times. For example a 1MHz reference is used to synthesizer a 2.4GHz LO. The dividing ratio is For a 10ppm crystal, in the worst case, there is a 10Hz offset at the reference frequency, the LO frequency offset is = 24kHz. 18

28 Dual loop architecture 2.4 Dual loop architecture The relationship between the channel spacing and the reference frequency of the integer-n phase-locked synthesizers can be altered by employing two or more loops. fout=2*f0+k(fref1-fref2) f1=f0+kfref1 f2=f0-kfref2 Loop 1 Loop 2 FIGURE 12. Dual-loop architecture using vernier effect A dual-loop architecture shown in Figure 12 is proposed in [4]. Two frequency synthesizers generates outputs at f 1 =f 0 +kf ref1 and f 2 =f 0 -kf ref2. The two signals are mixed to produce an output frequency of f out =2f 0 +k(f ref1 -f ref2 ). The output frequency resolution is equal to f ref1 - f ref2, while f ref1 and f ref2 can remain large. The primary difficulty exists for the architecture in Figure 12. Both the oscillators are oscillating at frequency which is very close to each other and may experience pulling. Another disadvantage is the mixer generates cross products of the harmonics and creates spurs, which may fall into the desired band. 19

29 Dual loop architecture fout=mxfref1+nxfref2 fref1 PD LF VCO Precaler M fout2=fref2 x N fref2 PD LF VCO Precaler N FIGURE 13. Improved dual loop architecture An improved dual loop architecture is shown in Figure 13. A secondary loop is used to synthesize output at f out2 =f ref2 N. The f out2 mixed with the VCO output of the primary loop, lower pass filtered and feedback to the prescaler. The output of the mixer which is at difference of the two VCOs output frequencies is locked to M f ref1. Hence at the output of the primary VCO, we have f out =M f ref1 +N f ref2.iff ref2 =f ref1 +f step, then f out =(M+N) f ref1 +N f step. By maintaining M+N = constant, the output frequency can be varied by varying N. In this architecture, the output frequencies of the VCOs are different and pulling can be avoided. Furthermore, the prescalers are running at lower speed and are easier to implement. 20

30 Dual loop architecture Also cross products of the mixer can be avoided by careful frequency planning. The reference offset is also magnified by smaller number by reducing the dividing ratio. The following configuration is used in our system. 1. f ref1 = 1.65MHz 2. f ref2 = 2.15MHz 3. f step = f ref2 - f ref1 = 500kHz 4. M = N = The required tuning range of the primary VCO is f omin =(M max +N min ) f ref1 +N min f step = 2.370GHz to f omax =(M min +N max ) f ref1 +N max f step = 2.498GHz, where M min is minimum value of M, M max is the maximum value of M, N min is the minimum value of N and N max is the maximum value of N. The required tuning range of the secondary VCO is f o2min =N min f ref2 = 1.1G Hz to f o2max =N max f ref2 = GHz. The reference frequency is increased from 500kHz to 1.65MHz and 2.15MHz. The choice of M and N is mainly limited by the tuning range of the secondary VCO. The dual loop architecture is simulated in Matlab. The input of the primary VCO is shown in Figure 14, the simulation result shows that the settling time improved to be less than 30µs. 21

31 Dual loop architecture x 10 5 FIGURE 14. Matlab simulation result for the dual loop frequency synthesizer The ripples at the input of the VCO after settling is generated by the XOR type phase detectors used in the simulation. The ripples can be reduced by using other type of phase detector. The ripples result in sideband spurs at the output of the VCO. 22

32 Voltage Controlled Oscillator CHAPTER 3 Hardware Implementation In this chapter, varies building blocks of the loop is discussed. Building blocks of the synthesizer include the RF VCOs, mixer, high speed prescalers, some high speed digital circuits for control purposes and charge-pumping phase detectors. Some of the building blocks is fabricated and tested in a 0.35µm Digitial CMOS technology. The difficulties for designing the building blocks are discussed. The proposed solutions, which include an innovative wide tuning range varactor, are presented. 3.1 Voltage Controlled Oscillator The high performance voltage controlled oscillator (VCO) is a key issue for high performance frequency synthesizer. Ideally, a VCO generates a frequency that is proportional to the input voltage. When a voltage is applied to the input of the VCO, the output of the frequency can be written as equation (27). V() t = Asin( ω 0 t + φ() t ) (27) 23

33 Voltage Controlled Oscillator where φ(t) is a time independent function. However, φ(t) is usually a random process, it introduces jitter on the total phase, which creates phase noise in V(t). The phase noise is usually characterized in terms of single sided spectral noise density. Monolithic LC-tank CMOS oscillators with on-chip spiral inductors have been intensively studied to improve the phase noise performance[6][7]. Challenges, however, still lie ahead in achieving reliable monolithic VCOs. For one thing, the process variation makes it rather difficult to accurately produce a VCO with the right centre frequency and tuning range. One possibility is to enhance the tuning range of the LC-tank so as to offer some compensation over process variation. In a LC-tank VCO, a varactor is primarily used as the tuning element. Thus, the tuning range of the VCO is strongly related to the tuning range of the varactors. The traditional PN junction varactor is quite limited in the tuning range. One way to overcome the problem is to employ a switched tuning VCO[8]. Such an approach increases the circuit complexity and may not be preferred. Alternatively, innovation can be made with the varactor itself. Accumulation-mode varactors with a tuning range of ±30% and nominal capacitance of 1pF and 3.1pF have been reported[9][10]. We have proposed a innovative wide tuning range varactor in [11][12] achieving ±50% in tuning range with nominal capacitance of 1.5pF Oscillator Theory Before we further discuss on the new varactor. The oscillator theory is revised. An LC-tank oscillator is a feedback network with an LC tank as the feedback circuit. Oscillation occurs at the frequency at which the loop transfer function is 1 and have zero phase shift. In reality, the loop transfer function is always designed to have value greater than 1, but have zero phase 24

34 Voltage Controlled Oscillator shift at the oscillating frequency. The amplitude of oscillation is usually limited by nonlinear effects. - Vout + G M Rp C L Rc R L FIGURE 15. An LC tank oscillator For the oscillator shown in Figure 15. The oscillation conditions are shown by [13] as (28),(29) and (30). 1 ω 0 = LC 1 R eff = R c + R l ( ω 0 C) 2 R p G M = R eff ( ω 0 C) 2 (28) (29) (30) From equation (30), if we increase the value of C, the power consumption of the VCO increases, but the action improves the tuning range. The major criteria of an oscillator is to have good phase noise performance. Besides, the tuning range and the tuning characteristic is also critical for an oscillator. 25

35 Voltage Controlled Oscillator An oscillator is a periodically time varying system. The time varying nature of the VCO converts the noise around integer multiples of the oscillating frequency into phase noise. The major noise sources are noise generated in transistors in the Gm cell and the thermal noise by varies resistance in circuit. A detail analysis on the effect of varies noise source is shown in [14]. The noise generated by a transistor is shown in equation (31). Due to the hot carrier effect, the value of γ in equation (31) can be as high as 3 in a short channel devices, while γ is around 2/3 for long channel devices. g do is the channel conductance and is defined as the resistance at the drain node at V ds =0. g do is a function of W, L and V gs. i noise 2 = 4KTγg d0 K I a f f b (31) To improve the phase noise, we should increase the ratio of the carrier power to the noise power. One way to do it is to increase the size of the transistors and reduces the biasing current. Keeping g do constant, the thermal noise generated by the transistors are kept at a constant level, but the 1/f noise reduces due to the increase in the total gate area. However, increasing the gate dimension, the gate capacitance contributes a larger portion of the total capacitance required for oscillation, the tuning range reduced. Another noise source is the thermal noise of the series resistance of the inductors. The noise generates by the a resistor is shown in equation (32). v noise 2 = 4KTR (32) 26

36 Voltage Controlled Oscillator To minimize the noise power generated by the series resistance, the Q factor of the inductor should be maximized. ω 0 2X ω 0 FIGURE 16. Conversion of noise around integer multiples of the oscillating frequency into phase noise Spiral inductors The phase noise and power consumption of an oscillator greatly depends on the Q factor of the inductors. Higher the Q factor, better the noise performance and lower the power consumption. On-chip inductors are realized as spiral inductors. The basics for the inductance calculation of these planar spiral inductors were developed by Greenhouse in 1974[15]. The theory predicts the inductance within ±5%. 27

37 Voltage Controlled Oscillator Via Second Layer of Metal Top Layer of Metal Oxide Substrate FIGURE 17. A spiral inductor The resistive losses in the substrate and low self-resonant frequency are the most important limitations in using planar spiral inductors in a standard CMOS process. These factors limit the value of inductors to be at 2-10nH with Q-factor of 2-8 at 2GHz where Q is defined as Im{ Z} Re{ Z} = X --- R A model for a spiral inductor with the substrate effect proposed in [16] is shown in Figure 18. C ox, C si and R si are used to model the substrate effect. The Q-factor of the inductor is shown in [16] as in equation (33). Q = ωl s R s R p R s ( C p + C s ) ω 2 R p + [(( ωl s ) R s ) 2 L + 1] R L s ( C p + C s ) s s (33) Substrate Loss Factor Self-Resonance Factor 28

38 Voltage Controlled Oscillator where R p and C p are the extracted parallel resistance and capacitance of the substrate model. The value of R p and C p are shown in equation (34) 2 C si 1 R R p si C ox ω 2 ( C ox + C si )C si R si = C ω 2 C 2 2 p = C ox ox R si C ox 1 ω 2 ( C ox + C si ) R si 2 (34) Cs Cox Ls Rs Cox Rsi Csi Rsi Csi FIGURE 18. Model of a spiral inductor Cox Rp Cp Rsi Csi FIGURE 19. Substrate model If the substrate loss factor and the self resonance factor are set 1, equation (33) reduces to ωl Q = s, the two factors are always smaller than 1. The Q factor of the inductor can be R s improved by reducing C ox. 29

39 Voltage Controlled Oscillator To reduce C ox, we can either reduce the thickness of the oxide or reduce the total area of the inductor. Since the oxide thickness is limited by the process, the only choice for a designer is to reduce the total area of the inductor. However, reducing the area of the inductor, usually results in reducing L s or increasing R s, both factors reduce the Q factor by reducing the first term in equation (33). There exist some metal width, at which the Q factor of the inductor is maximized. Intensive studies in maximize the Q of the inductor [6][13][16] have suggested that width metal width is not efficient. Besides hollow coils show be used. The resistance of the inner coils increase enormously due to eddy currents induced by the magnetic flux. The inner coils contribute little to the total inductance while contribute a lot to the series resistance. Employing hollow inductor design, maximizes the Q by increasing the inductance to resistance ratio. The magnetic flux also penetrates through the substrate and induces eddy current and causes energy lost. Large coils induce flux penetrates deeper into the substrate. Hence very large coils are not efficient Varactor Commonly used varactors include the PN junction varactors, the PMOS varactors and the accumulation-mode varactors. The structures of these varactors are shown in Figure

40 Voltage Controlled Oscillator a) N+ P+ N+ N-Well b) P+ P+ N-Well c) N+ N+ N-Well FIGURE 20. a) a PN junction varactor, b) an PMOS capacitor varactor and c) an accumulation -mode varactor The PN junction varactor consists of a P+ and an N+ region residing in an N-Well. The depletion region is formed between the P+ region and N-Well. The tuning range provided by a PN junction varactor varies with the doping profile. Typical PN junction varactors provide a ±10% tuning range. The PMOS varactor utilizes the gate capacitance of a PMOS transistor. While providing a wider tuning range than the PN junction varactors, the tuning range of the PMOS varactors is limited by the source and drain parasitic capacitance. In an accumulationmode varactor, the N+ contacts replace the source and drain of a PMOS varactor. Accumulation-mode varactors achieve a tuning range of ±30% after the removal of the parasitic source/ drain capacitance. 31

41 Voltage Controlled Oscillator The gated varactor structure is shown in Figure 21. The structure is similar to a PMOS transistor except that the drain node is replaced by an N+ contact. The gated varactor can be considered to be a combination of the three varactor structures mentioned above. Replacing only the drain node by an N+ region while keeping the source node as P+, the gated varactor provides a wider tuning range by varying the source capacitance. Gate Drain Source Gate Drain N+ P+ Source N-Well FIGURE 21. Cross-sectional view of the gated varactor The new structure is a three terminal device. The first terminal connected to the N+ contact is defined as the drain node. The gate node is connected to the poly-silicon gate. The P+ node is defined as the source node. In this study, the capacitance of the device is defined as the capacitance looking into the drain node. These notations are shown in Figure

42 Voltage Controlled Oscillator The capacitance can be varied by changing the potential difference between either the drain node and the gated node, or the drain node and the source node. The characteristics and the physics behind the gated varactor are discussed in later sections of this paper. The capacitance consists of several capacitances the gate capacitance, the junction capacitance, and some parasitic. Due to the presence of these capacitances, the gated varactor is able to offer a higher capacitance per unit area than the other implementations. The implemented varactor records a capacitance per unit area of ff/µm 2. The new structure is fully compatible with the standard CMOS process, and does not require any post-processing. In order to understand the operation of the varactor, a device simulation tool, MEDICI, is used to simulate the carrier concentration of the device with a standard bulk CMOS process. N-Well doping concentration of cm -3 is set. The structure is simulated under different biasing condition. The simulation is used to develop a set of theories that explain the operation of the device. The experiment was divided into two parts. In the first part, we examined the impact of varying the voltage at the gate node. In the second part, we examined the effect of varying the voltage at the drain node. In both cases, the source node was connected to ground. The simplified MEDICI simulation results are shown in Figure 22. In order to improve the readability of the simulation results, we redrew the diagrams and showed only the important information of the simulation. Figure 22 shows the carrier concentration under different gate 33

43 Voltage Controlled Oscillator biasing. The drain and the source node are grounded. The darkened region represents the depletion region. The depletion region shrinks as the voltage at the gate increases. C Vg N+ P+ depletion region shrinks as Vg increases depletion region N-Well FIGURE 22. Simplified MEDICI simulation showing the carrier concentration under different gate bias The operation of the gated varactor is similar to the operation of the accumulation-mode varactor. Increasing the gate voltage moves the varactor towards the accumulation mode and the capacitance increases. In Figure 23, a similar diagram with the drain biased at different voltage is shown. The gate node and the source node are grounded while the drain voltage is varied. Varying the drain voltage has two impacts on the device. Despite the finite resistance of the N-Well structure, the drain node and the N-Well should have roughly the same potential. Increasing the drain voltage increases the potential of the N-Well. And as the potential difference between the gate and the N-Well reduces, the device moves into inversion mode. This is shown by arrow 1 in Figure 23. The depletion region extends as the device moves towards inversion mode and reduces the capacitance that looks into the drain node. As the drain voltage increases the potential across the PN junction also increases. The depletion region across the PN junction 34

44 Voltage Controlled Oscillator widens, and the capacitance further reduces. One may notice that the depletion region extends at the subsurface region of the N-Well at which the gate loses control of the carrier concentration. This phenomena is similar to the sub-surface DIBL effect and occurs at the lower doping region at the subsurface. When the drain voltage increases to a certain point, a depletion region which formed underneath the gate merges with the depletion region which formed at the subsurface. The capacitance looking into the drain reaches its minimum at the point. C N+ P+ N-Well 2 depletion region FIGURE 23. Simplified MEDICI simulation showing the carrier concentration under different drain bias The total capacitance of the gate primarily consists of three components: the gate capacitance, the junction capacitance and some parasitic. While the first two components offer the varactor the ability to tune its capacitance, the last component limits the capacitance at some finite value. The maximum capacitance can be estimated by equation (35). C total = C ox + C j + C min (35) C total is the total capacitance that looks into the drain. C ox is the oxide capacitance. C j is the junction capacitance and C min includes the overlapping capacitance, the interconnection 35

45 Voltage Controlled Oscillator capacitance and the other parasitic capacitance that may appear at the drain node. When reaching its minimum capacitance, due to the subsurface depletion phenomena described, the C ox and C j offer little capacitance to the total capacitance. The minimum capacitance of the varactor is roughly equal to the quality C min. Compared with the accumulation-mode varactor, which has a maximum capacitance of Cox, the gated varactor offers a higher total capacitance. When the varactor reaches its minimum capacitance, the depletion region at the subsurface. This depletion enables the subsurface region, which cannot be depleted by controlling the gate voltage, to be depleted, and leads to a lower minimum capacitance. Figure 24 shows the carrier concentration of these cases. Essentially, with a higher maximum capacitance and lower minimum capacitance, the gated varactor allows a wider tuning range. 36

46 Voltage Controlled Oscillator depletion region N+ P+ N-Well a) Maximum Capacitance N P N-Well depletion region b) Minimum Capacitance FIGURE 24. The carrier concentration of the varactor when reaching its a) maximum capacitance and minimum capacitance A testing varactor was fabricated using a 0.35µm digital CMOS process. The measured varactor consists of 100 segments with total gate dimension of 500µm by 0.4µm, The size of each segment including the gate, source and drain is 5 µm 1.6µm. Fingering reduces the gate resistance. The measurement was done by a network analyzer. The 2-port S-parameters were measured with the drain node and the gate node as the ports. The source node was connected to the ground port. The capacitance and the resistance values were finally extracted from the 2-port S-parameters. The admittance looking from the drain was calculated from equation (36), while the equivalent R p and capacitance C eq was calculated as in equation (37) and (38). 37

47 Voltage Controlled Oscillator 1 S 11 Y = Y S 11 (36) R p = Re( y) 1 (37) C eq = Im( y) πf (38) The extracted capacitance is shown in Figure 25 with the x-axis showing the gate voltage and the family of curves representing the capacitance measured with the drain biasing voltage varying from 0V to 4V with a 1V step. With an oxide thickness, t ox, of 7.5nm, junction bottom capacitance, C jo,of F/m 2, and junction sidewall capacitance, C jsw,of F/m and gate to drain parasitic capacitance, C gdo of F/m, the capacitances are calculated as in equation (39) to equation (41). C ox = εa t ox (39) = 0.94 pf where A = 500µm 0.4µm C j = C jo A source + C jsw w (40) = 0.66 pf where A source = 500µm 1.2µm C min = C gdo w + C pad + C inter (41) = 0.55 pf where C pad + C inter 0.3 pf 38

48 Voltage Controlled Oscillator Vd=0V 2 Vd=1V 1.8 Increasing Vd Vd=2V Capacitance Vd=3V Vg FIGURE 25. Measured capacitance under different bias The A source is the area of the source node, w, the gate width is 500µm in our varactor. C pad and C inter is estimated by multiplying the metal area with the capacitance per unit area measured. Substituting the values in equation (35), we get C max =2.15pF and C min =0.55pF. 0.66pF of the total capacitance is provided by the PN junction which is roughly about 30% of the total tuning range. Compared with the measured values, the equation is correct within ±10%. If one of the curves in Figure 25 is looked at, the behaviour of the varactor is similar to an accumulation-mode varactor. When the drain voltage is varied, the curves shift to the right and experience a reduction in the minimum capacitance. This corresponds to the effect of driving the device to inversion mode with subsurface depletion. The tuning range is calcu- 39

49 Voltage Controlled Oscillator lated with equation (42). With a center capacitance of 1.5pF, the fabricated varactor achieves a tuning range of ±53%, from 0.7pF to 2.3pF. tuning range = 1 ±-- C max C min 2 + C max C min (42) The Q factor of the varactor is shown in Figure 26. In the graph both axes are shown in log scale. The measured Q value, when measured, exceeded 20 at 2GHz. A capacitor C eq with a parallel resistor R p and a series resistor R s represent a simplified model for the varactor. The series resistance includes the contact resistance, gate resistance and the N-Well resistance. The parallel resistance is an equivalent resistance related to the generation-recombination current, diffusion current and surface leakage current. For a given bias, Q varies a ωc eq R p at low frequency and as 1/ωC eq R p at high frequency. Vd=2V Q factor 10 Vd=1V Vd=0V 1 10 frequency (GHz) FIGURE 26. Measured Q-factor of the varactor 40

50 Voltage Controlled Oscillator Voltage Controlled Oscillator Two voltage controlled oscillators are fabricated in 0.35µm CMOS processes which is provided by HP and TSMC. Both VCOs have inductors fabricated with the third layer of metal. Gated varactors are used as the tuning element. A circuit topology is developed to utilized the third terminal to maximize the tuning range. The topology forces the varactors to traverse across the family of curves in Figure 25, while keeping the VCO as a single input block. The oscillators with gated varactors can be used in a phase-locked loop system without modifying the system architecture to accumulate the third terminal which is not presented in traditional VCOs. The schematic of the VCO fabricated in the HP process is shown in Figure 27. The LC tank consists of inductors of 2nH. The drain nodes of the varactors are biased at 1V. The sources of the varactors are connected to the output of a source follower to provide a level shifting from the tuning voltage. The tuning voltage also controls the voltage bias of the gate nodes directly. The level shifting of 1.5V provided by the source follower prevents the PN junctions of the varactors from forward biasing. When V tune is set to 0V, the PN junctions are reverse biased at 1V and the potential of the N- Wells (drain node voltage) is lower than the gate by 0.5V. When the tuning voltage, V tune, increases, the voltage across the drain and the source nodes drops. As discussed in previous sections this action increases the capacitance of the varactor. At the same time, as V tune increases, the gate voltage also goes up. This drives the device from inversion mode to accumulation mode and the capacitance further increases. With both actions moving the capacitance to the higher capacitance region, this circuit topology provides maximum VCO gain 41

51 Voltage Controlled Oscillator and tuning range. The capacitance tuning characteristic is shown with a solid line in Figure 28. The capacitance of the varactor is now varied by one tuning voltage as in conventional varactors. Long channel devices are used in the tuning source follower. The noise injected by the NMOS transistors can be described by equation (31). Using long channel devices also increases the gate area and hence reduces the 1/f noise. 7.5mA 2nH 2nH 70u/2u 104u/0.4u 104u/0.4u Vtune FIGURE 27. VCO fabricated in HP 0.35µm process 42

52 Voltage Controlled Oscillator Capacitance Vg FIGURE 28. Capacitance tuning characteristic The tuning characteristic of the VCO is shown in Figure 29. The frequency of oscillation varies by 320MHz with a 1.4V variation in the tuning voltage Increaseing Vd Frequency (G Hz) Family of curves showing the VCO frequency at different Vg and Vd. Utilizing configuration mentioned above Tuning Voltage (V) FIGURE 29. Tuning characteristic of the VCO with HP process 43

53 Voltage Controlled Oscillator The VCO, excluding the output buffers, draws 7.5mA from a 3V supply. The output power, when driving a 50 ohm loading through a source follower is measured to be -6dBm. The phase noise is measured to be -87dBc/Hz at 100kHz offset and -105dBc/Hz at 1MHz offset. FIGURE 30. The output spectum of VCO with the HP process In order to improve the phase noise performance of the VCO, the VCO is redesigned. The current bias for the tuning source follower is reduced from 1mA to 50uA and a new inductor is designed. The reduction in bias current of the source follower reduces the noise injected by the tuning circuit. The values of the inductors are increased from 2nH to 3.7nH. The increase in inductor values reduced the capacitance required for oscillation and reduces the Gm required for oscillation, as a result, the noise injected by the transistors reduces. The schematic of the VCO is shown in Figure 31. The tuning circuit is not shown in the figure. Table 3 summarized the inductors used in the two runs. In the table, w is the width of the metal lines, 44

54 Voltage Controlled Oscillator s is the separation between the metal lines, z is the number of segments used. A is the length of the innermost metal line and L is the calculated inductance of the inductor. The measured inductance of the new inductor is 3.8nH, when compared with the designed value 3.7nH, the difference is less than 3%. The measured Q is 3.5 compared with simulated Q of 2 in the previous run. The measurement results are shown in Figure 32 to Figure mA 3.7nH 3.7nH 3.7nH 3.7nH 4u/0.4u 64u/0.4u 70 Ohm 64u/0.4u FIGURE 31. Schematic of 2.4G Hz VCO with TSMC process A 70 ohm tail resistance is used to adjust the DC bias of the VCO output. When implemented with poly-silicon, the resistance introduces a tail capacitor and a tail noise source. The effect of the tail capacitor and tail noise source in a LC tank VCO is studied in [17]. It is shown in [17] that only the noise around even harmonics of the oscillating frequency f 0 and at low frequency have a significant effect on the phase noise. At low frequency, the transistors 1/f noise dominates and the 1/f noise produced by the poly-silicon resistance is not significant. Furthermore, the poly-silicon resistance is made up by a piece of 8µm 70µm poly-silicon, 45

55 Voltage Controlled Oscillator the large area of the poly-silicon resistance reduces the 1/f noise injected into the circuit. At high frequency, the tail capacitance introduced by the large poly resistance provides a filtering to the high frequency noise produced. TABLE 3. Summary of Inductors used HP TSMC w(µm) s(µm) z A(µm) L(nH) Q factor Measured data with probe pad attracted deembedded data frequency (GHz) frequency (GHz) a) b) FIGURE 32. The measured impedance of the inductor a) real part, b) imaginary part. 46

56 Voltage Controlled Oscillator frequency (GHz) FIGURE 33. Measured Q factor of the inductor inductance (H) frequency (GHz) FIGURE 34. Extracted inductance The phase noise spectrum of the VCO at the 1/f 2 region can be calculated as equation (43)[14]. phase noise at offset of ω = 10 log 2FkT P s ω o Q ω (43) 47

57 Voltage Controlled Oscillator where P s is the average power dissipated in the resistive part of the tank, F is known as the device excess noise number and Q is the Q factor of the LC tank. For steady-state oscillation, 2 V mas 1 By equating P s = = 2 R V. V max is simulated to be increase from 400mV to 1V 2 max Gm and Gm is reduced by half by reducing the both the basing current and the W/L ratio by half. The factor Ps is 3 times in the new VCO. The estimated improvement in phase noise is ω o ω o2 Improvement in phase noise = 10log P s1 Q P s2 Q 2 (44) 2.4G G = 10log = 9dB 3P s P s 2 The fabricated VCO records a phase noise of dBc/Hz, dBc/Hz and -118dBc/ Hz at 100kHz, 600kHz and 1MHz offset respectively at 2.4GHz. The figures are obtained by averaging the measurement results of 5 measurements. The data is shown in Table 4. The phase noise improvement at 1M Hz is -13dB. The 4dB difference in measured and calculated phase noise improvement is mainly due to the derivation in fitting parameter, F. TABLE 4. Phase noise measurement at 2.4GHz 100k Hz offset 600k Hz offset 1M Hz offset dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz With the gated varactor, the tuning range of the VCO is as wide as 600MHz, the carrier frequency is able to tune from 2.419GHz to 1.77GHz. However, the phase noise of the VCO 48

58 Voltage Controlled Oscillator degrades rapidly when the carrier frequency is tuned to below 2GHz. The phase noise measured at 2GHz is dBc/Hz, dBc/Hz and dBc/Hz for 100kHz, 600kHz and 1MHz offset respectively. The phase noise measured at 1.77GHz is recorded as -81dBc/Hz, dBc/Hz and -108dBc/Hz at 100kHz, 600kHz and 1MHz respectively. The phase noise plots of the measurements are shown in Figure 35 to Figure 37. FIGURE 35. Phase noise plot, carrier frequency = 2.419GHz 49

59 Voltage Controlled Oscillator FIGURE 36. Phase noise plot, carrier frequency = 2.020GHz FIGURE 37. Phase noise plot, carrier frequency = 1.770GHz The performance of the phase noise degrades mainly due to the PN junctions are biased to a point close to forward bias, the leakage current across the varactor increases and reduces the Q factor of the varactors. 50

60 Voltage Controlled Oscillator The tuning characteristic of the VCO is shown Figure 38, and the die photo is shown in Figure 39. The measurement setup of the VCO is shown in Figure 40. Tuning characteristic 2.4GHz VCO frequency(ghz) voltage(v) FIGURE 38. The tuning characteristic of the VCO FIGURE 39. The die photo of the 2.4GHz VCO 51