Precision Instrumentation Amplifier AD524

Transcription

1 Data Sheet Precision Instrumentation Amplifier FEATURES Low noise:. μv p-p at. Hz to Hz Low nonlinearity:.% (G = ) High CMRR: db (G = ) Low offset voltage: 5 μv Low offset voltage drift:.5 μv/ C Gain bandwidth product: 5 MHz Pin programmable gains of,,, Input protection, power-on/power-off No external components required Internally compensated MIL-STD-B and chips available -lead ceramic DIP and SOIC packages and -terminal leadless chip carrier available Available in tape and reel in accordance with EIA-A standard Standard military drawing also available FUNCTIONAL BLOCK DIAGRAM INPUT G = G = G = RG RG INPUT PROTECTION.kΩ Ω Ω PROTECTION V b kω kω kω kω kω kω Figure. SENSE REFERENCE 5- GENERAL DESCRIPTION The is a precision monolithic instrumentation amplifier designed for data acquisition applications requiring high accuracy under worst-case operating conditions. An outstanding combination of high linearity, high common-mode rejection, low offset voltage drift, and low noise makes the suitable for use in many data acquisition systems. The has an output offset voltage drift of less than 5 μv/ C, input offset voltage drift of less than.5 μv/ C, CMR above db at unity gain ( db at G = ), and maximum nonlinearity of.% at G =. The gain bandwidth product of the is 5 khz (G = ). The output slew rate of 5 V/μs and settling time of 5 μs to.% for gains of to, makes it suitable for high speed data acquisition systems. As a complete amplifier, the does not require any external components for fixed gains of,,, and. For other gain settings between and, only a single resistor is required. The input is fully protected for both power-on and power-off fault conditions. The is available in four versions of accuracy and operating temperature range. The economical A grade, the low drift B grade, and lower drift, higher linearity C grade are specified from 5 C to 5 C. The S grade guarantees performance to specification over the extended temperature range 55 C to 5 C. The is available in a -lead ceramic DIP, -lead SBDIP, -lead SOIC wide packages, and -terminal leadless chip carrier. PRODUCT HIGHLIGHTS. Guaranteed low offset voltage, low offset voltage drift, and low noise for precision high gain applications.. Functionally complete with pin programmable gains of,,, and, and single resistor-programmable for any gain.. Input and output offset nulling terminals are provided for high precision applications and to minimize offset voltage changes in gain ranging applications.. Input protected for both power-on and power-off fault conditions. 5. Superior dynamic performance with a gain bandwidth product of 5 MHz, full power response of 5 khz and a settling time of 5 μs to.% of a V step (G = ). Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box, Norwood, MA -, U.S.A. Tel:.. Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... Functional Block Diagram... General Description... Product Highlights... Revision History... Specifications... Absolute Maximum Ratings... Connection Diagrams... ESD Caution... Typical Performance Characteristics... Test Circuits... Theory of Operation... 5 Input Protection... 5 Data Sheet Input Offset and Output Offset... 5 Gain... Input Bias Currents... Common-Mode Rejection... Grounding... Sense Terminal... Reference Terminal... Programmable Gain... Auto-Zero Circuits... Error Budget Analysis... References... Outline Dimensions... Ordering Guide... 5 REVISION HISTORY / Rev. F to Rev. G Changes to General Description... Change to Output Offset Voltage vs. Temperature Parameter, Unit Column, Table... Added References Section... Updated Outline Dimensions... Changes to Ordering Guide... 5 / Rev. E to Rev. F Updated Format... Universal Changes to General Description... Changes to Figure... Changes to Figure and Figure Captions... Changes to Error Budget Analysis Section... Changes to Ordering Guide... 5 / Rev. D to Rev. E Rev. G Page of 5

3 Data Sheet SPECIFICATIONS At VS = ±5 V, RL = kω and TA = 5 C, unless otherwise noted. All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at the final electrical test. Results from those tests are used to calculate outgoing quality levels. Table. A B Parameter Min Typ Max Min Typ Max Unit GAIN Gain Equation (External Resistor Gain Programming),, ± % ± % R G R G Gain Range (Pin Programmable) to to Gain Error G = ±.5 ±. % G = ±.5 ±.5 % G = ±.5 ±.5 % G = ±. ±. % Nonlinearity G = ±. ±.5 % G =, G = ±. ±.5 % G = ±. ±. % Gain vs. Temperature G = 5 5 ppm/ C G = 5 ppm/ C G = 5 5 ppm/ C G = 5 ppm/ C VOLTAGE OFFSET (May be Nulled) Input Offset Voltage 5 µv vs. Temperature.5 µv/ C Output Offset Voltage 5 mv vs. Temperature 5 µv/ C Offset Referred to the Input vs. Supply G = 5 db G = 5 5 db G = 5 5 db G = db INPUT CURRENT Input Bias Current ±5 ±5 na vs. Temperature ± ± pa/ C Input Offset Current ±5 ±5 na vs. Temperature ± ± pa/ C Rev. G Page of 5

4 Data Sheet A B Parameter Min Typ Max Min Typ Max Unit INPUT Input Impedance Differential Resistance Ω Differential Capacitance pf Common-Mode Resistance Ω Common-Mode Capacitance pf Input Voltage Range Maximum Differential Input Linear (VDL) ± ± V Maximum Common-Mode Linear (VCM) G G V V VD V VD Common-Mode Rejection DC to Hz with kω Source Imbalance V G = 5 db G = 5 db G = 5 db G = 5 db RATING VOUT, RL = kω ± ± V DYNAMIC RESPONSE Small Signal db G = MHz G = khz G = 5 5 khz G = 5 5 khz Slew Rate V/µs Settling Time to.%, V Step G = to 5 5 µs G = 5 5 µs NOISE Voltage Noise, khz RTI nv/ Hz RTO nv Hz RTI,. Hz to Hz G = 5 5 µv p-p G = µv p-p G =,.. µv p-p Current Noise. Hz to Hz pa p-p SENSE INPUT RIN kω ± % IIN 5 5 µa Voltage Range ± ± V Gain to Output % REFERENCE INPUT RIN kω ± % IIN 5 5 µa Voltage Range ± ± V Gain to Output % Rev. G Page of 5

5 Data Sheet A B Parameter Min Typ Max Min Typ Max Unit TEMPERATURE RANGE Specified Performance C Storage C POWER SUPPLY Power Supply Range ± ±5 ± ± ±5 ± V Quiescent Current ma Does not include effects of external resistor, RG. VOL is the maximum differential input voltage at G = for specified nonlinearity. VDL at the maximum = V/G. VD = actual differential input voltage. Example: G =, VD =.5. VCM = V (/.5 V) =.5 V. At VS = ±5 V, RL = kω and TA = 5 C, unless otherwise noted. All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at the final electrical test. Results from those tests are used to calculate outgoing quality levels. Table. C S Parameter Min Typ Max Min Typ Max Unit GAIN Gain Equation (External Resistor Gain Programming),, ± % ± % R G R G Gain Range (Pin Programmable) to to Gain Error G = ±. ±.5 % G = ±. ±.5 % G = ±.5 ±.5 % G = ±.5 ±. % Nonlinearity G = ±. ±. % G =, G = ±. ±. % G = ±. ±. % Gain vs. Temperature G = 5 5 ppm/ C G = ppm/ C G = 5 5 ppm/ C G = 5 5 ppm/ C VOLTAGE OFFSET (May be Nulled) Input Offset Voltage 5 µv vs. Temperature.5. µv/ C Output Offset Voltage.. mv vs. Temperature 5 5 µv Offset Referred to the Input vs. Supply G = 5 db G = 5 db G = 5 db G = 5 db Rev. G Page 5 of 5

6 Data Sheet C S Parameter Min Typ Max Min Typ Max Unit INPUT CURRENT Input Bias Current ±5 ±5 na vs. Temperature ± ± pa/ C Input Offset Current ± ±5 na vs. Temperature ± ± pa/ C INPUT Input Impedance Differential Resistance Ω Differential Capacitance pf Common-Mode Resistance Ω Common-Mode Capacitance pf Input Voltage Range Maximum Differential Input Linear (VDL) ± ± V Maximum Common-Mode Linear (VCM) G G V V VD V VD Common-Mode Rejection DC to Hz with kω Source Imbalance V G = db G = db G = db G = db RATING VOUT, RL = kω ± ± V DYNAMIC RESPONSE Small Signal db G = MHz G = khz G = 5 5 khz G = 5 5 khz Slew Rate V/µs Settling Time to.%, V Step G = to 5 5 µs G = 5 5 µs NOISE Voltage Noise, khz RTI nv/ Hz RTO nv Hz RTI,. Hz to Hz G = 5 5 µv p-p G = µv p-p G =,.. µv p-p Current Noise. Hz to Hz pa p-p SENSE INPUT RIN kω ± % IIN 5 5 µa Voltage Range ± ± V Gain to Output % Rev. G Page of 5

7 Data Sheet C S Parameter Min Typ Max Min Typ Max Unit REFERENCE INPUT RIN kω ± % IIN 5 5 µa Voltage Range V Gain to Output % TEMPERATURE RANGE Specified Performance C Storage C POWER SUPPLY Power Supply Range ± ±5 ± ± ±5 ± V Quiescent Current ma Does not include effects of external resistor RG. VOL is the maximum differential input voltage at G = for specified nonlinearity. VDL at the maximum = V/G. VD = actual differential input voltage. Example: G =, VD =.5. VCM = V (/.5 V) =.5 V. Rev. G Page of 5

8 ABSOLUTE MAXIMUM RATINGS Table. Parameter Supply Voltage Internal Power Dissipation Input Voltage (Either Input Simultaneously) VIN VS Output Short-Circuit Duration Storage Temperature Range (R) (D, E) Operating Temperature Range A/B/C S Lead Temperature (Soldering, sec) Rating ± V 5 mw < V Indefinite 5 C to 5 C 5 C to 5 C 5 C to 5 C 55 C to 5 C C Maximum input voltage specification refers to maximum voltage to which either input terminal may be raised with or without device power applied. For example, with ± volt supplies maximum, VIN is ± V; with zero supply voltage maximum, VIN is ± V. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. NULL NULL 5 RG INPUT G = G = G = SENSE. (.) CONNECTION DIAGRAMS INPUT INPUT RG INPUT NULL INPUT NULL 5 REFERENCE INPUT OFFSET NULL RG INPUT NULL 5 NC INPUT NULL REFERENCE TOP VIEW (Not to Scale) 5 RG 5 NULL NULL G = G = G = SENSE 5 OFFSET NULL Figure. Ceramic (D) and SOIC (RW- and D-) Packages INPUT INPUT NC RG NULL TOP VIEW (Not to Scale) NC = NO CONNECT NC SENSE INPUT OFFSET NULL 5 Data Sheet SHORT TO RG FOR DESIRED GAIN 5- NULL G = SHORT TO NC RG FOR 5 G = DESIRED GAIN G = OFFSET NULL Figure. Leadless Chip Carrier (E) 5- INPUT RG ESD CAUTION INPUT NULL 5 INPUT NULL. (.) REFERENCE PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE D- AND RW- -LEAD CERAMIC PACKAGES. Figure. Metallization Photograph Contact factory for latest dimensions; Dimensions shown in inches and (mm) 5- Rev. G Page of 5

9 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS INPUT VOLTAGE (±V) C QUIESCENT CURRENT (ma) 5 5 SUPPLY VOLTAGE (±V) SUPPLY VOLTAGE (±V) 5- Figure 5. Input Voltage Range vs. Supply Voltage, G = Figure. Quiescent Current vs. Supply Voltage VOLTAGE SWING (±V) 5 5 INPUT BIAS CURRENT (±na) SUPPLY VOLTAGE (±V) SUPPLY VOLTAGE (±V) Figure. Output Voltage Swing vs. Supply Voltage Figure. Input Bias Current vs. Supply Voltage VOLTAGE SWING (V p-p) INPUT BIAS CURRENT (na) k k LOAD RESISTANCE (Ω) TEMPERATURE ( C) 5- Figure. Output Voltage Swing vs. Load Resistance Figure. Input Bias Current vs. Temperature Rev. G Page of 5

10 Data Sheet G = G = INPUT BIAS CURRENT (±na) CMRR (db) G = G = 5 5 INPUT VOLTAGE (±V) Figure. Input Bias Current vs. Input Voltage 5- k k k M M FREQUENCY (Hz) Figure. CMRR vs. Frequency, RTI, Zero to Source Imbalance 5- ΔV OS FROM FINAL VALUE (µv) 5 5 WARM-UP TIME (Minutes) Figure. Offset Voltage, RTI, Turn-On Drift 5- FULL POWER RESPONSE (V p-p) G =,, BANDWIDTH LIMITED G = G = G = k k k M FREQUENCY (Hz) Figure 5. Large Signal Frequency Response 5-5 GAIN (V/V) SLEW RATE (V/µs) G = k k k M M FREQUENCY (Hz) Figure. Gain vs. Frequency 5- GAIN (V/V) Figure. Slew Rate vs. Gain 5- Rev. G Page of 5

11 Data Sheet POWER SUPPLY REJECTION RATIO (db) k k k FREQUENCY (Hz) = 5V DC V p-p SINEWAVE G = G = G = G = Figure. Positive PSRR vs. Frequency 5- CURRENT NOISE SPECTRAL DENSITY (fa/ Hz) k k k k k FREQUENCY (Hz) Figure. Input Current Noise vs. Frequency 5- POWER SUPPLY REJECTION RATIO (db) k k k FREQUENCY (Hz) G = G = G = G = = 5V DC V p-p SINEWAVE 5-.Hz TO Hz 5mV s VERTICAL SCALE; DIVISION = 5µV 5- Figure. Negative PSRR vs. Frequency Figure. Low Frequency Noise, G = (System Gain = ).Hz TO Hz mv s G = VOLT NSD (nv/ Hz) G = G =, G =. k k k FREQUENCY (Hz) 5- VERTICAL SCALE; DIVISION =.µv 5- Figure. RTI Noise Spectral Density vs. Gain Figure. Low Frequency Noise, G = (System Gain =,) Rev. G Page of 5

12 Data Sheet TO TO %.%.% mv V µs TO STEP (V) TO TO %.%.% TO 5 5 SETTLING TIME (µs) Figure. Settling Time, Gain = 5- Figure. Large Signal Pulse Response and Settling Time, Gain = 5- mv V µs TO TO %.%.% TO STEP (V) TO Figure. Large Signal Pulse Response and Settling Time, Gain = 5- TO %.% TO.% 5 5 SETTLING TIME (µs) Figure. Settling Time, Gain = 5- TO TO %.%.% mv V µs TO STEP (V) TO TO %.%.% TO 5 5 SETTLING TIME (µs) Figure 5. Settling Time, Gain = 5-5 Figure. Large Signal Pulse Response and Settling Time, Gain = 5- Rev. G Page of 5

13 Data Sheet TO TO %.%.% 5mV V µs TO STEP (V) TO TO %.%.% TO 5 SETTLING TIME (µs) Figure. Settling Time, Gain = 5- Figure. Large Signal Pulse Response and Settling Time, Gain = 5- Rev. G Page of 5

14 Data Sheet TEST CIRCUITS INPUT V p-p kω.% kω kω Ω.%.%.% kω.% kω T kω.% RG G = G = G = RG Figure. Settling Time Test Circuit V OUT 5- I 5µA V B I 5µA A A C C R5 kω R5 kω SENSE IN CH, CH, CH CH I 5µA R5 kω R5 Q, Q kω Q, Q.kΩ RG Ω RG G = Ω G = I 5µA R5 kω CH, CH, CH A R55 kω CH V O REFERENCE IN Figure. Simplified Circuit of Amplifier; Gain is Defined as ((R5 R5)/(RG)) ; For a Gain of, RG is an Open Circuit 5- Rev. G Page of 5

15 Data Sheet THEORY OF OPERATION The is a monolithic instrumentation amplifier based on the classic -op amp circuit. The advantage of monolithic construction is the closely matched components that enhance the performance of the input preamplifier. The preamplifier section develops the programmed gain by the use of feedback concepts. The programmed gain is developed by varying the value of RG (smaller values increase the gain) while the feedback forces the collector currents (Q, Q, Q, and Q) to be constant, which impresses the input voltage across RG. As RG is reduced to increase the programmed gain, the transconductance of the input preamplifier increases to the transconductance of the input transistors. This has three important advantages. First, this approach allows the circuit to achieve a very high open-loop gain of at a programmed gain of, thus reducing gain-related errors to a negligible ppm. Second, the gain bandwidth product, which is determined by C or C and the input transconductance, reaches 5 MHz. Third, the input voltage noise reduces to a value determined by the collector current of the input transistors for an RTI noise of nv/ Hz at G =. INPUT PROTECTION As interface amplifiers for data acquisition systems, instrumentation amplifiers are often subjected to input overloads, that is, voltage levels in excess of the full scale for the selected gain range. At low gains ( or less), the gain resistor acts as a current limiting element in series with the inputs. At high gains, the lower value of RG does not adequately protect the inputs from excessive currents. Standard practice is to place series limiting resistors in each input, but to limit input current to below 5 ma with a full differential overload ( V) requires over kω of resistance, which adds nv Hz of noise. To provide both input protection and low noise, a special series protection FET is used. A unique FET design was used to provide a bidirectional current limit, thereby protecting against both positive and negative overloads. Under nonoverload conditions, three channels (CH, CH, CH) act as a resistance ( kω) in series with the input as before. During an overload in the positive direction, a fourth channel, CH, acts as a small resistance ( kω) in series with the gate, which draws only the leakage current, and the FET limits IDSS. When the FET enhances under a negative overload, the gate current must go through the small FET formed by CH and when this FET goes into saturation, the gate current is limited and the main FET goes into controlled enhancement. The bidirectional limiting holds the maximum input current to ma over the V range. INPUT OFFSET AND OFFSET Voltage offset specifications are often considered a figure of merit for instrumentation amplifiers. While initial offset may be adjusted to zero, shifts in offset voltage due to temperature variations causes errors. Intelligent systems can often correct this factor with an auto-zero cycle, but there are many smallsignal high-gain applications that do not have this capability. AD V s.kω µf / 5 RG.kΩ / µf µf G =,, G = kω Ω.MΩ Figure. Noise Test Circuit.kΩ.kΩ 5- Rev. G Page 5 of 5

16 Voltage offset and drift comprise two components each; input and output offset and offset drift. Input offset is the component of offset that is directly proportional to gain, that is, input offset as measured at the output at G = is times greater than at G =. Output offset is independent of gain. At low gains, output offset drift is dominant, at high gains, input offset drift dominates. Therefore, the output offset voltage drift is normally specified as drift at G = (where input effects are insignificant), whereas input offset voltage drift is given by drift specification at a high gain (where output offset effects are negligible). All input related numbers are referred to the input (RTI) that is the effect on the output is G times larger. Voltage offset vs. power supply is also specified at one or more gain settings and is also RTI. By separating these errors, one can evaluate the total error independent of the gain setting used. In a given gain configuration, both errors can be combined to give a total error referred to the input (RTI) or output (RTO) by the following formulas: Total error RTI = input error (output error/gain) Total error RTO = (gain input error) output error As an illustration, a typical might have a 5 µv output offset and a 5 µv input offset. In a unity gain configuration, the total output offset would be µv or the sum of the two. At a gain of, the output offset would be.5 mv or: 5 µv ( 5 µv) =.5 mv. The provides for both input and output offset adjustment. This simplifies very high precision applications and minimizes offset voltage changes in switched gain applications. In such applications, the input offset is adjusted first at the highest programmed gain, then the output offset is adjusted at G =. GAIN The has internal high accuracy pretrimmed resistors for pin programmable gains of,,, and. One of the preset gains can be selected by pin strapping the appropriate gain terminal and RG together (for G =, RG is not connected). INPUT RG G = G = G = RG INPUT kω INPUT OFFSET NULL Figure. Operating Connections for G = 5 V OUT SIGNAL COMMON 5- Data Sheet The can be configured for gains other than those that are internally preset; there are two methods to do this. The first method uses just an external resistor connected between Pin and Pin (see Figure 5), which programs the gain according to the following formula: R G kω = G = For best results, RG should be a precision resistor with a low temperature coefficient. An external RG affects both gain accuracy and gain drift due to the mismatch between it and the internal thin-film resistors. Gain accuracy is determined by the tolerance of the external RG and the absolute accuracy of the internal resistors (±%). Gain drift is determined by the mismatch of the temperature coefficient of RG and the temperature coefficient of the internal resistors ( 5 ppm/ C typical). INPUT.5kΩ kω INPUT RG.5kΩ RG V OUT REFERENCE, G = = ±%.5 Figure 5. Operating Connections for G = The second method uses the internal resistors in parallel with an external resistor (see Figure ). This technique minimizes the gain adjustment range and reduces the effects of temperature coefficient sensitivity. INPUT RG kω G = RG INPUT *R G = =.Ω *R G = =.Ω *R G = =.Ω *NOMINAL (±%) V OUT REFERENCE, G = = ±%. Figure. Operating Connections for G =, Low Gain Temperature Coefficient Technique Rev. G Page of 5

17 Data Sheet The can also be configured to provide gain in the output stage. Figure shows an H pad attenuator connected to the reference and sense lines of the. R, R, and R should be made as low as possible to minimize the gain variation and reduction of CMRR. Varying R precisely sets the gain without affecting CMRR. CMRR is determined by the match of R and R. INPUT INPUT G = RG G = G = G = RG (R kω) R R (R kω) R.kΩ R 5kΩ R.kΩ R L (R R R) R L kω Figure. Gain of V OUT Table. Output Gain Resistor Values Output Gain R R, R Nominal Gain 5 kω. kω. 5.5 kω.5 kω 5. kω. kω. INPUT BIAS CURRENTS Input bias currents are those currents necessary to bias the input transistors of a dc amplifier. Bias currents are an additional source of input error and must be considered in a total error budget. The bias currents, when multiplied by the source resistance, appear as an offset voltage. What is of concern in calculating bias current errors is the change in bias current with respect to signal voltage and temperature. Input offset current is the difference between the two input bias currents. The effect of offset current is an input offset voltage whose magnitude is the offset current times the source impedance imbalance. LOAD TO POWER SUPPLY GROUND Figure. Indirect Ground Returns for Bias Currents Transformer Coupled LOAD TO POWER SUPPLY GROUND Figure. Indirect Ground Returns for Bias Currents Thermocouple Rev. G Page of 5 LOAD TO POWER SUPPLY GROUND Figure. Indirect Ground Returns for Bias Currents AC-Coupled Although instrumentation amplifiers have differential inputs, there must be a return path for the bias currents. If this is not provided, those currents charge stray capacitances, causing the output to drift uncontrollably or to saturate. Therefore, when amplifying floating input sources such as transformers and thermocouples, as well as ac-coupled sources, there must still be a dc path from each input to ground. COMMON-MODE REJECTION Common-mode rejection is a measure of the change in output voltage when both inputs are changed equal amounts. These specifications are usually given for a full-range input voltage change and a specified source imbalance. Common-mode rejection ratio (CMRR) is a ratio expression whereas commonmode rejection (CMR) is the logarithm of that ratio. For example, a CMRR of, corresponds to a CMR of db. In an instrumentation amplifier, ac common-mode rejection is only as good as the differential phase shift. Degradation of ac common-mode rejection is caused by unequal drops across differing track resistances and a differential phase shift due to varied stray capacitances or cable capacitances. In many applications, shielded cables are used to minimize noise. This technique can create common-mode rejection errors unless the shield is properly driven. Figure and Figure show active data guards that are configured to improve ac common-mode rejection by bootstrapping the capacitances of the input cabling, thus minimizing differential phase shift. Ω Ω Ω AD INPUT G = RG INPUT Figure. Shield Driver, G INPUT AD RG RG INPUT Figure. Differential Shield Driver V OUT 5- REFERENCE V OUT 5- REFERENCE 5-

18 GROUNDING Many data acquisition components have two or more ground pins that are not connected together within the device. These grounds must be tied together at one point, usually at the system power-supply ground. Ideally, a single solid ground would be desirable. However, because current flows through the ground wires and etch stripes of the circuit cards, and because these paths have resistance and inductance, hundreds of millivolts can be generated between the system ground point and the data acquisition components. Separate ground returns should be provided to minimize the current flow in the path from the sensitive points to the system ground point. In this way, supply currents and logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors. Because the output voltage is developed with respect to the potential on the reference terminal, an instrumentation amplifier can solve many grounding problems. REFERENCE. µf. µf ANALOG P.S. 5V C 5V. µf DIG COM AD5 SAMPLE AND HOLD ANALOG GROUND*. µf DIGITAL P.S. 5V C µf µf SIGNAL GROUND AD5A µf 5 DIGITAL DATA *IF INDEPENDENT; OTHERWISE, RETURN AMPLIFIER REFERENCE TO MECCA AT ANALOG P.S. COMMON. Figure. Basic Grounding Practice SENSE TERMINAL The sense terminal is the feedback point for the instrument amplifier s output amplifier. Normally, it is connected to the instrument amplifier output. If heavy load currents are to be drawn through long leads, voltage drops due to current flowing through lead resistance can cause errors. The sense terminal can be wired to the instrument amplifier at the load, thus putting the IxR drops inside the loop and virtually eliminating this error source. V IN V IN V (SENSE) CURRENT BOOSTER X (REF) V Figure. Instrumentation Amplifier with Output Current Booster R L 5-5- Data Sheet Typically, IC instrumentation amplifiers are rated for a full ± volt output swing into kω. In some applications, however, the need exists to drive more current into heavier loads. Figure shows how a high current booster may be connected inside the loop of an instrumentation amplifier to provide the required current boost without significantly degrading overall performance. Nonlinearities and offset and gain inaccuracies of the buffer are minimized by the loop gain of the output amplifier. Offset drift of the buffer is similarly reduced. REFERENCE TERMINAL The reference terminal can be used to offset the output by up to ± V. This is useful when the load is floating or does not share a ground with the rest of the system. It also provides a direct means of injecting a precise offset. It must be remembered that the total output swing is ± V to be shared between signal and reference offset. When the is of the -amplifier configuration it is necessary that nearly zero impedance be presented to the reference terminal. Any significant resistance from the reference terminal to ground increases the gain of the noninverting signal path, thereby upsetting the common-mode rejection of the. In the, a reference source resistance unbalances the CMR trim by the ratio of kω/rref. For example, if the reference source impedance is Ω, CMR is reduced to db ( kω/ Ω = db). An operational amplifier can be used to provide that low impedance reference point, as shown in Figure 5. The input offset voltage characteristics of that amplifier adds directly to the output offset voltage performance of the instrumentation amplifier. V IN V IN SENSE REF LOAD V AD OFFSET Figure 5. Use of Reference Terminal to Provide Output Offset An instrumentation amplifier can be turned into a voltageto-current converter by taking advantage of the sense and reference terminals, as shown in Figure. INPUT SENSE INPUT REF A AD V X V IN, I L = = = ( ) R R R G R V X LOAD Figure. Voltage-to-Current Converter I L Rev. G Page of 5

19 Data Sheet By establishing a reference at the low side of a current setting resistor, an output current may be defined as a function of input voltage, gain, and the value of that resistor. Because only a small current is demanded at the input of the buffer amplifier (A) the forced current, IL, largely flows through the load. Offset and drift specifications of A must be added to the output offset and drift specifications of the. IN IN INPUT OFFSET TRIM R kω 5 PROTECTION PROTECTION 5 R kω kω kω kω kω kω.kω Ω Ω OFFSET TRIM NC RELAY SHIELDS G = K G = K G = K A kω OUT K D K D K D 5V ANALOG COMMON µf 5V C C GAIN TABLE A B GAIN K K = THERMOSEN DMC.5V COIL D D = IN INPUTS A GAIN RANGE B 5V 5 LS DECODER NC = NO CONNECT Figure. Three-Decade Gain Programmable Amplifier 5 Y Y Y 5 N BUFFER DRIVER µf LOGIC COMMON 5- Rev. G Page of 5

20 Data Sheet PROGRAMMABLE GAIN Figure shows the being used as a software programmable gain amplifier. Gain switching can be accomplished with mechanical switches such as DIP switches or reed relays. It should be noted that the on resistance of the switch in series with the internal gain resistor becomes part of the gain equation and has an effect on gain accuracy. The can also be connected for gain in the output stage. Figure shows an AD used as an active attenuator in the output amplifier s feedback loop. The active attenuation presents very low impedance to the feedback resistors, therefore minimizing the common-mode rejection ratio degradation. IN IN µf 5V (INPUT) ( INPUT) INPUT OFFSET NULL kω 5 PROTECTION PROTECTION kω kω kω pf AD kω 5 V SS kω kω kω V DD 5.kΩ Ω Ω GND V DD A A A WR AD5 5 Figure. Programmable Output Gain OFFSET NULL TO V R kω.kω.kω kω V OUT kω kω kω 5- INPUT ( INPUT) G = G = G = RG RG INPUT (INPUT) DATA INPUTS CS WR DAC A/DAC B PROTECTION.kΩ Ω Ω PROTECTION V b kω kω DAC A DB DB 5 AD5 DAC B 5 kω kω kω kω / AD 5: / AD Figure. Programmable Output Gain Using a DAC V OUT Another method for developing the switching scheme is to use a DAC. The AD5 dual DAC, which acts essentially as a pair of switched resistive attenuators having high analog linearity and symmetrical bipolar transmission, is ideal in this application. The multiplying DAC s advantage is that it can handle inputs of either polarity or zero without affecting the programmed gain. The circuit shown uses an AD5 to set the gain (DAC A) and to perform a fine adjustment (DAC B). AUTO-ZERO CIRCUITS In many applications, it is necessary to provide very accurate data in high gain configurations. At room temperature, the offset effects can be nulled by the use of offset trim potentiometers. Over the operating temperature range, however, offset nulling becomes a problem. The circuit of Figure 5 shows a CMOS DAC operating in bipolar mode and connected to the reference terminal to provide software controllable offset adjustments. 5- Rev. G Page of 5

21 Data Sheet DATA INPUTS CS WR kω AD5 MSB LSB INPUT RG G = G = G = RG INPUT VREF 5 AD5 GND C OUT OUT / AD R kω Figure 5. Software Controllable Offset R 5kΩ R kω R5 kω / AD 5 In many applications, complex software algorithms for autozero applications are not available. For those applications, Figure 5 provides a hardware solution. 5 RG RG AD.µF LOW LEAKAGE kω CH 5-5 V OUT 5Ω 5Ω V 5Ω 5Ω RG G = RG kω C Figure 5. Typical Bridge Application 5 -BIT ADC V TO V F.S. ERROR BUDGET ANALYSIS To illustrate how instrumentation amplifier specifications are applied, review a typical case where an is required to amplify the output of an unbalanced transducer. Figure 5 shows a differential transducer, unbalanced by Ω, supplying a mv to mv signal to an C. The output of the IA feeds a -bit ADC with a V to V input voltage range. The operating temperature range is 5 C to 5 C. Therefore, the largest change in temperature, ΔT, within the operating range is from ambient to 5 C (5 C 5 C = C). In many applications, differential linearity and resolution are of prime importance in cases where the absolute value of a variable is less important than changes in value. In these applications, only the irreducible errors (5 ppm =.%) are significant. Furthermore, if a system has an intelligent processor monitoring the analog-to-digital output, the addition of an autogain/auto-zero cycle removes all reducible errors and may eliminate the requirement for initial calibration. This also reduces errors to.%. 5-5 V DD V SS GND µs ZERO PULSE A A A A Figure 5. Auto-Zero Circuit AD5KD 5-5 Rev. G Page of 5

22 Data Sheet Table 5. Error Budget Analysis Error Source C Specifications Calculation Effect on Absolute Accuracy at TA = 5 C Effect on Absolute Accuracy at TA = 5 C Effect on Resolution Gain Error ±.5% ±.5% = 5 ppm 5 ppm 5 ppm Gain Instability 5 ppm (5 ppm/ C)( C) = 5 ppm 5 ppm Gain Nonlinearity ±.% ±.% = ppm ppm Input Offset Voltage ±5 µv, RTI ±5 µv/ mv = ±5 ppm 5 ppm 5 ppm Input Offset Voltage Drift ±.5 µv/ C (±.5 µv/ C)( C) = µv µv/ mv = 5 ppm 5 ppm Output Offset Voltage ±. mv ±. mv/ mv = ppm ppm ppm Output Offset Voltage Drift ±5 µv/ C (±5 µv/ C)( C)= 5 µv 5 ppm 5 µv/ mv = 5 ppm Bias Current-Source Imbalance Error Bias Current-Source Imbalance Drift Offset Current-Source Imbalance Error Offset Current-Source Imbalance Drift Offset Current-Source Resistance-Error Offset Current-Source Resistance-Drift ±5 na (±5 na)( Ω ) =.5 µv.5 µv/ mv = 5 ppm ± pa/ C (± pa/ C)( Ω )( C) =. µv. µv/ mv = ppm ± na (± na)( Ω ) = µv µv/ mv = 5 ppm ± pa/ C ( pa/ C)( Ω )( C) =. µv. µv/ mv = ppm ± na ( na)(5 Ω ) =.5 µv.5 µv/ mv =.5 ppm ± pa/ C ( pa/ C)(5 Ω )( C) = µv µv/ mv = 5 ppm Common Mode Rejection 5 V DC 5 db 5 db =. ppm 5 V =. µv. µv/ mv = ppm 5 ppm 5 ppm ppm 5 ppm 5 ppm ppm.5 ppm.5 ppm 5 ppm ppm ppm Noise, RTI (. Hz to Hz). µv p-p. µv p-p/ mv = 5 ppm 5 ppm Total Error 5.5 ppm 5.5 ppm 5 ppm Output offset voltage and output offset voltage drift are given as RTI figures. Rev. G Page of 5

23 Data Sheet Figure 5 shows a simple application in which the variation of the cold junction voltage of a Type J thermocouple-iron ± constantan is compensated for by a voltage developed in series by the temperature sensitive output current of an AD5 semiconductor temperature sensor. TYPE J K E T S, R R A NOMINAL VALUE 5.Ω.Ω.Ω.Ω 5.Ω MEASURING JUNCTION REFERENCE JUNCTION 5 C < T A < 5 C V A IRON V T CONSTANTAN TA AD5.5V.5V R A CU 5.Ω E O = V T V A 5.ΩI A.5V.5V 5.Ω R ~ = V T I A R T AD5 G = E O.kΩ kω NOMINAL VALUE 5Ω Figure 5. Cold Junction Compensation AMPLIFIER OR METER The circuit is calibrated by adjusting RT for proper output voltage with the measuring junction at a known reference temperature and the circuit near 5 C. If resistors with low temperature coefficients are used, compensation accuracy is to within ±.5 C, for temperatures between 5 C and 5 C. Other thermocouple types may be accommodated with the standard resistance values shown in Table 5. For other ranges 5-5 of ambient temperature, the equation in Figure 5 may be solved for the optimum values of RT and RA. The microprocessor controlled data acquisition system shown in Figure 5 includes both auto-zero and autogain capability. By dedicating two of the differential inputs, one to ground and one to the A/D reference, the proper program calibration cycles can eliminate both initial accuracy errors and accuracy errors over temperature. The auto-zero cycle, in this application, converts a number that appears to be ground and then writes that same number (-bit) to the AD5, which eliminates the zero error. Because its output has an inverted scale, the autogain cycle converts the A/D reference and compares it with full-scale. A multiplicative correction factor is then computed and applied to subsequent readings. REFERENCES The following reference materials provide additional information that supplements material found in the data sheet. A Designer s Guide to Instrumentation Amplifiers, RD Edition,. Analog Devices. Application Note, AN-, Synchronous System Measures μωs, Analog Devices. AD5 A, A, EN, A RG RG kω AD5 V IN AGND V REF kω V REF AD5A LATCH / AD kω / 5kΩ AD AD5 DECODE CONTROL MICRO- PROCESSOR ADDRESS BUS Figure 5. Microprocessor Controlled Data Acquisition System 5-5 Rev. G Page of 5

24 Data Sheet OUTLINE DIMENSIONS.5 (.) MIN. (.) MAX PIN. (5.) MAX. (5.).5 (.). (.5). (.). (.) MAX. (.). (5.5). (.5).5 (.).5 (.) MIN.. (.) SEATING (.5) PLANE. (.) BSC. (.). (.).5 (.). (.) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 55. -Lead Side-Brazed Ceramic Dual In-Line [SBDIP] (D-) Dimensions shown in inches and (millimeters).5 (.). (.) SQ. (.). (.). (.5). (.).5 (.) MAX SQ. (.).5 (.) SIDE VIEW.5 (.) REF.5 (.).5 (.). (.). (.) R TYP.5 (.) REF.55 (.).5 (.) BOTTOM VIEW. (5.) REF. (.5) REF.5 (.) BSC.5 (.) MIN. (.). (.5).5 (.) BSC 5 TYP PKG-5 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUI VALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 5. -Terminal Ceramic Leadless Chip Carrier [LCC] (E-) Dimensions shown in inches and (millimeters) -5--B.5 (.). (.). (.). (.).5 (.). (.). (.5) BSC.5 (.).5 (.5). (.). (.) COPLANARITY..5 (.) SEATING PLANE. (.). (.). (.).5 (.5).5 (.) 5. (.5). (.5) COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 5. -Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-) Dimensions shown in millimeters and (inches) -B Rev. G Page of 5

25 Data Sheet ORDERING GUIDE Model, Temperature Range Package Description Package Option AD C to 5 C -Lead SBDIP D- ADZ C to 5 C -Lead SBDIP D- AR- C to 5 C -Lead SOIC_W RW- ARZ- C to 5 C -Lead SOIC_W RW- ARZ--REEL C to 5 C -Lead SOIC_W, Tape and Reel RW- BD C to 5 C -Lead SBDIP D- BDZ C to 5 C -Lead SBDIP D- BE C to 5 C -Terminal LCC E- CD C to 5 C -Lead SBDIP D- CDZ C to 5 C -Lead SBDIP D- SD 55 C to 5 C -Lead SBDIP D- SD/B 55 C to 5 C -Lead SBDIP D- 5-5EA 55 C to 5 C -Lead SBDIP D- SE/B 55 C to 5 C -Terminal LCC E- SCHIPS 55 C to 5 C Die Z = RoHS Compliant Part. Refer to the official DESC drawing for tested specifications of the 5-5EA model. Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D5--/(G) Rev. G Page 5 of 5

26 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: CDZ BDZ AR- ARZ- ADZ AD SE/B BE ARZ--REEL AR--REEL BD 5-5EA SD SD/B CD