ST 65nm a Hardened ASIC Technology for Space Applications
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1 ST 65nm a Hardened ASIC Technology for Space Applications Laurent Hili ESA microelectronics section (TEC-EDM) Laurent.hili@esa.int Philippe Roche STMicroelectronics Philippe.roche@st.com Florence Malou CNES Florence.malou@cnes.fr ESCCON 2016
2 Agenda Motivation for DSM program ST C65SPACE radiation hardened ASIC technology ST C65SPACE qualification status / roadmap Conclusion
3 On board processors trend
4 European microprocessors roadmap ST C65SPACE 65nm ASIC technology Computing performances improvement x 10 times ATMEL ATC18RHA 180nm ASIC technology Source: Roland Weigand ESA Microelectronics section
5 On board memories trend Embedded memories (Gbits) Sentinel GAIA Rosetta Hubble
6 European FPGA roadmap ST C65SPACE 65nm ASIC technology Logic cells capacity improvement x 10 times ATMEL ATC18RHA 180nm ASIC technology Source: David Merodio ESA Microelectronics section
7 Digital telecom processors roadmap Bandwidth input / output port in MHz nm 65 nm Bandwidth per port improvement X 4 times 180 nm SMP 4 x 4 x 500 MHz scalable 128 x nm Spaceflex 48 x 48 x 500MHz Scalable 96 x x nm ALPHASAT 14 x 14 x 250 MHz Spaceflex5 20 x 20 x 250 MHz ST C65SPACE 65nm ASIC technology nm DTP 2G 650 nm 20 x 20 x 125MHz 180 nm Small GEO DTP 1G 8 x 8 x 40 MHz INMARSAT4 120 x 27MHz ATMEL ATC18RHA 180nm ASIC technology 4 x 4 x 36 MHz Courtesy: Airbus Defense Space (UK) Courtesy: Thales Alenia Space (France)
8 Agenda Motivation for DSM program ST C65SPACE radiation hardened ASIC technology ST C65SPACE qualification status / roadmap Conclusion
9 Hardened ASIC technology top level requirements Reach Space required functionalities 30 Mgates capacity Hardened standard-cells and memories Support for cold-spare IOs Hardened High speed link (HSSL) up to 6.25Gbit/s Hardened PLL Reliability Insure long term reliability during the 20 years operating time of the satellite Std-cell, RAMs, IOs, high speed link, very low FIT ( < 100ppm) over 20 years for temperature range from degrees (junction temperature / Tj) Radiation SEL free up to 60 MeV/mg/cm2 (in worst case conditions VDD / temperature) TID = 300krad (in worst case conditions VDD / temperature) Insure that all the offer (std-cells, IOs, memories, PLL, HSSL) is radiation robust Compliance with space qualification (ESCC) Wafer level Product level Process Assure stable performances along the C65SPACE manufacturing duration space process route frozen, specific process step, 10+ years supply guaranteed
10 Starting point ST65nm commercial process 65nm-LP CMOS from ST France : European technology, ITAR free 65nm CMOS commercially qualified in nm CMOS Bulk Process : Dual / Triple Gate Oxides Dual / Triple Threshold Voltages for MOS Transistors 7-9 Full Copper Dual Interconnect Levels Low K performances: 750 kgates/mm2 2GHz stdcells 5.7nW/(MHz x gates) GBit/s HSSL modules ST Rad Hard offer based on CMOS 65nm-LP commercial process Reliability and Radiation maximisation performed at design stages C65SPACE hardened process derived from ST65nm low power commercial process
11 C65SPACE offer Libraries allowing best design trade off between speed, area, power and radiation hardening SEL immune by layout techniques SEU performance adjusted according local design needs Hardness SEU hard C65SPACE flow adapted to specific radiation hardening needs Extended corner cases Extended design rule checks A full rad hard IP offer SEL free > 60MeV memory compilers SRAM, ROM ECC RTL wrappers, BIST Cold spare IOs Compatible with wire bond / flip chip CMOS 1.8v, 2.5v, 3.3v I2C LVDS 2.6Gbps High Speed Serial Link 6.25Gbps PLL 200MHz 1.2 GHz Robust flip-flops > 1GHz Robust combinatorial cells Clock gating, NAND2, IV Clock tree buffers Robust thermal sensors SEL free > 60MeV.cm2/mg SEU soft speed
12 C65SPACE offer Qualification domain No single event latch-up up to LET=60Mev/mg/cm2 at 125C and Vdd at 1.3V No significant parametric drifts up to TID = 300 kradsio2 SEU: ultra low fail rates by design and technology (SEU rate divided by 500) Extended reliability corners over 20 years at VDD max = 1.3V (nominal + 10%) Std-cell, RAMs, IOs degrees (Tj) High speed serial link degrees (Tj) Operational domain Mission profile: 20 years at Tj=110 degrees and VDD nom = 1.2V Features summary 7 copper metallization with 5 thin and 2 thick CoreLib Regular Flip-flop SEU /100 /500 Corelib (performance = speed + density + power) general purpose cells (high density / non SEU hardened) Standard speed grade cells Standard Voltage Threshold (SVT) High speed grade cells Low Voltage Threshold (LVT) Skyrob (performance = SEU / SET mitigation) 100+ hardened cells SVT optimised for leakage current 100+ hardened cells LVT optimised for speed Clocklib (performance = SET mitigation) 100+ hardened cells SVT 100+ hardened cells LVT SkyRob Rad-hard Flip-flop
13 C65SPACE radiation hardening flow Chip irradiation modelling Fault Injection SoC characterising simulating
14 C65SPACE hardened DFF characterisation SEU rate improvement factor with SKYROB ranging from 80 to 500 Cell type library Upset rate in GEO (SEU/bit/day) Improvement factor compared to standard commercial DFF description best worst Standard DFF from CORELIB with latchup protection (DNW) CORE65LPSVT (Standard Vt = Slow) 1.6E-7 (best) x x Reference DFF (commercial lib - CORELIB) Standard DFF from CORELIB with latchup protection (DNW) SKYROB65_LSDGUR FD12_DFPQX6 SKYROB_LSDGFD12 S_SDFPRQTX10 SKYROB_LSDGFD12 S_DFPQX18 CORE65LPLVT (Low Vt = fast) 4.1E-7 (worst) x x SKYROB65LPSVT (Standard Vt) 0.812E SKYROB65LPSVT (Standard Vt) 1.23E SKYROB65LPSVT (Standard Vt) 1.82 E Data computed with tool web based CREME96 GEO solar quiet Shielding 100mils Aluminium ions up to element Z=92 Weibull fit from experimental results at RADEF (December 2010) Reference DFF (commercial lib - CORELIB) Harden DFF with drive 6. D-type flip-flop with 1 phase positive edge triggered clock, Q output only Harden DFF with drive 10. Scanout D flip-flop with 1 phase positive edge clock, reset active low, Q and TQ outputs Harden DFF with drive 18. D-type flip-flop with 1 phase positive edge triggered clock, Q output only
15 C65SPACE hardened memories offer Speed Robustness Memory model Word Count Mux Range Voltage Range Supported Reliability Radiations Size Dual port high speed C65LP_ST_DPHS_SPACE 64-8K 8 1.1V V Large memory block Access (single/dual) Dual port high density C65LP_ST_DPHD_SPACE Single port register file C65LP_ST_SPREG_SPACE Small memory block 80-8K 4,8,16 1.1V V ,4,8 1.1V V Sustain 20 years, worst case operations Full immune with ECC against GEO harsh radiations Dual port register file C65LP_ST_DPREG_SPACE ,4,8 1.1V V Read only memory C65LP_ST_ROMHS_SPACE ,32,64 1.1V V Comprehensive Rad Hard SRAMs offer single or dual port memory optimised for density or speed
16 C65SPACE High Speed Serial Link 6.25Gbps HSSL IP datasheet BER Silicon measurement parallel loopback Rx to Tx After 6 days Ghz BER=1 e -15, CL=96% HSSL IP integration note
17 Agenda Motivation for DSM program ST C65SPACE radiation hardened ASIC technology ST C65SPACE qualification status / roadmap Conclusion
18 C65SPACE characterisations 4 different test vehicles families TC1 (rad hard digital library ): SKYROB65 ALLCELL blocks SKYROB65/CORE65 ROs FF shifters SKYROB65LP SRAM compilers Application digital blocks TC2 (rad hard analog library): high performance multiphase hardened PLL covering frequency range from 50MHz 1.2 GHz (6 phases) special IOs cold spare CMOS cold spare LVDS Signal I2C TC3 (rad hard high speed serial link): Quatuor / S7RADVAL quad high speed link 4 x 6.25 Gbps TC4 (C65 commercial library subset): Corelib 1000 general purpose cells
19 C65SPACE test vehicles development plan KIPSAT1 program (ESA) LIBEVAL (CNES) KIPSAT2.1 & 2.2 (ESA) TC1V1 TC1 TC1V2 Rad hard digital library Radiation performances reached TC1V3 ESCC evaluation TC1V4 Optimised digital offer TC2V1 TC2 Rad hard analog library TC2V1a ESCC evaluation TC2V2 Optimised analog offer TC3 TC3V1 Rad hard high speed link Radiation performances not reached: redesign needed TC3V1 TC3V2 Hardened HSSL IP TC3V4 TC4 Optimised HSSL offer Commercial library subset TC4V1 ESCC evaluation 12 test vehicles developed
20 C65SPACE ESCC Evaluation Plan Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 O c t N o vd e c J a nf e bm a r A p r M a y J u nj u l A u gs e po c t N o vd e c J a nf e bm a r A p r M a y J u nj u l A u gs e po c t N o vd e c J a nf e bm a r A p r M a y J u nj u l A u gs e po c t N o vd e c 65SPACE ESCC Evaluation Wire-bond Supply chain + Design houses: NGMP Cobham-Gaisler BRAVE/MEDIUM Nano Explore NGMP BRAVE/medium NGMP BRAVE/medium WB-CGA625 WB-QFP352 WB-CGA625 WB-QFP352 65SPACE ESCC Evaluation Flip-Chip CCGA Telecom ASIC FC-CGA1752 Supply chain + + Design houses: Telecom ASIC TAS BRAVE/LARGE Nano Explore Telecom ASIC FC-CGA1752 Samples ESCC Evaluation
21 Flip Chip package technology (E2V) Hermetic Seal Solder Columns PCB Flip Chip Under fill Solder Columns Chip & Wire Assembly Ceramic Package Heat sink Solder Balls Package Today s wire bond package solution Hermetic Package Ceramic Wire bonded single or staggered rows Soldered / Column mounted Emerging solutions Non hermetic PCB Flip Chip Solder Balls Solder Columns Heat sink / lid Walls Hermetic Package Hermetic PCB Flip Chip for Space applications High pin count package 1752 pins Pin pitch 1mm Column attach (6 Sigma) Signal integrity for high speed signals (HSSL 6.25 Gbps) Power integrity, better power grid distribution (lower voltage drop) Higher power dissipation 15 20W (dissipation from the backside of the die) Heat spreader attached on the backside of the active die Hermiticity capability
22 Application chips manufactured upon C65SPACE in 2015 Next Flight models in 2016 VT65 Telecom ASIC CNES funding 200mm Flip Chip -CGA Package (courtesy: TAS / ST / ATMEL / CNES) Next Generation Microprocessor NGMP ESA funding Quad Leon4 architecture 250MHz 70mm2 Wire bond package CGA625 (courtesy: Cobham-Gaisler / ST)
23 Agenda Motivation for DSM program ST C65SPACE radiation hardened ASIC technology ST C65SPACE qualification status / roadmap Conclusion
24 Conclusions ST 65nm hardening activities are close to completion 3000 pages data book compiling datasheets + radiation reports (HI + Protons + Gamma) ST C65SPACE flow has been deployed to Alpha users in 2015 Two applications test vehicles have been produced and functionally validated in 2015 NGMP next generation microprocessor developed by Cobham/Gaisler (ESA funding) VT65 telecom processor developed by TAS-F (TAS / CNES / ST/ ATMEL funding) A flight version of the telecom ASIC is currently under development (TAS / CNES / ST/ ATMEL funding) and will be manufactured in The circuit will exhibits a complexity of ~ half Billion transistors Radiation validation of HSSL IP version4 planned for Q Circuit has been taped out in December 2015
25 Conclusions Perspectives beyond 65nm Future developments will benefit from the lessons learned on ST C65SPACE program. C65SPACE has paved the way for future developments with ST. ST Fully Depleted SOI technologies 28nm / 14nm are promising nodes with respect to radiation hardening Better starting point with respect to latchup hardening Self heating might be an issue to tackle with care Cost might be a limiting element for the development and qualification of a general purpose ASIC technology beyond 65nm node. Economic considerations will instead push for the design and qualification of standard products (micro processor or FPGA). Still need to work very closely with technology supplier (ST) to get access to full reliability data based on mass volume production. Necessity to tackle reliability not only at technology level but also at architecture level with concepts such as FPGA, Network on Chip or GPU (many cores).
26 Acknowledgements CNES ST Florence Malou Caroline Amiot Bazile Francis Pressecq Kevin Sanchez Laurent Dugoujon Thierry Scholastique Remy Chevallier Yves Gilot Giles Gasiot Jean Christophe Mas Vincent Huard Philippe Magarshack
27 Thanks
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