Advanced Technology Programs Group Radiation Hardened Microelectronics Branch Program: Overview and Status L.M. Cohn NRO/AS&T

Transcription

1 UNCLASSIFIED Advanced Technology Programs Group Radiation Hardened Microelectronics Branch Program: Overview and Status L.M. Cohn NRO/AS&T Presented at the Aerospace Corporation Microelectronics Reliability and Qualification Workshop January 27-28, 2015 SUPRA ET ULTRA UNCLASSIFIED

2 Agenda Radiation Hardened Microelectronics Branch Mission Objectives Radiation Hardened Microelectronics Branch Near Term Program Mid Term Program Overview & Motivation RHBD 45nm ASIC Task Onboard Processing & Control Technology Task Analog & Mixed Signal Technology Task Radiation Testing & Characterization Trusted FPGA Far Term Program Nano-scale Microelectronics Investigation CNT Technology Advanced Power Converter Technology Development Summary 2

3 RHM Branch Mission, Objectives & Applications Mission: Develop both evolutionary and revolutionary microelectronics technologies to enhance satellite electronic systems capabilities Objectives: Onboard Processing (OBP) Enhancements: Provide flexible, heterogeneous capability to efficiently support full range of OBP requirements (MIPS to TIPS) & TB storage at reduced SWaP Provide high performance analog/mixed-signal technologies to support communications and signal processing applications Front End & Electronically Steerable Array (ESA) Enablement: Very high SFDR low power CNT FET technology for LNA, mixer and ADCs Ultra Deep Submicron Microelectronics technology for elemental digital beam-forming Applications: System survivability; Trusted, radiation hardened & high reliability Pre-planned program upgrades by providing improvements in performance, reliability & SWaP New mission capabilities 3

4 Objective: Productization & Qualification of RH Electronics Technologies (250nm to 150nm) 10X improvement in OB processing performance Tasks: RH15F Process Class V Qualification L2 Cache MCM/Synchronous SRAM Qualification 4Mb CRAM Qualification RH18/RAD MHz/400MIPS Processor Qualification 100 MHz Bridge ASSP Development RAD750/250MHz 500 MIPS processor Structured Array Development Optimized SERDES Development Advanced Packaging Development HX-5000 SEE Characterization Near Term Technology Program Completed RHBD 90nm Reliability Demonstration 4

5 Near Term Program Status: Completed Balanced design to support > 400 MIPS Throughput Satellite Front-End & Processing System L2 CACHE Memory Class Q Qualification Completed RAD MHz/400MIPS Class Q Qual Complete 250MHz/500 MIPS In development RH 16Mb (X32) SRAM Class Q Qual 4QCY12 X SERDES Test Chip BAE SYSTEMS 100MHz Bridge Chip Class Q Qual 4QCY12 RH SERDES Pass 2 Completed Class Q Qual 4QCY12 RH 4Mb NVRAM Class Q & V Quall Completed RH15 Class V Qual Complete RH15F Class V Qual Completed Structured Array Complete FPGA Replacement 5Gbps SERDES Design Complete Demo 2QCY13 5

6 Mid-Term RHM Technology Program Objective: Demonstration of technology to provide a heterogeneous, flexible OBP architecture to support full range of processing needs (MIPS to TIPS) Adaptation of Commercial Processes & IP for Space Applications >1000X in OB processing performance; > TFLOP OBP performance Demonstration of high performance AMS technology GSPS wide-band ADC/DAC Technology Development Areas: RHBD 45nm ASIC Design, Demonstration and Qualification RHBD Processor Development & Demonstration RHBD 90nm & 45nm GFLOP DSP Development RHBD 45nm Next Generation multi-core GPP Family (RAD55XX) RHBD SBC Next Generation GPP RH DDRX Radiation Effects Mitigation Assembly RHBD Next Generation Analog/Mixed-Signal Technology Development RHBD 45nm ASIC Switch Technology Development Enhanced SERDES Demonstration RHBD High Dynamic Range ADC Technology Development RHBD Next Generation FPGA Investigation 6

7 Mid-Term RHM Program Tasks 7

8 Integrated RHBD 45nm Development Strategy Commercial IP adopted for space applications and fabricated at a Trusted Foundry * * Fabricated at the Trusted IBM EFK facility 8

9 RHBD 45nm ASIC Development, Demonstration & Qualification Program Program Objectives Development, demonstration, and Class Q/V qualification of a RHBD 45nm ASIC technology. Program Tasks Radiation & Reliability Technology Assessment & Characterization Reliability assessment and remediation RHBD library development & demonstration Radiation effects modeling and simulation RHBD ASIC Design and Demonstration Design, fabrication and test of two ASICs Package development and demonstration ASIC & Technology Qualification QML Class V qualification QML Class Q ASIC qualification Design flow qualification 9

10 RHBD 45nm Technology Program Roadmap 10

11 RHBD 45nm Technology Goals and Requirements 11

12 RHBD 45nm Library Radiation Hardening and Reliability Enhancements Reliability enhancements Selective metal width modifications for electro-migration Lower Vdd (0.95 volts nominal) to limit NBTI/GOI. Enhanced design methodology (e.g., power aware placement) to reduce hot spots Power gridding segmentation to control thermal profile and power distribution Identification and avoidance of circuit topologies that may impact reliability Package/image co-design Radiation hardness enhancements RH bit cells with RAM trench capacitors Critical nodal spacing and interleaving Selective dual path logic on critical control circuits RH latches at RAM input/output Transistor sizing and other SET mitigation approaches for critical circuits Hardened registers and clock power level cells for control and critical signals Low power enhancements Additional high Vt (XVT) device/library for lower leakage Clock gating library cells and low power registers The RH45 library has been enhanced to support QML space qualification requirements 12

13 RHBD 45nm Library Overview 13

14 Library Content RH45 ASIC Library and PDK Summary Combinational Cells full family of Boolean and data path cells Clock Cells specially designed re-drive and gating functions for radiation hardness and glitch free operation Sequential Cells registers and latches; scan and SET filtering options Embedded RAMs - dual port and single port compilers; efuse for repair; low power/high performance options PLLs- programmable; low power/low jitter SERDES 8 lane macro; up to 5Gbs; multiple protocol support; power down and unidirectional features I/Os programmable LVCMOS, LVDS, SSTL(DDR2/3) Support Cells filler, antennae, ESD, delay cells, etc ASIC Product Design Kit (PDK) Accessible via BAE Systems Sharepoint Content: Four corner characterized models Black box timing/synthesis models for SRAM, IO, PLL, SERDES Verilog simulation models Floor plan and image/cover models Run Scripts and setup files for design tools and methodology flow Documentation (electrical specification, user guides) 14

15 Reliability Technology Characterization Vehicle 15

16 Technology Reliability Testing Summary (1/2) 16

17 Technology Reliability Testing Summary (2/2) 17

18 RHBD 45nm SRAM (ASIC) to Support QML V Testing and Qualification 18

19 QML Class V Qualification Test Flow 19

20 QML Class V Accelerated Life Test Results 20

21 ASIC Qualification Devices 24M eq. gates 15M eq. gates 21

22 ASIC-1Functionality Testing Status Testing Report cared: All Green! Fully Functional First Pass ASIC-1 Design Achieved The status: Electrical testing successfully completed over temperature & voltage Average yield of first 21 wafers > 40%. Flight units delivered. MIL-PRF Groups A-E testing initiated with QML qualification test completed Chip under test 22

23 ASIC-1 QML Qualification Status: Testing Completed 23

24 ASIC-1Total Ionizing Dose Radiation Test Results* * 22 parts tested IAW MIL-T-1019 to include rebound Result: RHACL= 500krd 24

25 ASIC-1 Single Event Effects Test Results 25

26 ASIC-1 Single Event Effects Test Results 26

27 Library Test Vehicle (LTV) Purpose: Comprehensive test vehicle for elemental evaluation and validation of ASIC library and custom blocks of the RAD5545 Contents: Entire Standard Cell library - every cell in the RH45 library exists as standalone test structure for functionality I/O (LVCMOS and LVDS) - test structure to test functionality and characterize Compiled and Custom RAMs - RAMs selected to cover each bit cell type and the extreme array dimensions (tallest/shortest, widest/narrowest, largest bank/smallest bank) efuse - efuse controller with BISR (built-in-self-repair) registers and RAM blocks to test full self-repair function Platform PLL - functional and SEE testing DFF chains various chains of 400 stages to ensure large enough cross-section for SEU/SET testing. Chain of each DFF function (set, reset, set/reset) for various power levels and Vts. ASIC SER test structure - synchronous logic representative of an ASIC to test SER vs. frequency Ring oscillators rings of different logic gates (eg: inv, nand, nor, and aoi) for each Vt to measure hardware to model correlation Miscellaneous - thermal sensor RAMs 8 single ports 8 dual ports 4 customs Entire Library ASIC SER experiment 165 DFF chains efuse LTV Physical Design View 15 ring oscillators Status Electrical performance & functionality verified SEE laser testing performed on selected circuits Initial SEE heavy Ion radiation test completed on 6/20/14. PLL 27

28 LTV Single Event Effects Test Results 28

29 Package Development - Completed Ceramic Column Grid Array (CCGA) package 35mm; 1144 pin; flip chip die attachment Leverages qualified CCGA design (GoldenGate Bridge ASIC) and >10 years CCGA and >30 years flip-chip production Modified substrate routing for Qualification ASICs - specific signal integrity considerations 360 pin 624 pin 1144 pin 25 mm 32mm 35 mm Ceramic Column Grid Array (CCGA) Samples Substrate Design Package vendor is NTK Development guidelines, routing rules, and other constraints levied by both ASIC subcontractors and BAE Systems Electrical Analysis Impedance for signals, loop LCRs for signal, S-parameters for select signals i.e., signals of interest such as ADC or SERDES inputs, longest and shortest paths Power plane impedance and IR drop for respective planes 144 Ceramic Column Grid Array Package Drawing and Layer Stack ASIC 1/ 2/LTV package has been released to manufacture. 29

30 RHBD 90nm/45nm Onboard Processing & Control Technology Development & Demonstration Program Program Objectives Design, development, demonstration and verification of a RH, flexible and heterogeneous architecture onboard processing capability to meet the full range of satellite payload processing and control function needs (MIPS to TIPS) Technical Approach Combines advanced commercial DSP & GPP IP with RHBD 45nm technology to achieve program objectives Develop and demonstrate: GFLOP DSP (90nm mid term& 45nm far term) Host Bridge to support TFLOP SBC capability GPP (RAD55XX) family and SBC RH REM DIMM Module 30

31 RHBD 90nm RADSPEED Single Instruction Multiple Data (SIMD) Digital Signal Processor The RADSPEED DSP is a radiation hardened variant of the CSX700 digital signal processor (DSP) from ClearSpeed Technology RADSPEED DSP 90nm 160 ( spare) processing elements (PE) in two multi-threaded array processors (MTAP) Throughput: W power Each PE incorporates double precision floating point hardware as well as integer processing Single instruction, multiple data (SIMD) architecture Dual ClearConnect bridges (CCBR) Each with ~ 30 Gb/s throughput Supports direct connection between DSPs or to a backplane using a bridge Dual DDR2 DRAM interfaces A DDR2 interface is dedicated to each MTAP, avoiding bottlenecks Throughput: ~30 Gb/s each Supported by mature commercial software development kit Software prototyping hardware available now The RADSPEED DSP has successfully completed electrical & functionality characterization, and radiation testing. Transition to RHBD 45nm TBD 31

32 Software Development Environment Software Development platform is available for customers to start RADSPEED DSP algorithm development Open-VPN to workstation (allows external customer access) User s guide for configuration of ClearSpeed processors to mimic RADSPEED DSPs Hardware platform contains: 2 ClearSpeed e710 cards in Dell workstation Each contains a CSX700 processor and local memory Cn compiler ClearSpeed multicore compiler SDK including MATLAB libraries Graphical profiler Graphical debugger Two organizations have used the development environment RADSPEED DSP SDK was developed for use on Phase B2 and beyond: Optimized version of Cn compiler/sdk for RADSPEED DSP configuration 32

33 RHBD Host Bridge & RAD55XX Family Embedded 4-core e5500 processor Custom I/O For GFLOP Single Core w/o High Speed Transfer Host Bridge srio Manager 20-Lanes SERDES Real Time DeBug Off-the-Shelf Space qualified solutions for processing & control applications Prototype Demonstration 2Q

34 RAD5545 System-on-Chip Multi-core Processor Status: Design > 95% Complete Fabrication scheduled for 2QCY15 34

35 RAD55XX Software Support 35

36 RAD55XX Prototyping & Software Development Support 36

37 RHBD Analog and Mixed-Signal Technology Development & Demonstration Program Program Objectives Design, development, and demonstration RH analog and mixed-signal technologies to support onboard data transfer, signal conditioning and conversing applications. Technical Approach Adoption of advanced commercial network switching and analog-to digital/digital- to- analog (ADC/DAC) for space applications. Development and demonstration tasks: RHBD Packet and Cross-Point Switch demonstration End-Point ASIC Demonstration High Dynamic Range (interleaved) ADC Development Enhanced SERDES Demonstration 37

38 RHBD 45nm Switch/Interface Development Efforts Packet Switch Common Processor Flexible Interface or End- Point Switch Protocol Independent or Cross-Point Switch Packet Switch Demonstrations 2Q

39 High Dynamic Range (HDR) ADC Technology Development RHBD 32nm HDR ADC inter-leaved design approach advances the stateof-the-art RHBD 32nm technology required to achieve instantaneous bandwidth; jitter control and insertion of adaptive calibration circuits 39

40 RHBD 45nm Enhanced SERDES Demonstration Initial program goals 40

41 RHM Branch Technology Development Support Efforts NASA & NRL Radiation Effects Testing & Characterization SEE Laser NRL Conventional radiation effects testing Cyclotron Heavy Ion Texas A&M NRL Laser Test Facility 41

42 Objective: Demonstration of Revolutionary and State of-the-art Evolutionary technologies to provide a paradigm shift in on-board processing. Demonstration of: CNT high Spurious Dynamic Range (SFDR) with very low power Mixers and Low Noise Amplifiers (LNA) CNT Non-volatile Memory RHBD 14nm ASIC technology Technology Development Areas: High SFDR Mixers & LNAs using CNT Linear field Effect Transistor Development CNT Memory Technology Development < RHBD 14nm CMOS Technology Development Radiation Effects Reliability Characterization Far-Term Technology Program Radiation & Reliability Effects Modeling and Simulation RHBD ASIC Library Development and Demonstration 3-D Packaging 42

43 CNT Technology Program 43

44 Program Objectives: RHM Branch Nano-scale ( < 32nm) Technology Development Efforts Investigate < 32nm* technologies for potential DoD/IC space & other system applications (e.g., SWaP-C, radiation, reliability, cost, Trust) Develop & demonstrate RHBD & reliability mitigation approaches Develop & demonstrate an ASIC library & design flow Identify & adopt selected commercial IP Productization & qualification * Initial efforts focused on 14nm with anticipated transfer to ~ 7nm as it becomes available Initial Program Tasks: VU: Investigate & characterize radiation effects and develop mitigation approaches for ~14nm technology BAE: Investigate and characterize reliability degradation modes in ~14nm technologies Boeing: Investigate and characterize combined radiation & reliability degradation modes in ~14nm technologies Program Schedule: T&E TCV/ SEC Library Demo ASIC Demo P&Q FY14 FY15 FY16 FY17 FY18 FY19 FY20 44

45 Advanced Point-of-Load Converter Technology Advanced POL technology needed to support insertion of scaled electronics Poor < 1v Large footprint Does not support MIL temperature range, susceptible to radiation effects Several ongoing efforts to provide POL technology for various applications with focus on digital control 45

46 Summary The ATPG RHM Program is supporting the development of both evolutionary and revolutionary technologies to enhance DoD and IC satellite system performance & reduce SWaP. Near Term Program: Completed P&Q efforts for a variety of 250nm to 150nm devices and technologies to enhance OBP; e.g., > 10X increase in performance compared to current capabilities (RAD6000) Mid-Term Program: Exploitation of < 45 nm technology to address the full range of OBP applications from MIPS to TIPS and wide band very high performance ADC/DAC applications to include: RHBD 45nm ASIC design, demonstration and qualification Analog/Mixed-Signal technology: High speed data switch family Gsps performance the 32nm technology node General Purpose Processor and Digital Signal Processor design and demonstrations with from > 10X to 1000X increased performance compared to RAD750 processor. Far-term Program: Next Generation microelectronics; e.g., RHBD 14nm technology Novel approaches (e.g., near threshold operation) to achieve significant SwaP savings 3D/2.5 D packaging Developing CNT technology for mixed signal and linear circuit applications Additionally, advanced Digital Point-of-Load converter technology is in development Applications for these technologies have been identified by a number of flight and technology development programs 46

47 Contact Information Lew Cohn (O) Mil 47