NGMP GR740. Status and Roadmap Vision for Future. Roland Weigand European Space Agency. Microelectronics Section
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1 NGMP GR740 Status and Roadmap Vision for Future Roland Weigand European Space Agency Microelectronics Section Microelectronics Section ESA UNCLASSIFIED For Official Use (1) 06. Nov. 2014
2 History of ESA Microprocessor Developments MA (Dynex Semiconductor) MIL-STD-1750A architecture GEC-Plessey 1.5 μm SPARC V7 ERC32 chipset 3-chips: IU, FPU, MEC Temic 0.8 μm SPARC V7 ERC32 single chip Temic 0.5 μm SPARC V8 LEON2/AT697 Atmel 0.18 μm SPARC V8 LEON4/NGMP Goal: 10x AT697 performance Performance (arbitrary units, normalised to MA31750) Computing Performance of ESA Standard Microprocessors Microelectronics Section ESA UNCLASSIFIED For Official Use (2) 06. Nov
3 NGMP Development Roadmap Start 2009: VHDL / PDR done (2010), commercial prototypes (2013) On-hold for 3 years waiting for access to technology Development resumed in 2014, product code is now GR740 ST C65SPACE technology design kit provided in April 2014 Technology mapping (memory and hard-ip integration) done Layout in progress, directly by ST no Atmel involvement Architectural refinements (L2 cache) and bugfixes in progress Baseline package: CLGA 625, cavity development in progress Tape-out planned in Q1/2015 EM / board availability: Q4/2015 Validation 2015 (funding approved) Qualification 2016 (funding permitted) Goal: use existing (EM) silicon dies Microelectronics Section ESA UNCLASSIFIED For Official Use (3) 06. Nov. 2014
4 GR740 Specification Adapted specification taking into account technology constraints and capabilities No DDR2 (requires PHY), only SDRAM No SERDES (requires flip-chip package) Increased L2 cache size 2 Mbyte Improved performance counters to ease execution time analysis L2 cache controller split support to reduce inter-core interference (TBC) Frequency goal 300 MHz (TBC) 250 is currently more realistic 4x250 = 10x100 = 10xAT697 = GINA L2 cache memories L2 cache memories CPU CPU CPU CPU L2 cache memories Pin multiplexing: PROM with UART, CAN, 1553 and SPW debug ports Half of SDRAM port multiplexed with PCI and one of 2 Ethernet ports Interfaces PLL Interfaces Chip area ~ 8.4 x 8.7 = 73 mm² Microelectronics Section ESA UNCLASSIFIED For Official Use (4) 06. Nov. 2014
5 NGMP Benchmarking Benchmarks run at the same frequency (50 MHz) for all devices increase in max clock frequency to be considered SCOC3, AT7913 have similar performance as AT697 improved cycles per instruction (CPI) good scaling on multithreaded benchmarks (4 cores) almost x4 Microelectronics Section ESA UNCLASSIFIED For Official Use (5) 06. Nov. 2014
6 FPMP Field Programmable MicroProcessor (a vision) FPGA and Microprocessor are 'high-volume' products for space Microprocessor and FPGA often complement each other Commercial FPGA offer SOC-FPGA with hard microprocessors ==> FPMP1 = space microprocessor with embedded FPGA? ==> FPMP2 = space FPGA with embedded microprocessor? BRAVE (EM) nm GR740 (EM) BRAVE (FM) GR740 (FM) FPMP (65 or 28 nm?) Microelectronics Section ESA UNCLASSIFIED For Official Use (6) 06. Nov. 2014
7 FPMP1: high end CPU + efpga for IO and co-processing serdes serdes serdes serdes Microelectronics Section ESA UNCLASSIFIED For Official Use (7) 06. Nov. 2014
8 FPMP2: large FPGA for DSP with light control CPU On-chip RAM no external memory serdes serdes serdes serdes serdes serdes serdes serdes Microelectronics Section ESA UNCLASSIFIED For Official Use (8) 06. Nov. 2014
9 For more information and documentation please refer to the following site: Microelectronics Section ESA UNCLASSIFIED For Official Use (9) 06. Nov. 2014
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