Wideband Down-Conversion and Channelisation Techniques for FPGA. Eddy Fry RF Engines Ltd

Transcription

1 Wideband Down-Conversion and Channelisation Techniques for FPGA Eddy Fry RF Engines Ltd 1 st RadioNet Engineering Forum Meeting: Workshop on Digital Backends 6 th September 2004

2 Who are RF Engines? Signal processing IP core supplier for FPGA SoPC designer of complex optimised front end subsystems for FPGA Signal processing subsystem consultant and supplier, FPGA + DSP

3 FPGAs vs DSPs

4 DSP Devices Advantages: Moderate performance Easy design methodologies Cheap and easily available Highly flexible Disadvantages Moderate performance

5 FPGA Devices Advantages: High performance Re-programmable Disadvantages Design methodologies seen as difficult Unit cost can be high Limited internal memory

6 When is an FPGA appropriate? Very high sustained processing rates Digitisation rates >100MHz to > 1GHz are common Real time processing no gaps in data Repetitive algorithms such as Down-Conversion and Channelisation are particularly suited

7 Reducing FPGA Disadvantages Design methodologies improving Availability of high performance IP High-level design entry (System Generator for DSP etc) Availability of COTS platforms improving Acqiris, Pentek, Spectrum Signal Processing, Nallatech etc Overall system cost lower than RF / DSP-based High bandwidth external memory support

8 FPGA Device Example Manufacturer: Xilinx Device: XC2VP100 No of Logic Cells: No of 18-bit x 18-bit Multipliers: 444 No of 18Kbit RAMs: 444 Assuming a 180MHz clock rate, maximum theoretical sustained performance is: 496e9 36-bit additions / second 80e9 18-bit x 18-bit Multiplications per second 360 GByte/s Memory bandwidth, but only ~1MByte storage Other manufacturers: Altera, Actel, Lattice etc

9 External Memory Support High bandwidth SRAM (QDR, ZBT etc) 10 s MBytes storage Few GBytes / s bandwidth Random addressing High bandwidth SDRAM (DDR etc) Few GBytes storage ~1 GBytes / s bandwidth for block addressing << GBytes / s bandwidth for random addressing

10 Down-Converter and Channeliser Types

11 Digital Down-Converter (DDC) Real to complex conversion (full Nyquist) Narrow-band channel extraction Fixed Multi-Channel Down-Converter (Channeliser) FFT Polyphase DFT PFT Re-configurable Multi-Channel Down-Converter Tuneable PFT

12 Real to Complex DDC Examples RFEL s Distributed Half-Band Filter (DHBF)

13 FFTs

14 RFEL s Vectis Pipelined FFTs

15 Vectis HiSpeed Architecture n x radix-2 FFT stages FFT Length = 2n Normally ordered Output Samples 0, 1, 2, 3 Interleaved I and Q Input Buffer (optional) Stage n Stage 2 Stage 1 Bit Reverser (optional) Interleaved I and Q Normally Ordered Inputs Samples 0,1, 2, 3, 4, 5, 6, 7, 8, 9,10.. Bit Reversed Output Samples 0, 8, 4, 12, 2, 10, 6, 14. (Sequence From 16-point FFT shown)

16 Vectis QuadSpeed Architecture 1:2 De-multiplexed I and Q inputs n x radix-2 FFT stages FFT Length = 2n Normally ordered Output Samples 0, 1, 2, 3 Ieven Qeven Iodd Qodd Input Buffer (optional) Stage n Stage 2 Stage 1 Bit Reverser (optional) Normally Ordered Inputs Samples 0,1, 2, 3, 4, 5, 6, 7, 8, 9,10.. Bit Reversed Output Samples 0, 8, 4, 12, 2, 10, 6, 14. (Sequence From 16-point FFT shown)

17 HyperSpeed Architecture FFT Length = N x M Complex Fs Fs / M 0,M,2M (N-1)M N-Point Matrix Serial DFT 0,1,2,3 NM-1 1:M Demux 1,M+1,2M+1 (N-1)M+1 N-Point Matrix Serial DFT M-1 Complex Multipliers M-Point Parallel DFT M-1, 2M-1, 3M-1, NM-1 N-Point Matrix Serial DFT Twiddle-Factors

18 HyperLength Architecture FFT Length = N x M Re-order (External RAM) Re-order (External RAM) Re-order (External RAM) Interleaved I and Q N-Point HiSpeed FFT Twiddle Factors M-Point HiSpeed FFT Interleaved I and Q FPGA Normally Ordered Inputs Samples 0,1, 2, 3, 4, 5, 6, 7, 8, 9,10.. Normally ordered Output Samples 0, 1, 2, 3

19 FFT Examples

20 Polyphase DFT and PFT Filter Banks

21 Polyphase Filter Vs Weighted FFT 20 Unweighted FFT Filter Response dbc Polyphase DFT Filter Response Kaiser Weighted FFT Filter Response E E E E E E E+07 Offset (Hz)

22 Kaiser Window 0 32-Point FFT Filter Bank Channel Spacing = F s / db Fs/2 Frequency 0 +Fs/2

23 0 32-Point Polyphase Filter Bank Typical Performance Channel Spacing = F s / db Superior Cut-Off & Stop-Band Performance Fs/2 Frequency 0 +Fs/2

24 Polyphase DFT Architecture Rate = F s Delay 1 K samples Delay 2 K samples Delay N-1 K samples Coeffs W 0, W 1, W 2.. W K-1 Coeffs W K, W K+1,.. W 2K-1 Coeffs W 2K, W 2K+1.. W 3K-1 + Coeffs W (N-1)K, W (N-1)K+1.. W NK-1 N*K Window Coeffs W NK-1 thro W 0 I Q K Point Complex FFT Rate = F s I Q Duplicate Q Channel

25 Polyphase DFT Examples

26 PFT Architecture 2 Points 4 Points 8 Points Aux O/P Aux O/P Aux O/P N Points Simultaneous outputs of PFT s with different number of bins / frequency resolutions For example: a 256-point PFT with 400 khz bin width at same time as a 16K-point PFT with 6.25 khz bin width Useful for discriminating in both frequency and time domains

27 Tuneable PFT Example

28 Wideband Spectrometer Example Pair of 8-bit ADCs are accurately clocked at 1GHz, 180 o apart to give 2GHz effective sample rate Total Resource Requirements: 308 Multipliers 306 RAMs ~95% of XC2VP70 1GHz Nyquist bandwidth, 800MHz usable bandwidth, centred on an IF of 500MHz ADC#1 ADC#2 Wideband DDC (DHBF) Window 32K-point HyperSpeed FFT Fixedpoint Complex to Floatingpoint Power Accumulate Floatingpoint Power PCI Programmable window applied Convert Programmable fixed-point complex floating-point to Each ADC s data is de-multiplexed DHBF converts into 2GHz 8 to x complex 8-bit real data 32K-point data. into complex 32-bit FFT power floating-point accumulator FPGA power (average) busses at 125MHz for 1GHz interfacing complex to 16 FPGA base-band Multipliers, (FFT data 0 RAMs HyperSpeed Example) Averaging 32 Multipliers from 1 to 1K frames (DDC Example #3) 30.52kHz channel spacing 64 RAMs

29 Questions?