Software Radio Satellite Terminal: an experimental test-bed

Transcription

1 Software Radio Satellite Terminal: an experimental test-bed TD S L. Bertini,, E. Del Re, L. S. Ronga

2 Software Radio Concept Present Implementations RF SECTION IF SECTION BASEBAND SECTION out RF CONVERSION DOWN CONVERSION IF PROCESSING A/D BASEBAND PROCESSING ENGINE D/A I/O Software Defined SOFTWARE CONTROL MAN-MACHINE INTERFACE Cost 272-6th MCM - Napoli Nov. 3rd-4th

3 Software Radio Concept Future Implementations Software Defined RF SECTION IF and BASEBAND SECTION out LOW NOISE AMPLIFIER & ANTI- ALIASING FILTER A/D WIDEBAND RF FRONT END PROCESSING ENGINE BASEBAND PROCESSING ENGINE D/A I/O SOFTWARE CONTROL MAN-MACHINE INTERFACE Cost 272-6th MCM - Napoli Nov. 3rd-4th

4 System Architecture Phase I Configuration Manager propagates PHY definitions SR Terminals perform PHY reconfiguration Phase II Traffic channels setup Communication Cost 272-6th MCM - Napoli Nov. 3rd-4th

5 Reconfiguration Process Blind Signal Analysis Is a known communication standard? (No) Acquire PHY definitions Use internal libraries when possible Download unknown functions PHY Reconfiguration Communication Phase Cost 272-6th MCM - Napoli Nov. 3rd-4th

6 Software Architecture I Cost 272-6th MCM - Napoli Nov. 3rd-4th

7 Software Architecture II (RADL Compilation Process) config.rdl Config. File radl.out Radio Access Definition Language Compiler.lib Lib1 Lib2 Lib3 Lib4 Lib5 Microcode Reconfig. Hardware Cost 272-6th MCM - Napoli Nov. 3rd-4th

8 RADL Structure The complete communication standard implemented in the SR terminal is described, in the configuration file, as a single block (in( red) ) with a set of inputs and outputs. This top-level block is composed by other blocks (in( green) ) interconnected to create the specific system to be developed. The setup file is composed by three sections: Parameter Definitions Link Statements Run Sequence In1 1st Parameter Set 2 Parameter Set 3 Block C 5th Out 1 Block A 3rd Block E Block B 4th In N Parameter Set 1 2nd Block D Parameter Set 5 Parameter Set 4 Out N Cost 272-6th MCM - Napoli Nov. 3rd-4th

9 HW Architecture of SR Terminal Cost 272-6th MCM - Napoli Nov. 3rd-4th

10 SR TestBed TX Tiger Sharc ADSP-TS101 DAC RF Front-End To C/Ka/Ku Upconverter (L-Band) Agilent ESA E-4402 Spectrum Analyzer From C/Ka/Ku Upconverter (L-Band) RF Front-End ADC Tiger Sharc ADSP-TS101 RX Cost 272-6th MCM - Napoli Nov. 3rd-4th

11 Analog Devices Tiger Sharc DSP programmable clock speed (166/300 MHz); on chip memory of 6M Bit; 32/40 bit floating point; 8/16/32/64 fixed point processing; 14.4G bytes per second of internal memory bandwidth; 14 DMA channel; up to eight DSPs on a common bus; 4 Link Port: 125MHz x 2 (DDR)= 250Mbyte/sec EZ-KIT Lite Evaluation Board 2 Tiger Sharc (@300MHz) 32MB RAM (up to 128MB) 544K Flash Memory 2 Link Port (2 DSPA, 2 DSPB) Cost 272-6th MCM - Napoli Nov. 3rd-4th

12 TX Chain Comblock COM-2001 (TX-DAC 9760) Comblock COM-4001 (RF Front-end) Dual 10bit DAC, 40 Msamples/s, 6-pole Butterworth rejection filter Dual-Band MHz or GHz Cost 272-6th MCM - Napoli Nov. 3rd-4th

13 RX Chain Comblock COM-3001 Dual Band ( MHz or GHz) Built-In AGC with 70 db dynamic range Dual 10bit 40 Ms/s Cost 272-6th MCM - Napoli Nov. 3rd-4th

14 Multi-processing Capability The ADSP-TS101S offers powerful features tailored to multi-processing DSP system through the external port and link port.. The multi-processing capability provides highest bandwidth for the interprocessor communication, including: Vector Interrupt: vector interrupts are used for interprocess communication Bus Lock and between DSP; and Semaphores: semaphores are usefull for synchronizing tasks performedin an MP system; - The external port supports a unified address space that enables direct interprocessor interface of each ADSP-TS101S processor s internal memory and register. -The DSP s four link port provide a second path for interprocessor communications with throughput of 1 G Bytes per second. Bandwidth: 14.4 Gbyte per second of DSP s internal memory; 800 Mbyte per second of cluster bus communication; 1 Gbyte per second of link port throughput; #1 #2 ADC RF #3 #4 Cost 272-6th MCM - Napoli Nov. 3rd-4th

15 2.238 Msymb/s, 4.5 Mbps, QPSK GHz Center Frequency Cost 272-6th MCM - Napoli Nov. 3rd-4th

16 SRTBED (SatNex( SJA) Objectives: 1. remote software configuration of the physical layer of the satellite terminal 2. implementation of advanced reception schemes with real-time adaptation to traffic, service and propagation conditions 3. real-time DSP testbed (available at CNIT/Florence site) and the related joint experimental activity obtained through exchange of researchers among the SJA participants Cost 272-6th MCM - Napoli Nov. 3rd-4th

17 SRTBED SJA SatNEx Satellite Communications Network of Excellence IST SJA-2420-yy SRTBED Software Radio Satellite Terminal TestBed KO+3 JAT CNIT (UFI) Other partners list Related WPs: 1200, 2420, 3200, 3300, 3400 Integration JER Spreading of Excellence (SoE) JAT classifiers: architecture initial conditions interfaces formation criteria activities organisation Star (Phase I) Loop (Phase II) Good know-how Single, montly Posting Joint (Phase I) Interleaving (Phase II) Integration measures Development of a DSP based satellite terminal test-bed starting from the experimental setup available at CNIT/UFI site. Implementation of various software defined physical layers on the testbed with real-time emulated satellite channel. Measure obtained through researcher exchanges between participating members. Use of common communication and collaboration platforms for JAT meetings Costs 50% of the CNIT budget for this SJA Objective(s) Design of a software architecture enabling the remote configuration of satellite terminals Experiments of Physical Layer adaptation to propagation, service, traffic conditions. Real-Time DSP implementation of reconfigurable satellite receivers. Work items System architecture supporting remote terminal configuration Common software platform for multi-standard satellite terminals DSP implementation of all the relevant signal processing functions involved in a satellite terminal High-Level physical layer definition language for remote terminal configuration Measurements Campaign on experimental testbed Deliverables (KO+9) SJA Report _ End of Phase I (Team Integrated and Test-Bed completed) (KO+17) SJA Report _ End of Phase II (Trials Results) Costs 30% of the CNIT budget for this SJA Objective(s) Promote the use of SR technology among satcom developers Provide technology solutions for the design of reconfigurable satellite terminals Provide training/learning opportunities Enhance technology transfers across communication areas toward a single architecture global terminal Contribute to standardisation SoE measures Submission of technical papers to journals and magazines Participation to conferences Involvement in standardization activities Information exchange with industry Information exchange with teams from other EC-IST projects, ESA projects, COST Actions and national initiatives Costs 20% of the CNIT budget for this SJA Cost 272-6th MCM - Napoli Nov. 3rd-4th