A Software Configurable Spread Spectrum Transceiver

Transcription

1 A Software Configurable Spread Spectrum Transceiver Henrique C. Miranda and Sílvio A. Abrantes INESC Porto, Largo Mompilher, Porto (Portugal) Tel.: , Fax: hmiranda@inescn.pt FEUP - Faculdade de Engenharia da Universidade do Porto Rua dos Bragas - 45 Porto, Portugal. Tel.: , Fax: Abstract A low-cost, software configurable, direct sequence spread spectrum transceiver based on a digital radio architecture is described and its implementation approach is addressed. Configuration capabilities of the graphical interface software that controls the transceiver, as well as several experimental results, namely, spectrum plots and error performance curves, are presented. Practical applications for this system are also foreseen. 1 Introduction C ommunication systems employing spread spectrum (SS) modulation are becoming very popular, mainly in the field of mobile telephony and wireless data communications (WLAN). With this modulation, multiple access techniques like CDMA (Code Division Multiple Access) become feasible and under certain conditions can lead to a more efficient use of the ever scarce radio-electric spectrum. Several air-interface standards have already been defined, being IS-95 and UMTS/IMT-2 (Universal Mobile Telecommunications Systems / International Mobile Telecommunications Systems - 2) the most important ones. In order to reduce the hardware investments to a minimum, the implementation of these communication systems should use very flexible radio hardware architectures that can be easily adapted to existing or forthcoming standards simply by changing its embedded software. These radio systems are generally termed software radios. [1][2] Recent advances in digital signal processors (DSPs) and Analog-to-Digital/Digital-to- Analog (ADC/DAC) converter technologies, including specialized VLSI circuits (e.g. digital downconverters and numerically controlled oscillators) have paved the way for the development of software radio systems using digitalization at the IF (Intermediate Frequency) or even at the RF (Radio Frequency) stages. The ultimate goal for a digital radio receiver is to directly digitize the RF signal at the antenna output and therefore implement all receiver functions in either digital hardware or software, although this later goal seems to be very difficult to attain for the time being. This is mainly due both to the lack of affordable very-high speed ADCs with adequate effective number of bits [3] and DSPs with enough computational power. This kind of radio architecture possesses important advantages when compared to its analog counterparts. The most relevant are: substantially better repeatability and stability (component aging and matching are no longer factors of performance limitation); implementation of signal processing functions that are unrealizable with analog hardware (for instance, FIR filters); hardware tweaking replaced by software tuning;

2 design of cost-effective multifunction radios supporting different modulation types and bandwidths; potential reduction in product cost and development time. 2 Direct Sequence Spread Spectrum Transceiver The system herein presented is basically a lowcost, modular direct sequence spread spectrum (DSSS) transmitter-receiver with software configurable parameters. This transceiver is based on a digital radio architecture with digitalization at the IF stage, thus retaining the advantages previously stated for this architecture. The transceiver is housed in a 19 3U rack and its image is depicted in Figure 1. Figure 1: Transceiver picture. Among the several modules that build up the transceiver, the DSSS modulator/demodulator is the main one, where all the signal processing takes place. The way these modules are interconnected is illustrated in Figure 2. Parallel port adaptor PC (runnig Linux) Common bus (address, data, control and power signals) Data interface TX + CLK RX + CLK DSSS modulador / demodulador IF Out IF In (I) IF In (Q) Power supply adaptador +5 V +12 V -12 V Switching power supply Figure 2: DSSS Transceiver module diagram. There is a common bus containing the address, data, control and power signals, where each module is attached to. These modules are described in the following subsections. 2.1 DSSS modulator/demodulator A highly integrated SS processor - the Stanford Telecom s STEL-2A [4] - forms the main building block of this module. This device integrates functions of a differential BPSK/QPSK encoder, PN modulator (spreader), BPSK/QPSK modulator, digital downconverter (DDC), PN matched filter, differential PSK/QPSK demodulator and a complex numerically controlled oscillator (NCO) which is used as the local oscillator for the modulator and DDC. The receiver input is converted to the digital IF signal by a dual flash 8-bit ADC (AD958 from Analog Devices.) [5] This converter can digitize a complex IF signal (quadrature sampling mode: IF In (I) and IF In (Q)) or a real IF signal (direct IF sampling mode: IF In (I) only with IF In (Q) grounded.) The transmitter output (IF out) is the sampled and digitally modulated signal that is analog converted by the AD978 8-bit DAC (from the Analog Devices TxDAC family.) [6] The receiver clock rate must be at least four times the receiver PN spreading rate and is limited to a maximum speed of 2 MHz (for the version of the SS processor used.) As a result, the maximum supported PN chip rate is 5 Mchip/s. Since PN modulation is symbolsynchronous in the STEL-2A (the PN code is aligned with the symbol transitions and repeats once per symbol), data rate is defined by the PN chip rate and length of the PN code (N). Hence, for BPSK modulation, the maximum data rate is 5 N Mbit/s whereas for QPSK modulation the maximum data rate is 1 N Mbit/s. In this processor, N can be 64 at maximum. The STEL-2A receiver circuitry employs an NCO and complex multiplier referenced to the receiver clock rate to perform frequency downconversion, where the input IF sampling rate and the receiver clock rate must be identical. The input IF frequency is not limited by the capabilities of the STEL- 2A. To avoid destructive aliasing, the NCO

3 should not be programmed above 5% of the IF sampling rate. Higher IF frequencies, however, can be supported by programming the NCO to operate on in-band aliases as generated by the sampling process. The following example illustrates the use of such aliases. Assume that the transceiver is to be configured for a chip rate of R c =1.288 Mchip/s and a center IF frequency of f IF = 7. MHz. It is clear that the sampling frequency should be the highest possible without overranging the maximum frequency specification of the SS processor (2 MHz) in order for the intended image to be located in the lowest possible Nyquist region 1. To minimize the aliasing distortion, f IF should be placed in the center of the selected region. Moreover, the sampling frequency must be an integer multiple of the chip rate. Taking all the previous conditions into account, the best sampling frequency is MHz, yielding the spectrum presented in Figure 3. The data interface module provides the transmitter and receiver data signals and respective master clocks. One can directly connect a BER (Bit Error Rate) tester to this interface to evaluate the error rate performance under various channel impairments. The power supply subsystem is made of a multiple output switching power supply and is connected to the common bus through an adaptor that integrates overload protection and voltage supervisory circuits. 3 Control Software All the transceiver configuration can be done through a graphical interface running on Linux operating system (ix86 platform) using the Xforms library. [7] This application can be easily ported into other UNIX platforms (or even Windows.) Several screenshots of the software interface are displayed in Figure 4. Power spectrum density output image f (MHz) 2R c Figure 3: IF output spectrum example. One should note that the 7. MHz image will have its spectrum inverted as it is laying on an even Nyquist region (the 8th one.) Although irrelevant for BPSK, the effect for QPSK will be the exchange of the in-phase and quadrature channels (these can be reversed within the SS processor, thus eliminating this effect.) The above discussion equally applies to the receiver IF frequency spectrum. (a) main (b) transmitter window 2.2 Other Transceiver Modules The parallel port adaptor incorporates the necessary logic circuitry to translate the signals of a standard PC s parallel port into the address, data and control lines of the common bus. All the configuration procedures are made via this adaptor. 1 The nth Nyquist region is defined as: ( n 3 2) fs < f < ( n 1 2 ) fs (c) receiver window Figure 4: Control software screenshots. The most relevant parameters that one can

4 control are presented below: REF dbm CENTER 5. MHz 2 KHz/div Tektronix 494P REF dbm CENTER 5. MHz 2 KHz/div Tektronix 494P transmitter section: modulation type (BPSK or QPSK), data scrambler (for spectrum whitening), chip rate, symbol rate, PN code sequence (can be any sequence up to 64 chip), number of transmitted data symbols (when in burst mode); receiver section: modulation type, chip rate, symbol rate, PN code sequence, acquisition threshold, data descrambler and the number of data symbols expected for each burst; NCO section: NCO frequency which is equivalent to the transmitter and receiver IF frequencies; test section: there is test port from which one can monitor the signal behavior at various stages of the transmitter and receiver signal processing chains; setup section: transceiver sampling frequency and parallel port number. 4 Experimental Results This system has undergone several experimental tests yielding some interesting results. These tests were performed under the following transceiver settings: sampling frequency: 2. MHz intermediate frequency: f IF =5.MHz chip rate: R c = kchip/s symbol rate: R b =1.8 kbit/s PN code sequence: 31 chip, m-sequence (generator polynomial: x 5 + x 2 +1) modulation: DPSK 4.1 Spectrum plots The spectrum plots obtained are shown in Figure 5. As can be observed, the spectrum plots are fairly clean, with good signal-tonoise ratios (SNR>6 db.) Plot (d) shows the amplitude decay of the several images. Any of db/div ATT 3 db RBW 1 KHz VBW 1 KHz SWP.5 s (a) unmodulated carrier REF dbm CENTER 5. MHz 2 KHz/div Tektronix 494P 8 1 db/div ATT 3 db RBW 1 KHz VBW 1 KHz SWP 2 s (c) data modulated db/div ATT 3 db RBW 1 KHz VBW 1 KHz SWP 2 s (b) PN sequence modulated REF dbm CENTER 25. MHz 5 MHz/div Tektronix 494P 8 1 db/div ATT 3 db RBW 1 KHz VBW 3 Hz SWP 5 s (d) images spectrum Figure 5: Transmitter IF spectrum plots. these images can be used as the transmitted IF signal, but the SNR will drop considerably for the higher order ones. 4.2 Bit error rate curves The error performance curves (presented in Figure 6) were evaluated for an AWGN channel (Additive White Gaussian Noise) and three PN code sequences were used: 11-chip Barker code, 31-chip Gold Sequence and 63-chip m-sequence. Two different chip rates were set for these tests: kchip/s and 1.25 Mchip/s. As one could expect, the longer the length of the PN sequence (higher processing gain) the lower the bit error rate (the curves in each plot are shifted by approximately the ratio of the length of each PN sequence.) For the higher chip rate test, the performance is reduced due to the fact that fewer samples per chip period are now processed by the receiver digital filters.

5 Bit error rate Error rate performance for 333 kcps Barker 11 Gold 31 M Sequence Signal to noise ratio (db) (a) BER at 333 kchip/s education tool for teaching spread spectrum or applied signal processing to communications classes; wireless local area networks with multiuser access. A forward error correction (FEC) module is planned to be included into the system, in order to enhance the BER performance. This module will be based on the STEL-24 convolutional encoder/viterbi decoder chip. [8] A suitable RF subsystem is also being designed to enable the system to be utilized in a real application. References Bit error rate Error rate performance for 1.25 Mcps Barker 11 Gold 31 M Sequence Signal to noise (db) (b) BER at 1.25 Mchip/s Figure 6: Bit error rate performance for several PN sequences. 5 Applications and Further Work Several applications can be identified for this system to be used in: packet radio networks; data communications in electromagnetically harsh environments (like telemetry in industrial plants or mains data communications); [1] J. Mitola, The Software Radio Architecture, IEEE Communications Magazine, vol. 33, pp , May [2] J. Mitola, Technical Challenges in the Globalization of Software Radio, IEEE Communications Magazine, vol. 37, pp , Feb [3] R. H. Walden, Performance Trends for Analog-to-Digital Converters, IEEE Communications Magazine, vol. 37, pp , Feb [4] Stanford Telecommunications, Inc, STEL-2A - Digital, Fast Acquisition, Spread Spectrum Burst Processor, Nov [5] Analog Devices, Inc., AD958 - Dual 8-Bit 5 MSPS A/D Converter. Rev. A. [6] Analog Devices, Inc., AD978-8-Bit, 1 MSPS+ TxDAC D/A Converter, Rev.. [7] T. C. Zhao and M. Overmars, Forms Library - A Graphical User Interface Toolkit for X, Mar V [8] Stanford Telecommunications, Inc, STEL-24 - Convolutional Encoder / Viterbi Decoder, Aug