FPGA BASED DIGITAL QPSK MODULATORS FOR ADVANCED KA-BAND REGENERATIVE PAYLOAD. Kishori Lal Sah, TVS Ram, V. Ramakrishna and Dr.

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1 FPGA BASED DIGITAL QPSK MODULATORS FOR ADVANCED KA-BAND REGENERATIVE PAYLOAD Kishori Lal Sah, TVS Ram, V. Ramakrishna and Dr. K S Dasgupta On-board Signal Processing Division Advanced Digital Communication Technology Group Space Applications Centre, Ahmedabad kishorilalsah@yahoo.com ABSTRACT This paper describes the features of the Design Verification Model of the 2.48 Mbps & 576 Kbps /2 rate Digital QPSK Modulators for Advanced Ka-band regenerative payload in GSAT-4 satellite. The entire digital blocks consisting of scrambler, differential encoder, /2 FEC and two pulse shaping filters for each modulator are designed and implemented in a single Altera Flex FPGA with 22% occupancy. This FPGA will be replaced with space qualified Actel FPGA in Flight Model. In order to achieve minimum ISI and optimum performance, 4% raised cosine (RRC) digital low pass pulse shaping filters (PSF) have been in the modulators. The RRC filter is bit wide with 25 taps. The digital implementation of PSF offers use of the modulator at variable data rate. With identical filters used in the receive chain of the demodulator, eye opening to the extent of 8.7% have been achieved. The out of band suppression at the modulator output is 4 db. The evaluated performance of these modulators is found to be comparable with standard satellite modulator. The compact size (29mm x 7.5 mm), and low power consumption (6 watts for two modulators i.e. wide band and TDM) make them suitable for use in satellite. For design, simulation and characterization of the performance, MATLAB tool has been used. Various simulation and experimental results are illustrated in this paper.. INTRODUCTION This section discusses the specification, design approach, and simulation results of Digital QPSK Modulators which are needed in the GSAT-4 Regenerative payload. One type of the unit modulates time division multiplexed channel running at 576 Kb/s (8 NB data & signaling channel data each running at 64 Kb/s) while another type modulates wide band (WB) data channel running at 2.48Mb/s for each beam. The carrier frequencies are 63 MHz & 7 MHz respectively. So, for all the 8 beams, 6 QPSK modulators are needed. The block diagram of overall QPSK Modulator is given in Figure. It accepts differential data and differential sampling clock. The sampling clock rate is 4 times the actual clock rate. It delivers QPSK modulated output after scrambling, differential encoding, /2 rate convolutional encoding of the input data stream. The details of the various subsystems of the QPSK Modulators are as follows:. Differential line receiver The incoming data and sampling clock to the Modulator are received in differential mode to suppress the undesired disturbances (cross talk, etc) that travel with desired signals. Differential Receivers having inherent high CMRR (Common Mode Rejection Ratio) characteristics are used to eliminate common mode disturbances..2 Scrambler In order to reduce the maximum power flux density and transmission requirement for Bitsync circuits in the demodulator, CCITT V.35

2 scrambler [] is used. It is self synchronizing type. output of the selected stages being added modulo-2 to form the encoded symbols. This DATA DATA CLK SCRAMBLER, DIFFERENTIAL ENCODER & CONVOLUTIONAL ENCODER G G2 PSF_I PSF_Q D/A D/A SMOOTHING FILTER SMOOTHING FILTER BUFFER BUFFER Implemented in FPGA usingverilog HDL SAMPL CLK SAMPL CLK DIVIDE BY 4 DBM DRIVER BIPOLAR CONVERTER NOMINAL O/P LEVEL + db AMP POWER COMBINER HYBRID AMP WAY POWER DIVIDER TCXO 9 DBM DRIVER BIPOLAR CONVERTER Figure. Block Diagram of the QPSK Modulator.3 Differential Encoder: In order to remove phase ambiguity from the recovered carrier in the demodulator, differential decoding is used in the demodulator. Correspondingly, a differential encoder has to be there with the modulator. The equation of the differential encoder is as follows: d k = b k d k- () Here d k is a differentially encoded bit of the encoded sequence{d k }, b k is the present bit of the message sequence { b k }and d k- is previous bit of the encoded sequence. If there is no difference between b k and d k-, then d k =, otherwise d k =. The symbol denotes a modulo-2 adder..4 Convolutional Encoder In order to improve BER in the link, Forward Error Correcting Code with a constraint length K=7 and Rate R=/2 is used. The FEC encoder [2] consists of a 7 stage shift register with the means that the code has a memory of six bits which together with the incoming data bit forms a constraint length K=7. The code generator polynomials are G =7 8 and G 2 = 33 8 with (octal notation). Since the code is transparent to 8 phase ambiguities, the incoming data stream is differentially encoded before the ½ rate convolutional encoder..5 Pulse Shaping Filter (PSF) In order to limit the Modulator Spectrum Output as per the INTELSAT specifications (IESS-38 Rev. 8)[] to minimize interference into adjacent channels, the data coming through G and G2 of FEC block need to be filtered and shaped. It is achieved by implementing a 4% raised cosine digital filter. An exactly similar filter is also put at the receive end in the demodulator for matching of the received signal. The overall filter transfer function at the receive end is raised cosine which ensures an Inter-Symbol- Interference (ISI) free impulse transmission.

3 The amplitude response of the raised cosine filter [3] is as follows: H(w) = < w < π(-α)/ts Ts ( ) ( ) ( cos w for w ) 2 π α π α π + α =... 4α Ts Ts Ts = for w > π(+α)/ts.. (2) A time domain plot for a portion of filtered data output for 2 - length sequence PRBS input to the raised cosine filter is shown in Figure 4. We observe that the amplitude of the filtered data remains undisturbed at the sampling instances and hence there is no ISI. That is why, the eye opening is % as exhibited in Figure 3. Here, w=2πf, T s is the unit symbol interval and α is the roll off factor..5. Simulation results of PSF The number of coefficients of the RRC filter is 25 with α =.4. The various simulated results with unquantized coefficients are shown in Figure 2 & Figure 3. Amplitude input data filtered data.2 RC RRC index Figure 4. Comparison of unfiltered & fitered data (unquantized) Figure 2. Impulse Response of RRC & RC Filter (unquantized) Figure 5. Frequency Response (unquantized) Figure 3.Eye Opening with 25 coefficients (unquantized) The simulated spectral characteristics at the QPSK modulated output is show in Figure 5. We observe that the out of band suppression is 4 db and the bandwidth at -4 db is 2.92 MHz. The adjacent FDM outputs are specified to be separated by 3.48 MHz. So, the adjacent channel will not interfere.

4 complement arithmetic approach [4] has been used to efficiently handle the addition and multiplication of sign numbers as required in equation (3). It facilitates the same hardware to add negative numbers and positive numbers. The design is totally implemented using Verilog HDL which enables to go for Flight model straight-way. The PSF is implemented using the Look Up Table approach [4]..6 D/A Converter Figure 6. Frequency Response of the PSF with bit quantization The digital outputs available from PSFs are passed through bit D/A converters and smoothened for analog look. They are then passed through buffers/drivers to enable them to drive 5 Ω load. Settling Time of Current Output Converter type D to A converter is 27 ns with bit resolution..7 Buffer & Driver The filtered analog outputs are adjusted to provide balanced output (bipolar form) for better carrier suppression of the modulated spectrum for equiprobable, balanced, random NRZ-L data set..8 Temperature Compensated Crystal Oscillator Figure 7. Eye pattern of the PSF with bit quantization The simulated eye pattern of the I-arm raw data at the demodulator output is shown in Figure 7. We observe that the eye opening is 8.7% with the same α = Implementation of PSF The following is the equation of the 25-tap PSF filter: Dout = 25 i= c( i) d( i)...(3) where c(), c(2), c(3)are the quantized filter coefficients and d(), d(2), d(3) are sequentially stored input data values either or-. The filter coefficients are made up of both positive and negative numbers. Two's The Temperature Compensated Crystal Oscillator (TCXO) is needed to generate carrier frequency. The TCXO frequencies for TDM & wide band channels are 63. MHz and 7 MHz respectively. The power output of each of the source is +7 dbm.. The TCXO o/p is given to an 8-way Power Divider. The 8 outputs of the Power divider are meant for 8 modulators..9 Double Balanced Mixer (DBM) The filtered output of I & Q chain are fed to IF input port of Double Balanced Mixers. A power splitter divides the TCXO output into two equal parts having and 9 phase which are fed to LO input ports of these DBMs respectively.. Power Combiner & Modular Amplifier The modulated outputs of DBMs are added together by power combiner to obtain QPSK

5 signal. Finally, the modulated output is suitably amplified to provide the required output level. 2. TEST RESULTS The measured values of amplitude and phase unbalances are as follows: Amplitude Unbalance.3 db Phase Unbalance 3 Figure. Photograph of Design Verification Model of GSAT-4QPSK Modulator Figure 8. Modulator output on Spectrum Analyzer for wide band channel -2-3 BER Performance of the QPSK Modulator for GSAT-4 uncoded(theoretical) coded (practically observed) The photograph of the wide band and TDM modulators are shown in Figure. The card size is just 29 mm x 7.5 mm and the total power consumption is approximately 6 watts with two modulators ( wide-band & TDM). The PCB is multi-layer (6 layers). 3. CONCLUSIONS BER Coding Gain=4.3 db at E-6 BER. The performance of the modulator is similar to commercially available standard satellite modulator. 2. Because of its compact size and low power consumption, it is suitable for use as satellite Data Transmitter. 3. The digital implementation of PSF offers use of the modulator at variable data rate Eb/No in db Figure 9. BER Performance with GSAT-4 Modulator & Radyne Demodulator The experimentally recorded modulator output for wide band channel (2.48 Mbps) on spectrum analyzer for 2 5 -PRBS data with 7 MHz carrier is shown in Figure 8. The BER performance with GSAT-4 Modulator and Radyne Satellite Demodulator is shown in Figure 9. Similar performance was observed with Radyne Modulator at -6 BER. 4. REFERENCES [] Intelsat Earth Station Standards Document IESS - 38 (Rev. 8) pp [2] The Forward Error Correction Handbook published by Standford Telecom, Inc. Third Edition, Application Note 8 [3] Dr. Kamilo Feher "Digital Communications satellite/earth station engineering pp -4 [4] titled "Designing FIR Filters with Actel FPGAs.

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