Hardware-accelerated CCD readout smear correction for Fast Solar Polarimeter

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Philomena Powell
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1 Welcome Hardware-accelerated CCD readout smear correction for Fast Solar Polarimeter Stefan Tabel and Korbinian Weikl Semiconductor Laboratory of the Max Planck Society, Munich, Germany Walter Stechele Chair for Integrated Systems, Technical University of Munich, Munich, Germany Monday July 10th, Session 3: Image Processing 1

as satellites Lower costs Can we install FSP on SUNRISE?

2 Related projects Fast Solar Polarimeter (FSP) Full custom camera Solar ground-based observations 1m solar telescope SUNRISE On a stratosphere balloon Same image quality as satellites Lower costs Can we install FSP on SUNRISE? No, readout smear will hinder the post-facto correction of image jitter. An online correction can solve this problem 2

Readout smear models for the FSP camera δ: relative transfer-time α : relative switching-time S: smeared column Y: unsmeared column k: time index Ground-based observations Constant scene 4

3 Readout smear models for the FSP camera δ: relative transfer-time α : relative switching-time S: smeared column Y: unsmeared column k: time index Ground-based observations Constant scene 4 polarization states Circularly appearing images Accumulation and inversion General solution for corrected image column Not constant scene For a jittered balloon flight 2 x 1024 half-columns 512 pixel/half-column 400 images/second 1 hour burst length How to compute? 3

4 Optimization of the algorithm 1) Quadratic complexity Undefined length of series Convergent 2) Correction via n successors only 3) Approximation with fake assumption of periodicity Matrix becomes circulant 4) 5) The inverse of a circulant matrix is circulant Matrix-vector multiplication with a circulant matrix is a convolution A block of a circulant matrix is of Toeplitz type Each Toeplitz matrix can be extended to a circulant matrix 4

cores: The correction needs to be done in single precision floating point Choose a mixed-model with n є

5 Design space exploration 1 Study and single unit => no ASIC FPGA instead of CPU / GPGPU: Power dissipation in the stratosphere 10G Ethernet peripherals on-chip No need for hosts => Focus on Xilinx FFT cores: The correction needs to be done in single precision floating point Choose a mixed-model with n є [4:6] Uint16 image data should be transformed using a 31 bit fixed-point transform Twiddle factor width is 24 bit <= 5

6 Design space exploration 2 NetFPGA SUME offers QDR II+ SRAM 6.7 gbps Ethernet stream 209 M samples per hemisphere Requirements: Rotation of the image Parallelization FFT, multiplication, IFFT Degrees of freedom DDR3 vs. QDR II+ => simple design for feasibility study targeting a single unit camera Sequential vs. parallel algorithm => parallel version is always fast, slightly more expensive in logic, can be built in before the RAM, and can be easily configured to different depths of correction Order of RAM and FFT => FFT before RAM would increase memory costs Tasks Use one RAM-module per hemisphere, rotate image during write access Readout of parallel image-data Parallel fixed-point FFT Cast to single precision floating point, multiply with constants, cast to fixed-point, IFFT Interface 10Gig Ethernet 6

7 Memory and logic design 209 M 225 MHz write Write single pixel for image rotation Row LSB for column access during read burst Each word serves as ring buffer for image bursts A crossbar is necessary at read side n times higher read n parallel and synchronous inputs Correction values are constant (ROM) Synchronous calculations Higher throughput than in stream FFT modules are extended with typecasts One FFT module transforms 2 signals 7

Parallelization 1 sensor 2 RAMs 4 pipelines 1 stream Throughput and capacity require one RAM per hemisphere Parallel algorithm forces temporal multiplexing on two logic pipelines per RAM (zero

8 Parallelization 1 sensor 2 RAMs 4 pipelines 1 stream Throughput and capacity require one RAM per hemisphere Parallel algorithm forces temporal multiplexing on two logic pipelines per RAM (zero insertion) Sequential variant can be built with lower logic resources at the costs of RAM Twice the clock-rate at 2 pipelines did not meet timing constraints No buffers at the memory interfaces, straight forward stream 8

Results and tests Implementation: n = 4 SRAM not included in table

co-design with camera Separate throughput test, later testing Readout

9 Results and tests Implementation: n = 4 SRAM not included in table Correction for n=4 => max. error = 2 (Uint16) Correction for n=6 => max. error = 1 (Uint16) Cutoff due to noise => 3 bit in Uint16 Model-based, co-design with camera Separate throughput test, later testing Readout smear is a convolution Stepwise correction removes copies of the image FPGA module allows to use the FSP camera on the SUNRISE balloon mission 9

10 That`s it! Thank you very much for your interest! Your questions, please. 10

Wideband Down-Conversion and Channelisation Techniques for FPGA. Eddy Fry RF Engines Ltd

Wideband Down-Conversion and Channelisation Techniques for FPGA Eddy Fry RF Engines Ltd 1 st RadioNet Engineering Forum Meeting: Workshop on Digital Backends 6 th September 2004 Who are RF Engines? Signal