Using HLS in Digital Radar Frontend FPGA-SoCs. Dr. Jürgen Rauscher 11 October 2017

Transcription

1 Using HLS in Digital Radar Frontend FPGA-SoCs Dr. Jürgen Rauscher 11 October 2017

2 Content Short Company Introduction FPGA-SoCs in Radar Frontends Using High-Level Synthesis (HLS) in Extended Frontend Processing 2

3 HENSOLDT: The new Sensor House We bring 100 years of defence and security electronics under one roof HENSOLDT stands for: The spirit of technological progress and the continuous quest for premium solutions reined in by a solid sense of efficiency A strong corporate heritage from leading European Defence companies An extensive sensors portfolio which establishes a broad technological basis from which to fulfil the ever-changing customers needs 3

4 Our Fields of Competence Air, Sea, Land HENSOLDT all major sensor technologies under one roof Information superiority for political and military leadership Situational awareness for optimum protection in the air, at sea, on land 4

5 Challenges and Trends for Radar Frontends SWaP-C (Size, Weight, and Power consumption, less Cost) Multipurpose/Multifunctional Radar (Swiss Army knife) Low lot size compared to consumer market Limited component choice (e.g. due to export restrictions, environmental conditions, reliability, obsolescence, ) D/A antenna LO control A/D SoC-FPGA FOL Data Processing Digitalization of the frontend A/D D/A conversion closest to antenna Enormous data reduction necessary Limited thermal budget Limited size and weight 5

6 Radar Signal Processing in FPGA-SoC Processing System Command & Control A/D, D/A initialization, (running in processing system) Programmable Logic Corner Turning (e.g. DDR4) A/D DDC (CIC/FIR Filter) Digital Beamforming (e.g. cplx. MULTS) Range Proc. (e.g. FFT) Doppler Proc. (e.g. FFT) Constant False Alarm Rate D/A Digital Waveform Generator (NCOs) Adaptive Beamforming / Space Time Adaptive Processing (matrix inversion) Detections (Range, Velocity, AOA, ) extreme data reduction Fixed Point Potentially Floating Point due to High Dynamic Range (>120 db) 6

7 Radar Study Extended Frontend Pre-Processing to be realized in FPGA-SoC 16 Channel IF signal Digital IQ + Decimation 16 Channel baseband signal Digital Beamforming 16 Antenna lobes Doppler-FFT Desensitization SUM/DIF/Guard Detection Threshold (CFAR) Detections Sidelobe Cancellation Detections in main lobes Monopulse Detections with bearing angle Plot Extraction Strongest detections per direction 7

8 Study Conceptual Design DDR GBit/s 70 GBit/s FFT for Doppler Processing: ~ 4 N log 2 N - 6N + 8 > 50.4 GFLOPS 22.4 GBit/s Predominantly HLS 8

9 High Level Synthesis + applying directives e.g. set function initiation interval (II) = wait time of the consumer module for a new value in clocks Clock Cycle x a b c * + + y Finite State Machine (Control Logic) Register 9

10 Why should one use HLS? Functional verification can be done in C / Final validation in RTL: C simulation is orders of magnitude faster than RTL simulation (seconds compared to days or even weeks) Maintainability of HLS design is usually better (e.g. pipelining is done by the HLS tool) Design iterations can be done much faster Design entry for complex algorithms is much easier Floating point is fully supported You get immediately resource and timing estimates (no need for PAR iterations) 10

11 HLS Example: Doppler Processing 11

12 HLS Example: CFAR Still in-depth FPGA technology knowledge needed to achieve performant solutions (actually even more experience is needed than for RTL design) 12

13 HLS just another form of design entry? You can approach your solution from functional C and see what results you can get with HLS Usually you have to solve a given problem (given throughput, given functionality, limited FPGA resources, timing restrictions, ) In most cases you will have to rewrite the C code in a FPGA-friendly way You will have to think how the synthesis tool will map the C code to RTL You will have to spend some time to create directives to help the synthesis tool to do it right Don t expect that this initial design entry goes faster than in VHDL in all cases; especially if you want to realize a non-trivial design component (you might save a lot of time for implementing algorithms which are not well suited for RTL design) Example: Think about a block which shall be able to process some input data at each clock cycle. Each input data is related to a specific detection (1 out of 8). The processing in the block needs to keep some interim values which it will read with each update from RAM and write it back after the values have been updated. The calculation of the update for the interim values takes several clock cycles. As an FPGA engineer you know you will get an update only every 8 th clock cycle for the same detection (= same address). But now you have to explain this the HLS tool to use this information in terms of directives ;-) 13

14 HLS where does it make sense? Functionality Linear algebra (e.g. QRD) Trigonometric calculations AXI4 DMA engines Floating point calculations Heavily pipelined IF THEN ELSE stuff Complex algorithms Filter (e.g. Polyphase FIR, CIC) FFT Control logic (clock cycle based timing) Well suited Yes Yes Yes (Xilinx Vivado HLS) Yes Yes Yes No No No 14

15 Radar Study Device CFAR HLS Monopulse RTL DBF Doppler FIR/CIC 15

16 Radar Study 3 successful flight test campaigns Fully integrated sensor including FPGA-SoC design works perfectly 16

17 Summary Not feasible to hand code Radar Frontend FPGA-SoCs anymore within given development time and budget In the right hands, HLS allows to efficiently realize even modern Radar floating-point algorithms in FPGA-SoCs; like STAP, adaptive beamforming and CFAR In the real world more in-depth FPGA technology knowledge is needed to use HLS successfully compared to traditional RTL design Algorithm changes can be implemented much faster than in hand-coded FPGA designs Radar Frontend FPGA-SoCs provide an unrivaled level of system performance per Watt Closer collaboration between SW, HW, FPGA and Algorithm engineers necessary to get the most of FPGA SoCs 17

18 Thank you for your attention! Juergen Rauscher Woerthstrasse Ulm Germany T +49 (0) E juergen.rauscher@hensoldt.net 18