Real-time Implementation of Digital Coherent Detection

Transcription

1 R. Noé 1 Real-time Implementation of Digital Coherent Detection R. Noé, U. Rückert, S. Hoffmann, R. Peveling, T. Pfau, M. El-Darawy, A. Al-Bermani University of Paderborn, Electrical Engineering Optical Communications and High-Frequency Engineering

2 R. Noé 2 Outline Introduction Real-time constraints for coherent receiver algorithms Angle-based phase estimation for QPSK Combination with polarization multiplex Integrated DSPU for a PDM-QPSK receiver Real-time measurement results Conclusion and outlook

3 R. Noé 3 Coherent QPSK transmission QPSK transports 2 bits per transmitted optical symbol compared to OOK Lower symbol rate enhances chromatic and polarization mode dispersion tolerance (10 Gbaud Polarization multiplex QPSK 40 Gbit/s) Feedforward receiver concepts can easily be implemented using digital signal processing compared to classical OPLL approach. Off-the-shelf, low-cost, small-sized DFB lasers suffice in spite of phase noise.

4 R. Noé 4 Coherent optical receiver structure single-chip or modular system TX Local oscillator LO 90 hybrid 90 hybrid DSPU Digital Signal Processing Unit I1 Q1 I2 Q2 Compensation of intermediate frequency and phase noise, polarization crosstalk, PMD, CD, (nonlinear effects,) using digital signal processing.

5 R. Noé 5 Internal structure of the DSPU 1:m demux 1:m demux 1:m demux 1:m demux T-spaced sampling: f IN = 1/T S T/2-spaced sampling: f IN = 2/T S f DIV = f IN /m feedback path Algorithms must be compatible to the receiver structure! m:1 mux m:1 mux m:1 mux m:1 mux f OUT = 1/T S I1 Q1 I2 Q2

6 R. Noé 6 Real-time constraints for receiver DSP algorithms Demultiplexing and parallelization allows to use standard logic elements with relaxed clock speed requirements. Delay robustness of control algorithms for all the cases when feedback loops cannot be avoided at all. Efficient hardware is required to enable a high degree of parallelization with moderate area and power consumption.

7 R. Noé 7 Feasibility of parallel processing sampling frequency: 10 GHz to 56 GHz 1:m demux 1:m demux 1:m demux 1:m demux Demultiplexing to parallel channels DSPU clock frequency: 100 MHz to 800 MHz m:1 mux m:1 mux m:1 mux m:1 mux I1 Q1 I2 Q2

8 R. Noé 8 Comparison of FIR and IIR filters x x k T k-1 x T k-2 x k y k α 0 α 1 α 2 β 2 β1 y k serial y k-2 T y k-1 T parallel data not instantly available

9 R. Noé 9 Real-time constraint: Hardware efficiency Computationally complex algorithms increase the required chip area, power consumption and cost. Ways to increase hardware efficiency: Signal transformations, example: FFT/ IFFT Convolution FFT/IFFT Use of look-up tables Multiplication Optimization of the required precision

10 R. Noé 10 Real-time constraint: Tolerance against feedback delays Digital signal processing for coherent optical receivers requires massive parallel processing, pipelining. 1:m demux 1:m demux 1:m demux 1:m demux m:1 mux m:1 mux m:1 mux m:1 mux I1 Q1 I2 Q2

11 R. Noé 11 Decision-directed carrier recovery Y k FF e j ψ ˆ k 1 exp{-j( )} ^ ψ k decision circuit W(z) filter function arg( ) - ^ X k Feedback delay of 1 symbol arg( ) jψˆ k 5 m e FF exp{-j( )} ψ^ k-4m FF Y k-m1 Linewidth tolerance is significantly reduced! Y k FF FF FF FF Decision Decision arg( ) circuit Decision FF circuit decision FF arg( ) FF arg( ) circuit FF arg( ) circuit arg( ) FF arg( ) FF arg( ) FF FF arg( ) - FF - FF - FF - FF FF ^ X k-3m1 ^ W(z) X k-2m

12 R. Noé 12 Feedforward carrier recovery Viterbi & Viterbi Algorithm [1] : Y k ( ) 4 2N CR 1 2. Polarisation arg( ( )) ( )/4 1.5 ϕˆ k 1 Barycenter-Algorithm [2] : 0.5 ϕ k Y k arg( ) ( )mod π 2 ϕˆ k nd Polarization [1] R. Noé, IEEE J. Lightwave Technology, Vol. 23, No. 2, Feb. 2005, pp [2] S. Hoffmann et al., IEEE Photon. Technol. Lett., Vol. 21, No. 3, Feb. 2009, pp

13 R. Noé 13 Barycenter algorithm Inherent weighting due to multiple use of inputs Im Re Y k arg( ) ( )mod π 2 ϕˆ k Each filter cell averages pairwise along shortest path.

14 Digital synchronous QPSK receiver scheme R. Noé 14 Differential encoding of data quadrant number n d in TX TX fiber LO E TX E LO l 11 l 22 l 21 l 12 Re X Im X A/D and 1:M DEMUX Mod. M Mod. 2 Mod. 1 demultiplexed output data bits o 1, o 2 Functionally identical with analog scheme X ~ E TX E LO * Module (i mod M) All signals it needs from neighbor modules are already available. X(i) ( ) 4 (X(i 1)) 4 (X(i 2)) 4 (X(i))4 (X(i 2N)) 4 Frequency quadrupling LPF X(i N) Lowpass filtering Y(i) Signal phase ψ(i) arg( ) n r (i 1) (1/4)arg( ( )) ϕ(i) Carrier phase angle ϕ(i 1) n j (i) Quadrant phase number (0, 1, 2, 3) n r (i) n o (i) o 1 (i), o 2 (i) Differential decoding of quadrant phase number, taking carrier phase jumps into account

15 Detection and correction of quadrant phase jump R. Noé 15 ϕ π/4 0 π/4 n j (i 0 ) π/2 chosen course i 0 1 i 0 i physical course n j n j (i) n r (i) n o (i) = n d (i N) n c (i N) 0 n r (i) n r (i 1) i 0 1 i 0 i Data bits d 1, d 2 quadrant number n d Differential encoding of quadrant number in transmitter: nc () i = nd ( i) nc ( i 1) mod Differential decoding of quadrant number in receiver, taking phase jumps into account! ( ) 4 d 1, Re c, o 1 d 2, Im c, o 2 n d, n c, n o

16 R 1 (i) R 2 (i) Z(i) M X 1 (i) (X 1 (i)) 4 (X 2 (i)) 4 X 2 (i) Electronic polarization control data recovery 1 data recovery 2 Z(i 1) Z(i 2) Z(i 2N) LPF ϕ(l) cos( ), sin( ) e jϕ(l) X 1 (l N), X 2 (l N) Y(i) n r,1 (l), n r,2 (l) ϕ(i 1) n j (i) ϕ(i) (1/4)arg( ( )) Q(l) M(l) Q X p (i N) X p (i) ( ) 4 (X p (i)) 4 ψ p (i) arg( ) ϕ(i) n r,p (i 1) n j (i) ( ) ( ) ( ) jϕ( i i = 1 2 X i N e ) r( i) := ( 1 g( 1 Q) )M n r,p (i) n o,p (i) ( NA) R. Noé 16 Q be a perfect estimate of MJ M : = Q M = ( MJ) M = J Q 1 1 = ( 1 ( 1 Q ) A be a data vector N = A o p1 (i), o p2 (i) Q ( Q ) M g 10 3 results in well sufficient accuracy of matrix elements and control time constant on the order of 10 3 cycles. At 10 Gbaud control time constants down to 100 ns are possible.

17 R. Noé 17 Decision-directed polarization control Phase offsets are compensated! Z Z k, x k, y M M k Matrix-update ( 1 Q k ) k k 1 := M k g M Control target is to force the correlation to the unity matrix. Y Y k, x k, y Q k Carrier & data recovery ϕˆk Correlation Q k = Y Y k, x k, y e cˆ c ˆ j ˆ ϕ k, x k, y k cˆ cˆ k, x k, y R. Noé, IEEE Photon. Technol. Lett., Vol. 17, No. 4, April 2005, pp

18 R. Noé 18 DSP components for real-time synchronous QPSK transmission Single-chip system DEMUX DEMUX DEMUX DEMUX DSPU Highest integration small footprint Simple interfacing Common technology for s and DSPU suboptimal performance Multi-chip system DEMUX DEMUX DEMUX DEMUX DSPU Optimum performance Possibility to use commercial s Complex interface Increased footprint

19 R. Noé 19 Chip Specifications SiGe CMOS ASIC Technology 0.25µm SiGe Resolution 5 bit Number of transistors 3378 Chip size 5.4 mm 2 Supply voltage -4 V, 1.8 V Measured power consumption 2.7 W Measured full scale range 410 mv Measured DNL < ± 0.45 LSB Measured INL < ± 0.35 LSB Sampling frequency > 10 GHz Measured input bandwidth > 5GHz Standard Cell Design Full Custom Design Gates 306,963 Devices 11,838 Std. cells 121,576 Max. frequency 10 GHz Max. frequency 625 MHz Supply voltages 1.8 V,1.2V Supply voltage 1.2 V Power consumption 1.5 W Power consumption 0.5 W Combined Standard Cell and Full Custom Designs Power 2 W Technology 130 nm bulk CMOS Size mm 2 Pads 146 Supply voltages 1.2 V, 1.8 V

20 R. Noé 20 5-bit 10-GS/s analog-to-digital converter technology resolution 0.25 μm SiGe:C BiCMOS 5 bit number of transistors 3378 chip size 5.4 mm 2 supply voltages measured power consumption measured full scale range (V FSR ) measured DNL measured INL sampling frequency measured input bandwidth measured SNR -4 V 1.8 V 2.7 W 410 mv < ± 0.45 LSB < ± 0.35 LSB > 10 GHz > 5 GHz (10 GSymbol/s) up to 30 db O. Adamczyk et al., Electron. Lett., Vol. 44, No. 15, July 2008, pp

21 R. Noé Digital signal processing unit Full-custom Standard-cell ASIC Complexity [transistors] 11,838 1,216,000 1,227,838 Area [mm²] Frequency [MHz] 5,000 half-rate 625 5,000 half-rate Power Supply [V] ,

22 R. Noé 22 Digital signal processing unit Full-custom Standard-cell ASIC Complexity [transistors] 11,838 1,216,000 1,227,838 Area [mm²] Frequency [MHz] 5,000 half-rate 625 5,000 half-rate Power Supply [V] , 1.2

23 Components R. Noé 23 5-bit 10 Gsample/s flash A/D converter chip Size: 2.1 mm 2.55 mm 0.25µm SiGe CMOS ASIC 4.1 mm 4.1 mm 130 nm bulk CMOS Co-packaged module Ceramic substrate 8.5 cm 6.0 cm

24 R. Noé Gb/s polarization-multiplexed QPSK transmission 4 x 700 Mb/s I1 Q1 I2 Q2 precoder PBC DFB laser QPSK modulator Signal laser 45 PBS SSMF 80 km QPSK modulator precoder DSPU hybrid 90 hybrid PBS 45 DFB laser Polarization scrambler PBS Local oscillator no x-talk: SOP is manually adjusted, that the polarization cross-talk is minimized. Switching noise is minimized. x-talk: SOP is manually adjusted, that the polarization cross-talk is maximized. Switching noise is maximized. 50 rad/s: SOP is scrambled with 50 rad/s on the Poincaré sphere. Switching noise is the average value of best and worst case.

25 R. Noé 25 Experimental transmission setup Poincaré sphere traces measured with polarized signal: 4 x 700 Mb/s precoder PBC DFB laser QPSK modulator Signal laser 45 PBS SSMF 80 km QPSK modulator precoder Photline polarization scrambler 12 motorized quarterwave plates motorized half-wave plate (bulk optic) HWP PDL variable PDL element (0 6 db) VOA PBS Local oscillator 45 DFB laser PBS CeLight Israel 90 hybrid 90 hybrid I1 Q1 I2 Q Xilinx Virtex 4 FPGA 25

26 R. Noé 26 Measurement results fast polarization changes & receiver sensitivity penalty c=0.75μs c=3.00 μs 0 krad/s 20 krad/s 40 krad/s

27 R. Noé 27 Measurement results polarization-dependent loss

28 R. Noé 28 Generation of fast endless polarization changes by mechanical halfwave plate, inserted between fiberoptic quarterwave plates

29 R. Noé 29 Conclusion General real-time requirements for the DSPU: Parallelization Delay tolerance Hardware Efficiency Angle-based phase recovery concept (barycenter): simple, linewidth-tolerant Polarization diversity with automatic polarization demultiplex Realtime coherent receiver implementation: SiGe, CMOS DSPU Test results: 10 Gb/s, 40 krad/s

30 R. Noé 30 Acknowledgement European Commission FP6 contract synqpsk Univ. Paderborn, Germany CeLight Israel Photline, France IPAG, Germany Univ. Duisburg-Essen, Germany Thank you for your attention!