The NemeriX G3 chipset : a radiation hardened front end for GNSS receivers aimed at space application
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1 The NemeriX G3 chipset : a radiation hardened front end for GNSS receivers aimed at space application Angelo Consoli & Francesco Piazza; NemeriX Hannes Schwammschneider; Austrian Aerospace AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
2 Outline G3 Chipset Requirements Microelectronic Technology Selection Architecture of the 2 ASICs First Space Application using the ASICs AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
3 NemeriX s G3 chipset The chipset consists of 2 ASICs: NJ1007R: RF receiver front end NJ1017R: AD DA interface Requirements Multifrequency receiver GPS/Galileo/GLONASS High RF performances more important than integration level or cost effectiveness Radiation tolerant design for space borne applications Technology selection criteria: Shall have good RF performance. Shall be available also in small quantities. Shall be either radiation tolerant or allow radiation tolerant circuits to be designed. AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
4 The G3 chipset Main Reason for a Chipset: Prevent interference between AD converters and sensitive RF circuitry. NJ1007R: Pure analog RF ASIC S35, SiGe process NJ1017R: Massive digital ASIC. C35 process would be fine. S35 was selected in order to produce NJ1007 and NJ1017 on the same wafer. Main advantages: Reduced costs Easier qualification process AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
5 System configuration NemeriX s RF front end BB processor AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
6 G3 chipset common parameters Supply voltage AVDD DVDD to AVDD+0.2 V V Power Supply in active mode NJ1007R supply 3.6V AVDD DVDD (*) ma µa NJ1017R Supply 3.6V AVDD DVDD 2 <1 (*) ma ma Radiation Tolerance Total Dose Heavy Ions krad(si) MeV/mg/cm 2 (*) Excluding load AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
7 Package solution: 36-CBGA 5x0.8= ± ± ± ± ±0.05 NJ10xxR CERAMIC KYOCERA A473 SOLDER LID 42 ALLOY / Solder KC ±0.15 AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
8 General: Process selection Thin layers (wells, diffusions, oxides). Thick N-well may improve latchup. Retrograded well or buried layer and epi improve latch-up resistance. SOI has no mechanism to generate a latch-up. Deep trenches improve latch-up somewhat. BJT: Thin base and emitter more robust than thick base (less β degradation). Poly emitter (thinner) more robust than a diffused one. MOS: Thin gate oxide better than thick oxide (less charge trapping, less device degradation). Shorter channel transistors (stronger) give improved SEE resistance. Process: AMS S35, 0.35µm SiGe HBT AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
9 Microsection of the S35 process (NJ1007R) Polymide Passivation Thick Metal 4 Oxide + Vias Metal 3 Oxide + Vias Metal 2 Oxide + Vias Metal 1 Oxide + Vias Substrate AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
10 NJ1007R RF receiver front end GNSS Antenna L3 RF-Filter IF-Filter 1 IF-Filter 2 C2 L4 SAW SAW or LC C3 C4 C5 AVDD AVSS LNO RFP RFN MIXP MIXN IF1P IF1N IF2P IF2N I AVDD AVSS OIP RFin L1 C1 L2 LNI LNA DBM VGA Q LPF (15MHz) OIN OQP OQN VB bias :8 (:4) :N1 log :2 :4 :N2 AGCI To ADC, base-band processor Integrated LNA External filters I/Q outputs VBG C6 C7 RENB Die size: 1.2 x 1.0 mm Signal Bandwidth < 24MHz L5 RF LO inductor PFC NJ1007 RL1 RL2 RPLL IENB IL1 IL2 PFC L6 RF IF IF LO Loop Loop inductor C8 C9 filter C10 C11 filter IPLL reg RCP DIO AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
11 NJ1007R characteristics Gain 19 db LNA Noise figure IP db dbm 1 db compression point -22 dbm Conversion gain 25 db RF Downconverter SSB noise figure IP db dbm 1dB compression point -18 dbm NJ1007 (G3RF) IF Strip AGC amplifier gain Gain control range db db RF VCO sensitivity 800 MHz/V RF-VCO IF-VCO RF SSB phase noise IF VCO sensitivity IF SSB phase noise 100kHz 1kHz 10Hz 100kHz 1kHz 10Hz dbc/hz dbc/hz dbc/hz MHz/V dbc/hz dbc/hz dbc/hz PLL spurs <35 dbc AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
![NJ1017R :4 :63 PFC SEL[3:0] :2 :16 bias D1 F4 3 I[2:0] B5 C4 D4 E4 B4 A4 B3 A2 C3 D2 D3 3 reg DVDD 8bit AGC DAC DVSS Q[2:0] SCK CKD MISO MOSI CS_B FREF F2 E3 F3 E1 E2 F1 C1 C2 A1 B1 B2 A3 C6 C5](/docs-images/94/118986504/images/12-2.jpg "AVDD DVDD out in To bb processor (I/Q data and clock) DVDD To SPI-like interface TCXO DVDD AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA - www.nemerix.")
12 NJ1017R AD DA Interface ASIC 2 ADCs (for I/Q outputs of NJ1007R) 3-bit Sampling frequency < 50MHz 8-bit DAC (for AGC) SPI like interface to the base band processor PLL (for sampling clock) I-In From RF front-end Q-In Loop filter From RF front-end R1 C3 C2 C1 C4 C5 C6 D5 D6 F5 F6 E6 B6 A6 A5 E5 AVDD IIP IIN IQP IQN VOSC LF VBG AGCO DIO RCP AVSS I Q ADC-3bit (flash) ADC-3bit (flash) NJ1017R :4 :63 PFC SEL[3:0] :2 :16 bias D1 F4 3 I[2:0] B5 C4 D4 E4 B4 A4 B3 A2 C3 D2 D3 3 reg DVDD 8bit AGC DAC DVSS Q[2:0] SCK CKD MISO MOSI CS_B FREF F2 E3 F3 E1 E2 F1 C1 C2 A1 B1 B2 A3 C6 C5 AVDD DVDD out in To bb processor (I/Q data and clock) DVDD To SPI-like interface TCXO DVDD AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
13 NJ1017R characteristics DNL 0.5 LSB INL 0.5 LSB 3-bit ADC Max sampling freq. <50 MHz Input Voltage range 700 mvpp SFDR 25 db NJ1017 (G3AD) AGC 8-bit DAC DNL INL Output Voltage range LSB LSB V Frequency Range MHz VCO, PLL RF SSB phase noise 1MHz 10kHz 100Hz db db db AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
14 NJ1007R chip layout AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
15 NJ1007R chip on CBGA substrate AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
16 Close view of bonded NJ1007R AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
17 Overview of G3 chip set Lot Validation Project started in 2007 Lot Validation based on ESCC9000 including Wafer Manufacturing Wafer Lot Acceptance including Total Ionizing (TID) Dose testing Packaging of Evaluation Lot Evaluation Test Packaging of Flight Lot Screening of Flight Lot Lot validation of Flight Lot Completion expected early 2009 AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
18 G3 chip set First Application GPS based Precise Orbit Determination (POD) Receiver for ESA-SWARM Mission Down-converts and digitizes the GPS L1 and L2 signals by means of Nj1007R and NJ1017R, RF- and mixed-signal ASICs AGGA-2 chips and a LEON processor form the heart of the digital signal processing AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
19 G3 chip set First Application AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
20 G3 chip set First Application AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
21 G3 chip set First Application Interfaces UART (RS-422) TC/TM interface MIL-STD-1553B TC/TM interface extension Electronic Box Box Size: 322x240x104 mm 3 Weight: < 3.5 kg including antenna Power Consumption: < 10W Antenna Patch Excited Cup Antenna with improved multipath suppression from Saab Space AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
22 Conclusions G3 Chipset consists of RF Front-End and AD Converter Chipset is Radiation Tolerant (120 krad(si); 84 MeV/mg/cm 2 ) G3 ASICs are Being Qualified to ESCC9000 First Application for SWARM Mission (under construction) Thank you for your attention AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright 2008 NemeriX SA
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