Development and Evaluation of Advanced Electronic Components and Technologies

Transcription

1 25th Microelectronics Workshop Development and Evaluation of Advanced Electronic Components and Technologies Florence MALOU with the participation of David DANGLA CNES, France 2nd November 2012

2 COMPONENTS DEVELOPMENT PROGRAM AT CNES OUTLINE DEVELOPMENT AND SPACE EVALUATION FLOW VLSI & ASIC TECHNOLOGIES DEVELOPMENT AND EVALUATION PROGRESS REPORT DSM TECHNOLOGIES RELIABILITY AND RADIATION TESTS RESULTS FUTURE CHALLENGES CONCLUSION 2

3 COMPONENTS DEVELOPMENT PROGRAM AT CNES OUTLINE DEVELOPMENT AND SPACE EVALUATION FLOW VLSI & ASIC TECHNOLOGIES DEVELOPMENT AND EVALUATION PROGRESS REPORT DSM TECHNOLOGIES RELIABILITY AND RADIATION TESTS RESULTS FUTURE CHALLENGES CONCLUSION 3

4 OBJECTIVES OF THE COMPONENTS DEVELOPMENT PROGRAM To contribute to the European non dependence Avoid possible embargo (ITAR restriction, ), Contribute to the exploitation of the European capabilities in terms of space components Propose, in time, state of the art technologies and components with a good readiness level and at a reasonable cost To Support the competitiveness of European Space industry Equipment manufacturers» Allow the space industry to have access to state of the arts components» Increase systems and equipment performances» Be able to propose new applications (New Generation telecom payloads, ) Component manufacturers» Develop a production capacity of HiRel and radiation hardened components to a reduced number of component manufacturers» Develop as much as possible their products portfolio in order for them to be attractive and get back a significant revenue Program harmonized through the ESCC/CTB and coordinated with ESA Collaboration with JAXA Budgets : Approx. 2M per year - CNES funding participation target : 50 % 4

5 COMPONENTS DEVELOPMENT PROGRAM AT CNES OUTLINE DEVELOPMENT AND SPACE EVALUATION FLOW VLSI & ASIC TECHNOLOGIES DEVELOPMENT AND EVALUATION PROGRESS REPORT DSM TECHNOLOGIES RELIABILITY AND RADIATION TESTS RESULTS FUTURE CHALLENGES CONCLUSION 5

6 DEVELOPMENT PHASE Define the target specification reflecting Space industry needs Design the product on the selected process : Architecture study Mitigation techniques Modelling Simulations Design reviews to authorize or not to go-on manufacturing Manufacture the prototypes Perform electrical & radiation characterization : If the results are not in line with the target spec Design re-spin up to reach the performances If the design is OK Go to Evaluation stage 6

7 EVALUATION PHASE What is the purpose of an Evaluation phase? During this phase, components and technologies are extensively characterized and tested ( to destruction wherever possible) Tests are designed to : Gauge reliability and lifetime Provide stresses that» Simulate thermal, mechanical, electrical, vacuum and radiation environments» Address intrinsic and extrinsic failure modes» Allow to determine the margins for these failure mechanisms Bathcurve The idea is to learn about the components, not just to verify that they can survive a pre-defined stress level or a suite of tests 7

8 EVALUATION FLOW Evaluation phase consists of : Preparation of an ETP (Evaluation Test Plan) Manufacturer Evaluation ( incl. subs if considered necessary) Component Evaluation Testing by the Manufacturer and monitoring by the Tech. Officer Evaluation phase Outputs : Evaluation report Applicable Detail Specification(s) Final PID(Process Identification Document) A Generic Specification if not existing Introduction in EPPL (European Preferred Parts List) 8

9 EVALUATION FLOW 9

10 COMPONENTS DEVELOPMENT PROGRAM AT CNES OUTLINE DEVELOPMENT AND SPACE EVALUATION FLOW VLSI & ASIC TECHNOLOGIES DEVELOPMENT AND EVALUATION PROGRESS REPORT DSM TECHNOLOGIES RELIABILITY AND RADIATION TESTS RESULTS FUTURE CHALLENGES CONCLUSION 10

11 Objectives : ASIC from ATMEL / STMicroelectonics CMOS065 LP DSM technology is required for next generation flexible Telecom payloads : Higher ASIC complexity : 20 to 30 Millions gates, Clock data path ~ 400 MHz, Power dissipation per ASIC 15 Watts, Multiple HSSL links at 6.25 Gbps Process : ST 65nm LP CMOS (F) Agreement between ATMEL and ST: ST will be technology provider and ATMEL will be the ASIC vendor 65nm Space platform specification : 1st ASIC platform : Rad-Hard Dedicated Libraries for Space IO Libraries : I2C, CMOS IO and LVDS with cold spare feature 1.2GHz PLL New Memories and associated BIST/ECC for SPACE Extension of library parameters to simulate 20ys aging 100 krads No SEL at 70MeV/mg.cm², SEU hardened DFF s + 2 nd ASIC platform : HSSL IP PLL for Delay compensation Flip-Chip package Status : 1st ASIC offer design completed with integrated ST Design in Reliability (DiR) methodology ESCC evaluation in progress by ST end Q2/13 (See preliminary results in next section ) ATMEL is initiating the 65nm ASIC deployment and design support to 1st Telecom ASIC CAD Flow, HSSL IP hardening, Flip Chip package dvlpment, under ESA contracts, KO in Q4/12. 11

12 ASIC from ATMEL 0.15µm SOI Objectives: Manage near obsolescence of digital.35µ and.18µ digital technologies for small (500Kg- 1Mg) and medium (5Mg) ASIC s needs Process : LFoundry 0.15µm SOI (F) 0.15µm SOI offer specification : Digital radhard library 5V IO compatibility 1.8V Low voltage - Processes with 3.3V I/Os logic devices PLL EEPROM blocks Analog devices No SEL at 80 MeV/mg/cm² at ambient & high temperature SEU hardened DFF s Tested up to 300 krads. Radiation Level is 100 krads. Status : Design completed Digital & Analog Test Vehicles available Electrical characterization, Radiation and reliability tests in progress Alpha tests by TAS: circuit with analog blocks under design 12

13 FPGA from ATMEL ATF280F Main features : SRAM-based FPGA 280K equivalent ASIC gates 14,400 cells ( two 3-input LUT or one 4-input LUT, one DFF) Unlimited reprogrammability No SEL at a LET of 80 MeV/mg/cm2 SEE-hardened (Configuration RAM, FreeRAM, DFF, JTAG, I/O buffers) RHBD no need for mitigation techniques during design 300 krads MQFP-256/352, MCGA-472, LGA µm CMOS techno (F) Status: Design completed IDS Tools Release 9.1.2a available ESCC evaluation tests completed under ESA contract. SMD number : ATFS450E Joint ATMEL and HIREC development with CNES and JAXA respective support Based on the ATMEL AT40K FPGA architecture and HIREC radiation hardening by design techniques Target specification: SEU/SET hardened SRAM based reprogrammable FPGA 450K equivalent ASIC gates organized in an array of 152x152 core cells SEE-hardened (Configuration RAM, FreeRAM, DFF, JTAG, I/O buffers) RHBD no need for mitigation techniques during design 100 krads Lapis 0.15μm SOI (J) Status: Design completed 3rd silicon prototypes available Electrical characterization in progress : some bugs have been discovered on configuration memory readback. Feasibility of a silicon fix on-going Reliability tests for Electro Migration and Stress Migration on going on Lapis 0.15µm SOI TC 13

14 VLSI from ATMEL LEON2 AT697F µp Dvlpt Supported by ESA and ESCC eval supported by CNES Main features : 32-BIT SPARC PROCESSOR 1 W at 100 MHz Fault Tolerance by Design 86 MIPS (Dhrystone 2.1) 23 MFLOPS (Whetstone) 300 krads SEU error rate better than 1 E-5 error/device/da No SEL below a LETth of 70 MeV.cm2/mg MQFP256 and LGA349 packages 0.18µm CMOS techno (F) Status : ESCC evaluation completed in November 2011 : All results are satisfactory ESCC Detail Specification No. 9512/004 approved Products listed in EPPL 40Mb Asynchronous SRAM Target specification : 2 config : 4Mbx10b or 1Mbx40b with no embedded EDAC 2 options core: 1.2V std speed and 1.4V high speed. 3.3V IOs Packages: x10bit in FP42 (tbc), x40bit in CQFP132 UMC 90nm Low Leakage CMOS technology (TW) Status : 1st silicon available (x40bit 1.2V version) Electrical characterization have shown some bugs at IOs level Design fix under investigation 2nd Si expected in Q2/13 14

15 VLSI MODULES from ATMEL Reprogrammable FPGA module 2 FPGA ATF280F + 2 EEPROM AT69170E in one package Reprogrammable Computer : 1 FPGA ATF280F + 1 LEON2 AT697F in one package Atmel Reprogrammable FPGA module : open package Main features: 2x ATF280F FPGA + 2x AT69170E MQFP352 package 0.18µm CMOS techno (F) Status: Design completed Electrical Characterization Completed targeted spec reached Prototypes, Starter Kit, User guide and Application Note are available Atmel Reprogrammable computer : open package Main features: 32-bit SPARC V8 with Embedded FPGA MQFP352 package 0.18µm CMOS techno (F) Status: Design completed Electrical Characterization Completed targeted spec reached Prototypes, Starter Kit, User guide and Application Note are available ESCC evaluation in progress end Q3/13 15

16 HIGH SPEED CONVERTERS from E2V EV10AS180 ADC Dvlpt. in the frame of ESA program and ESCC eval in the frame of European Community's (CNES within FP7 consortium) ADC Main Features : 10-bit resolution 1.5 Gsps Conversion Rate LBand Selectable 1:1/2/4 DEMUX 1.7 W Power Dissipation 100 krads CI-CGA255 Package B7HF200 SiGeC techno. from Infineon (G) Status : Design Completed Reach target spec. ESCC evaluation in progress end Q4/12 EV12DS130 MUX-DAC Dvpt. and ESCC eval. in the frame of CNES program DAC Main Features : 12-bit resolution 3 Gsps Conversion rate 6 GHz analog output bandwidth 4:1 or 2:1 built in MUX (selectable) 1.3 W Power Dissipation NRZ, Narrow RTZ, 50% RTZ, RF modes 100 krads Ci-CGA255 Package B7HF200 SiGeC techno. from Infineon (G) Status : Design completed Very good performances ESCC evaluation completed in Sept.12 : very good reliability and radiation results, see next slides EPPL submission in Q4/12 16

17 STANDARD INTEGRATED CIRCUITS from STMicroelectronics / Completed activities ADC RHF1201 RHF1401 VCHX # bit Fs V CC Msps 2.5V Msps 2.5V fonction TID 16-bit Bus Buffer 16-bit bus transceiver 300 krads 16-bit D- type Latch 16-bit D- type Flip- Flop Power 100mW at 50Msps 85 mw at 20Msps SEL Immune up to 110 MeV-cm2/mg at 125 C TID SEL & SEFI SEU / SET Package Immune up to 120MeV-cm2/mg at 2.7V and 125 C SET immune for a LET 20MeV.cm²/mg SEU saturated cross-section = 3x10-4 cm²@ LET =60MeV.cm²/mg 300 krads KSO48 SET immune for a LET 116MeV.cm²/mg SEU saturated cross-section = 4x10-4cm²@ LET =116MeV.cm²/mg SEU/SET Package Techno SET immune up to a LET of 110 MeV.cm²/ mg FP µm CMOS SEU saturated crosssection = 1.2x10-5cm²@ LET =110MeV.cm²/mg Techno 0.25µm CMOS Products listed in EPPL 17

18 STANDARD INTEGRATED CIRCUITS from STMicroelectronics / Completed activities Opamps V CC I CC -3dB Bandwidth Slew Rate TID SEL SET RHF43B Precision 4 to 14V 2.3mA 2MHz, A V = V/µs SET saturated cross-section ~ 2,5x10-3cm², LETth < 3.3 MeV/mg/cm² RHF310 High-Speed 4.5 to 5.5V 400µA 120MHz, A V =+2 115V/µs 300 krads ELDRS free - Immune in Inverting config. -Very low sensitivity in Non- Inverting config.(σsat ~ 1E-6cm²). -Low sensitivity in Subtracting config.(σsat ~ 1E-5cm²). RHF330 High-Speed 4.5 to 5.5V 16.6mA 1 GHz, A V = V/μs Immune at 125 C, LET up to 110MeV.cm2/mg Low sensitivity in the three config. PWM Duty cycle V CC I CC TID SEL SET Package Techno ST % 50 krads 17 ma max Immune up to 120 MeV-cm²/mg at 30V, at 125 C SET saturated crosssection = 1x10-2cm², LETth = 1.5 MeV/mg/cm² Voltage regulator Output currents Output voltages TID SEL SET 15V FP8 Bipolar ST % 100 krads SET saturated crosssection = 9x10-3cm², LETth = 1.5 MeV/mg/cm² RHFL and 3 A 2.5 V, 3.3 V, 5.0 V 300 krads ELDRS free Immune LET up to 110MeV.cm²/mg SET sensitive Package FP8 Package FP16, SMD.5, TO-257 Techno Bipolar 0.25µm BiCMOS Techno Bipolar 18 Products listed in EPPL

19 STANDARD INTEGRATED CIRCUITS from STMicroelectronics / Dvpt & ESCC Evaluation in progress Fast Comparator Main features : Propagation time of 5 ns Rise/fall time: 1.4 ns on 10 pf Low consumption: 1.4 ma Single supply: 3 V to 5.5 V FP8 package ST 0.25µm BiCMOS techno (F) Status : Design completed Electrical Characterization Completed Very good Electrical Results Radiation Test in progress ESCC evaluation in progress end Q2/13. Voltage reference Main features : Reference voltage = 1.2V High Precision: ± 25 C Low Tempco:< 30ppm/ C FP10 package ST 0.25µm BiCMOS techno (F) Status : Design completed Electrical Characterization Completed Very good Electrical Results Radiation Test in progress ESCC evaluation in progress end Q2/13. Differential amplifier Target specification : Slew rate: 780 V/μs min. Input voltage noise: 2.8 nv/ Hz High input impedance 4.5V to 5.5V power supply range Rad-hard Status : Design in progress on 0.25µm BiCMOS techno (F) Si expected in Q2/13 16 bit DAC Target specification : 16-bit resolution at 5kHz bandwidth 20-bit resolution at 250Hz bandwidth 3.3 V analog supply Rad-hard Status : Design in progress on 0.13µm CMOS techno (F) Si expected in Q1/13 19

20 COMPONENTS DEVELOPMENT PROGRAM AT CNES OUTLINE DEVELOPMENT AND SPACE EVALUATION FLOW VLSI & ASIC TECHNOLOGIES DEVELOPMENT AND EVALUATION PROGRESS REPORT DSM TECHNOLOGIES RELIABILITY AND RADIATION TESTS RESULTS FUTURE CHALLENGES CONCLUSION 20

21 65NM EVALUATION TEST PROGRAM Evaluation Test Plan : Representative Test chips manufacturing of ST CMOS065LP Space platform Test chips Electrical characterization in -55 C/+125 C temperature range Construction analysis on TC1 Reliability tests to confirm life time of 20 Tj=110 C with temperature & voltage accelerations on TC1, TC2 & TC4 Radiation tests : TID, SEE under heavy ions and protons on TC1 and TC2 TC1 (Rad hard digital libraries): TC2 (Rad-hard PLL + cold spare IOs) TC4 (commercial library subset): 21

22 65NM RELIABILITY TESTS RESULTS First reliability results on TC4 test vehicle HTOL in progress on RH TC1 & TC2 test chips Several tests were performed on TC4 Standard Foundry qualification FIT calculations Vddnom, 125 C and 3x77 parts for criteria. 65nm TC HTOL trials results : Acceleration factors were confirmed For SRAM arrays, it is shown that all compilers remain stable with margins with respect to the specifications even after 20yrs/110 C. EOL Vddmin values are showing 200mV margins with respect to compiler spec. ST CMOS065LP CORE items are all passing SPACE mission profile Experimental SRAM Vddmin drifts and absolute Vddmin value at End-Of-Life 20yrs. 22

23 65NM RADIATION TESTS RESULTS Assessment phase : Heavy ions tests performed on a test vehicle with many mitigation schemes : 2 FFs architectures retained ECC confirmed robust and needed RAD tolerant Clock Trees SEU rate improvement factor with SKYROB ranging from 80 to 500 ST Clock Trees mitigation techniques in FF shifters ESCC evaluation phase : Heavy ions and Protons tests on TC1 test chip with rad-hard library to confirm previous data Test campaign in Q3/12 Test results under analysis 23

24 EV12DS130A DAC RELIABILITY TESTS RESULTS HTOL 3000Hrs on 15 devices at Tj 156 C Test results :» No parametric drift at Ambient, Low and High temperatures» EV12DS130AMGS9NB1 product has passed with success 3000Hrs life test (Tj 156 C) Drift 0Hrs Hrs Drift Part_ID:21 Relative deviation limit IVCCA5_Mux4:1 Alim Max 85 ma ±5% -0,58% IVCCA3_Mux4:1 Alim Max 86 ma -5% -0,50% IVCCD_Mux4:1_Alim Max 87 ma -5% -0,78% FullScale_GA_Typ 112 v -1% -0,61% VOL_STVF 200 v -5% 0,19% VOH_STVF 202 v -5% -0,15% Drift calculation after 3000hrs HTOL on 1 part Construction analysis : No defect after visual inspection and SEM cross-section at package and die levels :» Pull test and Ball shear test results were in spec. limits» Good aspect of SiGeC process Package tests : Test conditions :»500 x (-65 C / C) Temp. Cycling Thermal shock on 5 parts»50 Mechanical shock (1500g)+ 120 vibration (20g) on 5 parts Test results :»No parametric drift. Seal test OK»No assembly degradation : Pull test and Ball shear test results were in spec. limits» Qualification of ball bonding process 24 E2V EV12DS130A : open package Infineon SiGeC B7HF200 technology cross-section

25 EV12DS130A DAC RADIATION TESTS RESULTS : TID TID according to ESCC parts dynamically biased + 5 parts unbiased + Reference part 36 rad/h up to 110Krad 25 C anneal under bias during 24 hours after completion of irradiation accelerated ageing under bias (100 C for 168 hours) Parameters monitored : Supply currents, leakage on static inputs Level of harmonics H1, H2, H3, Fclk/4-Fout and in RF mode E2V EV12DS130A - Current consumption versus TID TID test results : No failure nor parameter drift up to 110 Krad (Si) at low dose rate of 36 rad/h 25

26 EV12DS130A DAC RADIATION TESTS RESULTS : HEAVY IONS SEE tests according to ESCC25100 No SEL observed up to a LET of 80MeV.cm²/mg at Tj=125 C No SEFI detected SET observed from LET 1.1 to 67.7 MeV.cm²/mg Only short duration transient on DSPCLK Different behaviors can be observed on DACOUT: Long duration transient for LET>31 MeV.cm²/mg» = successive erroneous conversion» Worst case transient duration is 100ns max» Periodicity not affected, but smooth variation of DACOUT amplitude: Short duration transient. See Fig.1: Worst case duration of ~20ns max. Same worst case Weibull curve can be applied on DSPCLK & DACOUT curves for all modes GEO Quiet Active CREME M3 CREME M8 Complete mission 15 years 16 days Rate/day 1.00E E E-02 MTBF (days) Heavy Ion SEE Rate calculation with OMERE (DACOUT & DSPCLK) Long SET DACOUT, NRTZ mode, 2760MS/s, LET=31MeV.cm²/mg 53 Heavy Ion DSPCLK SET cross section for all configurations 26

27 EV12DS130A DAC RADIATION TESTS RESULTS : PROTONS SEE tests according to ESCC25100 No SEL and no SEFI detected up to 200 MeV Very few events detected even if the device appears to be sensitive down to 20 MeV Worst case Weibull parameter is considered Same behavior on DSPCLK & DACOUT DSPCLK events: only slight variation of 1 period or glitches DACOUT events: only very short transients of ~ 2 to 3 ns DACOUT DSPCLK Saturation cross 1.50E E-10 section (cm²) E th (MeV) 1 1 S 1 1 W (MeV) 1 1 Protons Worst case Weibull parameters Rate/day MTBF (days) GEO Quiet CREME M3 15 years 0.00E+00 Active CREME M8 16 days 3.30E-01 3 Complete mission 9.64E Proton SEE Rate calculation with OMERE (DACOUT & DSPCLK) 27 Protons SET DACOUT cross section, all modes Protons SET DSPCLK cross section,all modes

28 COMPONENTS DEVELOPMENT PROGRAM AT CNES DEVELOPMENT AND SPACE EVALUATION FLOW VLSI & ASIC TECHNOLOGIES DEVELOPMENT AND EVALUATION PROGRESS REPORT DSM TECHNOLOGIES RELIABILITY AND RADIATION TESTS RESULTS FUTURE CHALLENGES CONCLUSION 28

29 FUTURE CHALLENGES Atmel 2.5Mg RH SRAM based FPGA : To Develop an Mg SRAM based reprogrammable FPGA Process : ST CMOS65LP (F) Architecture: NanoXplore Target specification : FRANCE SRAM-based FPGA 2.5M equivalent ASIC gates 324 clusters, LUT 5 832Kb RAM Unlimited reprogrammability RHBD no need for mitigation techniques during design Radiation performance:» SEL free for a LET of C junction,» No configuration memory upset up to 100 MeV/mg/cm²» SEU and SET susceptibility higher than a LET of 40 MeV/mg/cm².» 300Krads Packages: FlipChip and Highly Dissipative Hermetic Ceramic Package up to 2000 GERMANY Status : CNES contract launched for the development of the first prototype. Project duration: 27 months Complementary ESA contracts for Hardware and Software will start in Q4/12 29

30 FUTURE CHALLENGES Flip-Chip package for space : To develop and evaluate Flip-Chip capability for 65nm digital components & ASIC Investment by French government initiative : KO in Q3/12 After 65nm : Process to be selected Radiation and Reliability capabilities to be assessed versus space requirements 30

31 COMPONENTS DEVELOPMENT PROGRAM AT CNES DEVELOPMENT AND SPACE EVALUATION FLOW VLSI & ASIC TECHNOLOGIES DEVELOPMENT AND EVALUATION PROGRESS REPORT DSM TECHNOLOGIES RELIABILITY AND RADIATION TESTS RESULTS FUTURE CHALLENGES CONCLUSION 31

32 CONCLUSION CNES contribution to European Components Initiative for 7 years up to now Many activities in different technological domains Good collaboration/coordination : within the CTB and between CNES and ESA with JAXA (FPGA 450Kgates on LAPIS 150nm SOI CMOS process) A step forward to make available the future components necessary to improve the competitiveness of the European space industry in the international market. 32

33 ACKNOWLEDGEMENTS Marketing & Business Development Manager Atmel Space Data converters Project Manager E2V Space BU Manager STMicroelectronics CMOS065LP Space Program Manager STMicroelectronics 33