Rad-hard 16-bit transceiver 3.3 V to 5 V bidirectional level shifter. Description. Parameter RHRAC164245K1 RHRAC164245K01V

Transcription

1 Rad-hard 16-bit transceiver to bidirectional level shifter Datasheet - production data Features Fully compatible with 54ACS Dual supply bidirectional level shifter Extended voltage range from 2.3 V to 5. Separated enable pin for 3-state output Schmidt-triggered I/Os: 100 mv hysteresis Internal 26 Ω limiting resistor on each I/O High speed: Tpd = 8 ns maximum Fail safe Cold spare Hermetic package 100 krad (Si) at any Mil1019 dose rate SEL immune to 110 MeV.cm 2 /mg LET ions RHA QML-V qualified Description The 54AC is a rad-hard advanced highspeed CMOS, Schmitt trigger, 16-bit, bidirectional, multi-purpose transceiver with 3- state outputs and cold sparing. Designed for use as an interface between a bus and a bus in mixed / supply systems, it achieves high-speed operation while maintaining the CMOS low-power dissipation. All pins have cold spare buffers to change them to high impedance when VDD is tied to ground. This IC is intended for two-way asynchronous communication between the data buses. The direction of the data transmission is determined by the ndir inputs. The A port interfaces with the bus but can also operate at 2.3 V. The B port operates with the bus. Table 1: Device summary Parameter RHRAC164245K1 RHRAC164245K01V SMD 5962R VYC Quality level Package Lead finish Mass Engineering model Flat-48 Gold 1.50 g QML-V flight EPPL (1) Yes Temp. range Notes: (1) EPPL = ESA preferred part list -55 C to 125 C May 2017 DocID18093 Rev 8 1/25 This is information on a product in full production.

2 Contents 54AC Contents 1 Functional description Cold spare Power-up Pin connections Absolute maximum ratings and operating conditions Electrical characteristics Radiations Test circuit Package information Ceramic Flat-48 package information Ordering information Other information Data code Documentation Revision history /25 DocID18093 Rev 8

3 Functional description 1 Functional description Figure 1: Logic diagram DIR1 OE1 DIR2 OE2 1A1 2A1 1B1 2B1 1A2 2A2 1B2 2B2 1A3 2A3 1B3 2B3 1A4 2A4 po rt 1B4 po rt 2B4 1A5 po rt 2A5 po rt 1B5 2B5 1A6 2A6 1B6 2B6 1A7 2A7 1B7 2B7 1A8 2A8 1B8 2B8 Table 2: Function table Enable, OEx Direction, DIRx Operation L B data to A bus L H A data to B bus H X Isolation DocID18093 Rev 8 3/25

4 Functional description 1.1 Cold spare 54AC The 54AC features a cold spare input and output buffer. In high reliability applications, cold sparing enables a redundant device to be tied to the data bus with its power supply at 0 V (VDD = VSS = 0 V, VDD - VSS = 0 V) without affecting the bus signals or injecting current from the I/Os to the power supplies. Cold sparing also allows redundant devices that are not powered to be switched on only when required. Power consumption is therefore reduced by switching off the redundant circuit. This has no impact on the application. Cold sparing is achieved by implementing a high impedance between I/Os and VDD. The ESD protection is ensured through a non-conventional dedicated structure. Using cold spare on Bus A and Bus B separately is not allowed. In cold spare, both VDD1 and VDD2 must be at 0 V. Figure 2: Cold spare and cold redundancy 1. R = Ioff/VDD 4/25 DocID18093 Rev 8

5 1.2 Power-up Functional description During power-up, all outputs are forced to high impedance. The high-impedance state is maintained approximately until VDD is high, thus avoiding any transient and erroneous signals during power-up. However, the 54AC must be supplied with VDD1 (VCCB) higher or equal to VDD2 (VCCA). Figure 3: Power-up 1. In operating mode, VDD1 (VCCB) must be higher than or equal to VDD2 (VCCA). VDD2 higher than VDD1 is forbidden. 2. In power-up, VDD1 (VCCB) must be powered up before VDD2 (VCCA). 3. In power-down, VDD2 (VCCA) must be powered down before VDD1 (VCCB). DocID18093 Rev 8 5/25

6 Functional description 1.3 Pin connections Figure 4: Pin connections 54AC Table 3: Pin descriptions Pin number Symbol Name and function 1 DIR1 Direction control inputs 2, 3, 5, 6, 8, 9, 11, 12 1B1 to 1B8 Side B inputs or 3-state outputs ( port) 4,10, 15, 21, 28, 34, 39, 4SS Reference voltage to ground 7, 18 VDD1 Supply voltage () 13, 14, 16, 17, 19, 20, 22, 23 2B1 to 2B8 Side B inputs or 3-state outputs ( port) 24 DIR2 Direction control inputs 25 ng2 Output enable inputs (active low) 31, 42 VDD2 Supply voltage () 47, 46, 44, 43, 41, 40, 38, 37 1A1 to 1A8 Side A inputs or 3-state outputs ( port) 36, 35, 33, 32, 30, 29, 27, 26 2A1 to 2A8 Side A inputs or 3-state outputs ( port) 48 ng1 Output enable inputs (active low) 6/25 DocID18093 Rev 8

7 Absolute maximum ratings and operating conditions 2 Absolute maximum ratings and operating conditions Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Unless otherwise noted, all voltages are referenced to VSS. The limits for the parameters specified in Table 4: "Absolute maximum ratings" apply over the full specified VDD range and case temperature range of -55 C to 125 C. Table 4: Absolute maximum ratings Symbol Parameter Value Unit VDD1 supply voltage (1) VDD2 VIA VIB VOA VOB IIA IIB 3 V supply voltage DC input voltage range port A DC input voltage range port B DC output voltage range port A DC output voltage range port B DC input currents port A, anyone input DC input currents port B, anyone input -0.3 to to VDD V Tstg Storage temperature range -65 to 150 TL Lead temperature (10 s) 300 TJ Junction temperature range 175 V ± 10 ma Rthjc Thermal resistance junction to case (2) 8 C/W ESD HBM: human body model (3) 2 kv Notes: (1) VDD1 must be higher or equal to VDD2 (VDD2 higher than VDD1 is forbidden). (2) Short-circuits can cause excessive heating and destructive dissipation. Values are typical. (3) Human body model: a 100 pf capacitor is charged to the specified voltage, then discharged through a 1.5 kω resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. C In Table 5: "Operating conditions", unless otherwise noted, all voltages are referenced to VSS. Table 5: Operating conditions Symbol Parameter Value Unit VDD1 VDD2 VI VO Supply voltage (1) Input voltage Output voltage 4.5 to 5.5 or 2.3 to to 3.6 or 4.5 to to VDD1 V DocID18093 Rev 8 7/25

8 Absolute maximum ratings and operating conditions 54AC Symbol Parameter Value Unit Top Operating temperature -55 to 125 C dt / dv Input rise and fall time VCC = 3.0, 4.5 or 5.5 (2) 0 to 8 ns / V Notes: (1) VDD1 must be higher or equal to VDD2 (VDD2 higher than VDD1 is forbidden). (2) Derates system propagation delays by difference in rise time to switch point for tr or tf > 1 ns/v. 8/25 DocID18093 Rev 8

9 Electrical characteristics 3 Electrical characteristics Symbol VT+ In the table below, Top = -55 C to 125 C, VDD1 = 4. to 5., to 3.6 V, unless otherwise specified. Each input/output, as applicable, is tested at the specified temperature, for the specified limits, according to the tests specified in TABLE IA from the SMD DLA Agency Spec. Non-designated output terminals are high-level logic, low-level logic or open, except for all IDD tests, where the output terminals are open. When performing these tests, the current meter must be placed in the circuit so that all current flows through the meter. Parameter Schmitt trigger positive going threshold port A Schmitt trigger positive going threshold port B Port voltage Table 6: DC specifications Test condition (VDD) (1) VDD1 = 4.5 and 5. VDD2 = 2.7 and 3.6 V VDD1 = 4.5 and 5. VDD2 = 4.5 and 5. VDD2 = 2.7 and 3.6 V VDD1 = 2.7 and 3.6 V VDD1 = 4.5 and 5. VDD2 = 2.7 and 3.6 V Min. Limits Max. 0.7 VDD2 0.7 VDD1 Unit VT- Schmitt trigger positive going threshold port A Schmitt trigger positive going threshold port B VDD1 = 4.5 and 5. VDD2 = 2.7 and 3.6 V VDD1 = 4.5 and 5. VDD2 = 4.5 and 5. VDD2 = 2.7 and 3.6 V VDD1 = 2.7 and 3.6 V VDD1 = 4.5 and 5. VDD2 = 2.7 and 3.6 V 0.3 VDD2 0.3 VDD1 V VH Schmitt trigger range of hysteresis port A Schmitt trigger range of hysteresis port B VDD1 = 4.5 and 5. VDD2 = 2.7 and 3.6 V VDD1 = 4.5 and 5. VDD2 = 4.5 and 5. VDD2 = 2.7 and 3.6 V VDD1 = 2.7 and 3.6 V VDD1 = 4.5 and 5. VDD2 = 2.7 and 3.6 V IIH Input current high port A (for input under test VI = VDD2 other inputs, VI = VDD2 or VSS) VDD1 = 5. VDD2 = 3.6 V VDD1 = 5. 3 µa DocID18093 Rev 8 9/25

10 Electrical characteristics 54AC Symbol Parameter Port voltage Test condition (VDD) (1) Limits Min. Max. Unit VDD2 = 5. Input current high port B (for input under test VI = VDD1 other inputs, VI = VDD1 or VSS) VDD1 = 3.6 V VDD2 = 3.6 V VDD1 = 5. VDD2 = 3.6 V IIL Input current low port A (for input under test VI = VSS other inputs, VI = VDD2 or VSS) Input current low port B (for input under test VI = VSS other inputs, VI = VDD1 or VSS) VDD1 = 5. VDD2 = 3.6 V VDD1 = 5. VDD2 = 5. VDD1 = 3.6 V VDD2 = 3.6 V VDD1 = 5. VDD2 = 3.6 V -1 Input current cold spare mode port A = port B = 5. = VI DIRn = 5., OEn = 5. ICS Input current cold spare mode port A = port B = 5. = VI DIRn = 0V, OEn = 5. Input current cold spare mode port A = port B = 5. = VI DIRn = 5., OEn = 0 V Input current cold spare mode port A = port B = 5. = VI DIRn = 0 V, OEn = 0 V VDD1 = 0 V -1 5 VOL1 Low level output voltage port A, IOL = 8 ma for all inputs affecting output under test, VI = VDD2 or VSS Low level output voltage port B, IOL = 8 ma for all inputs affecting output under test, VI = VDD1 or VSS VDD1 = 4. VDD1 = 4. VDD2 = 4. VDD1 = 2.7 V VDD1 = V VOL2 Low level output voltage Port A, IOL = 100 µa for all inputs affecting output under test, VI = VDD2 or VSS VDD1 = 4. VDD1 = 4. VDD2 = V 10/25 DocID18093 Rev 8

11 Symbol VOH1 VOH2 IOL (2) IOH (3) Parameter Low level output voltage Port B, IOL = 100 µa for all inputs affecting output under test, VI = VDD1 or VSS High level output voltage port A, IOH = -8 ma for all inputs affecting output under test, VI = VDD2 or VSS High level output voltage port B, IOH = -8 ma for all inputs affecting output under test, VI = VDD1 or VSS High level output voltage port A, IOH = µa for all inputs affecting output under test, VI = VDD2 or VSS High level output voltage port B, IOH = µa for all inputs affecting output under test, VI = VDD1 or VSS Output current (sink) port A, VI = VSS Output current (sink) port B, VI = VSS Output current (source) port A, VI = VDD2 or VSS Port voltage Test condition (VDD) (1) VDD1 = 2.7 V VDD1 = 4. VDD1 = 4. VDD1 = 4. VDD2 = 4. VDD1 = 2.7 V VDD1 = 4. VDD1 = 4. VDD1 = 4. VDD2 = 4. VDD1 = 2.7 V VDD1 = 4. VDD1 = 4. VOL = 0. VDD1 = 4. VDD2 = 4. VOL = 0.4 V VDD1 = 2.7 V VOL = 0. VDD1 = 4. VOL = 0.4 V VDD1 = 4. VOH = VDD2-0.9 V VDD1 = 4. Electrical characteristics Min. VDD2-0.9 VDD2-0.7 VDD1-0.9 VDD1-0.7 VDD2-0.2 VDD Limits Max. Unit ma DocID18093 Rev 8 11/25

12 Electrical characteristics 54AC Symbol Parameter Port voltage Test condition (VDD) (1) Limits Min. Max. Unit VDD2 = 4. VOH = VDD2-0.7 V VDD1 = 2.7 V 3 V Output current (source) port B, VI = VDD2 or VSS VOH = VDD2-0.9 V VDD1 = 4. VOH = VDD2-0.7 V Three-state output leakage current high port A, for input under test, VI = VDD2 other inputs, VO = VDD2 VI = VDD2 or VDD1 = 5. VDD2 = 3.6 V VDD1 = 5. IOZH VSS Three-state output leakage current high port B, for input under test, VI = VDD1 other inputs, VO = VDD1 VI = VDD1 or VSS VDD2 = 5. VDD1 = 3.6 V VDD2 = 3.6 V VDD1 = 5. VDD2 = 3.6 V 3.0 µa IOZL Three-state output leakage current low port A, for input under test, VI = VSS other inputs, VO = VSS VI = VDD2 or VSS Three-state output leakage current low port B, for input under test, VI = VSS other inputs, VO = VSS VI = VDD1 or VSS VDD1 = 5. VDD2 = 3.6 V VDD1 = 5. VDD2 = 5. VDD1 = 3.6 V VDD2 = 3.6 V VDD1 = 5. VDD2 = 3.6 V -1.0 µa IOS (4) Short circuit output current port A, VO = VDD2 or VSS Short circuit output current port B, VO = VDD1 or VSS VDD1 = 4.5 to 5. VDD1 = 4.5 to 5. VDD2 = 4.5 to 5. VDD1 = 2.7 to VDD1 = 4.5 to ma PD (3)(4)(5) Power dissipation, port A, CL = 50 pf per switching output VDD1 = 4.5 to 5. VDD1 = 4.5 to 5. VDD2 = 4.5 to mw/ MHz 12/25 DocID18093 Rev 8

13 Symbol IDDQ Parameter Power dissipation, port B, CL = 50 pf per switching output Quiescent supply current port A, VI = VDD2 or VSS Quiescent supply current port B, VI = VDD1 or VSS Port voltage Test condition (VDD) (1) VDD1 = 2.7 to VDD1 = 4.5 to 5. VDD1 = 5. at 25 C VDD2 = 5. at 25 C VDD1 = 5. at -55 to 125 C VDD2 = 5. at -55 to 125 C VDD1 = 5. at 25 C VDD2 = 5. at 25 C VDD1 = 5. at -55 to 125 C VDD2 = 5. at -55 to 125 C CI Input capacitance f = 1 MHz VDD1 = VDD2 = 0 V CO Output capacitance f = 1 MHz VDD1 = VDD2 = 0 V (6) Functional test VIH = 0.7 VDD, Notes: VIL = 0.3 VDD VDD1 = 4.5 to 5. Electrical characteristics Min. L Limits Max Unit µa 15 pf (1) This device requires both VDD1 and VDD2 power supplies for operation. The power supply is indicated and followed by the voltage to which the power supply is set to the given test (2) This parameter is supplied as a design limit but not guaranteed or tested (3) Power does not include power contribution of any CMOS output sink current (4) No more than one output should be shorted at a time for a maximum duration of one second (5) Power dissipation specified per switching output (6) Tests must be performed in sequence and include attribute data only. Functional tests should include the truth table and other logic patterns used for fault detection. The test vectors used to verify the truth table must, at the minimum, test all the functions of each input and output. All possible input to output logic patterns per function should be guaranteed, if not tested, to the function table, Table 2. Functional tests are performed in sequence as approved by the qualifying activity on qualified devices. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min + 20%, -0%); VIL = VIL(max + 0%, -50%), as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices are guaranteed to VIH(min) and VIL(max). H In the table below, data are guaranteed by design but, not tested. Table 7: AC electrical characteristics Symbol Parameter Port voltage Test condition (VDD) tplh Propagation delay time, data to bus (active low) CL = 50 pf Port A =, Port B = Port A = Port B = VDD1 = 4.5 to 5. VDD1 = 2.7 to 3.6 V Limits Min. Max. 1.0 Port A = Port B = VDD1 = 4.5 to Unit ns DocID18093 Rev 8 13/25

14 Electrical characteristics Symbol Parameter Port voltage Test condition (VDD) tphl tpzl tpzh tplz tphz tpzl Propagation delay time, data to bus (active high) CL = 50 pf Propagation delay time, output enable, OEn to bus (active low), CL = 50 pf Propagation delay time, output enable, OEn to bus (active high), CL = 50 pf Propagation delay time, output disable, OEn to bus (low impedance), CL = 50 pf Propagation delay time, output disable, OEn to bus (high impedance), CL = 50 pf Propagation delay time, output enable, DIRn to bus (active low), CL = 50 pf Port A =, Port B = Port A = Port B = Port A = Port B = Port A =, Port B = Port A = Port B = Port A = Port B = Port A =, Port B = Port A = Port B = Port A = Port B = Port A =, Port B = Port A = Port B = Port A = Port B = Port A =, Port B = Port A = Port B = Port A = Port B = Port A =, Port B = Port A = Port B = VDD2 = 4.5 to 5. VDD1 = 4.5 to 5. VDD1 = 2.7 to 3.6 V VDD1 = 4.5 to 5. VDD2 = 4.5 to 5. VDD1 = 4.5 to 5. VDD1 = 2.7 to 3.6 V VDD1 = 4.5 to 5. VDD2 = 4.5 to 5. VDD1 = 4.5 to 5. VDD1 = 2.7 to 3.6 V VDD1 = 4.5 to 5. VDD2 = 4.5 to 5. VDD1 = 4.5 to 5. VDD1 = 2.7 to 3.6 V VDD1 = 4.5 to 5. VDD2 = 4.5 to 5. VDD1 = 4.5 to 5. VDD2 = 2.7 to VDD1 = 2.7 to VDD2 = 2.7 to VDD1 = 4.5 to 5. VDD2 = 4.5 to 5. VDD1 = 4.5 to 5. VDD2 = 2.7 to VDD1 = 2.7 to VDD2 = 2.7 to Min AC Limits Max. Port A = Port B = VDD1 = 4.5 to Unit ns 14/25 DocID18093 Rev 8

15 Symbol Parameter Port voltage Test condition (VDD) tpzh tplz tphz Propagation delay time, output enable, DIRn to bus (active high), CL = 50 pf Propagation delay time, output disable, DIRn to bus (low impedance), CL =50 pf Propagation delay time, output disable, DIRn to bus (high impedance), CL =50 pf Port A =, Port B = Port A = Port B = Port A = Port B = Port A =, Port B = Port A = Port B = Port A = Port B = Port A =, Port B = Port A = Port B = Port A = Port B = VDD2 = 4.5 to 5. VDD1 = 4.5 to 5. VDD2 = 2.7 to VDD1 = 2.7 to VDD2 = 2.7 to VDD1 = 4.5 to 5. VDD2 = 4.5 to 5. VDD1 = 4.5 to 5. VDD2 = 2.7 to VDD1 = 2.7 to VDD2 = 2.7 to VDD1 = 4.5 to 5. VDD2 = 4.5 to 5. VDD1 = 4.5 to 5. VDD2 = 2.7 to VDD1 = 2.7 to VDD2 = 2.7 to VDD1 = 4.5 to 5. VDD2 = 4.5 to 5. Electrical characteristics Min. Limits Max Unit DocID18093 Rev 8 15/25

16 Radiations 54AC Radiations Total dose (Mil1019 dose rate): all parameters are post-irradiation guaranteed by wafer-lot acceptance (after dose, all guaranteed electrical parameters are tested on a sample of units of each wafer lot). All parameters provided in Table 6 and Table 7 apply to both pre- and post-irradiation. The 54AC is a pure CMOS product. Irradiation is performed at high dose rates. Heavy ions: the behavior of the product when submitted to heavy ions is guaranteed by qualification and is not tested in production. Heavy-ion trials are performed on qualification lots only. Table 8: Radiations Type Features Value Unit TID Total ionizing dose, high-dose rate ( rad/sec) up to: 100 krad Heavy ions SEL immune (at 125 C) up to: 110 MeV.cm²/m SEU immune up to: 64 g 16/25 DocID18093 Rev 8

17 Test circuit 5 Test circuit Figure 5: Test circuit V CC D 1 D 3 PULSE GENERATOR D.U.T I SNK R T C L D 2 D 4 V REF I SRC 1. CL = 50 pf or equivalent (includes jig and probe capacitance), RT = ZOUT of pulse generator (typically 50 Ω ), VREF = 0.DD. ISRC is set to -1.0 ma and ISNK is set to 1.0 ma for tphl and tplh measurements. Input signal from pulse generator: VI = 0.0 V to VDD; f = 10 MHz; tr = 1.0 V/ns "0.3 V/ns; tf = 1.0 V/ns "0.3 V/ns; tr and tf are measured from 0.1 VDD to 0.9 VDD and from 0.9 VDD to 0.1 VDD respectively. Figure 6: Waveform 1: propagation delay t r t f INPUT 90% 50% 10% V DD GND t PLH t PHL V OH OUTPUT 50% 50% V OL DocID18093 Rev 8 17/25

18 Test circuit Figure 7: Waveform 2: enable and disable times (port A = port B, operation) 54AC V DD INPUT 50% 50% 0 V t PZL t PLZ 50% V DD % V DD OUTPUT 0.2 V DD +0.2 V 0.2 V DD t PZH t PHZ OUTPUT 80% V DD 80% V DD -0.2 V 50% V DD % V DD Figure 8: Waveform 3: enable and disable times (port A = port B, operation) 18/25 DocID18093 Rev 8

19 Figure 9: Waveform 4: enable and disable times (port A =, port B = ) Test circuit V DD INPUT 50% 50% 0 V t PZL t PLZ 50% V DD % V DD OUTPUT 0.2 V DD +0.2 V 0.2 V DD t PZH t PHZ OUTPUT 80% V DD 80% V DD -0.2 V 50% V DD % V DD t PZL t PLZ 50% V DD % V DD OUTPUT 0.2 V DD +0.2 V 0.2 V DD t PZH t PHZ OUTPUT 70% V DD 70% V DD -0.2 V 50% V DD % V DD DocID18093 Rev 8 19/25

20 Package information 54AC Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. 20/25 DocID18093 Rev 8

21 6.1 Ceramic Flat-48 package information Figure 10: Ceramic Flat-48 package outline Package information Pin 1 identifier 48 e (N-2 places) D b (N places) S1 (4 places) L E L c A Q E3 E2 E3 f 1. The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the package. Connecting any unused pins or the metal lid to ground or to the power supply will not affect the electrical characteristics. Ref. Table 9: Ceramic Flat-48 mechanical data Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A b c D E E E e f L Q S DocID18093 Rev 8 21/25

22 Ordering information 54AC Ordering information Table 10: Order codes Order code Description Temp. range Package Marking Packing RHRAC164245K1 Engineering model RHRAC164245K1-55 C to 125 C Flat-48 RHRAC164245K01V QML-V flight 5962R VYC Conductive strip pack 22/25 DocID18093 Rev 8

23 Other information 8 Other information 8.1 Data code The date code is structured as shown below: EM xyywwz QML-V yywwz where: 8.2 Documentation Table 11: Documentation provided for ESCC flight Quality level Documentation Engineering model QML-V flight Certificate of conformance QCI (1) (groups A, B, C, D, and E) Screening electrical data Precap report PIND (2) test SEM (3) inspection report X-Ray report Notes: (1) QCI = quality conformance inspection (2) PIND = particle impact noise detection (3) SEM = scanning electron microscope DocID18093 Rev 8 23/25

24 Revision history 54AC Revision history Table 12: Document revision history Date Revision Changes 23-Sep Initial release. 06-Apr Added Pin 4 description to Table 3: "pin descriptions". 29-Aug Apr Jul Sep Jan May Minor changes to layout Features: removed Bus hold Table 1: updated order codes, quality level, and EPPL data. Table 10: "Order codes": updated order codes and description data. Added Section 8: "Other information" Table 11: "Documentation provided for ESCC flight": removed documentation for engineering model (there is none). Updated disclaimer Table 4: "Absolute maximum ratings": removed Rthja and updated Rthjc information respectively. Table 1: updated "RHFAC164245K1" with "RHRAC164245K1" and "RHFAC164245K01V" with "RHRAC164245K01V". Table 10: "Order codes": updated "RHFAC164245K1" with "RHRAC164245K1". Updated Section 1.1: "Cold spare" Updated Section 1.2: "Power-up" Table 4: "Absolute maximum ratings": updated VDD1/VDD2 value and updated footnote 1. Table 5: Operating conditions : added footnote 1 Updated Section 1.2: "Power-up" and footnote 1 in Table 5: "Operating conditions" 24/25 DocID18093 Rev 8

25 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved DocID18093 Rev 8 25/25