Optimizing LC VCO Performances Through a Heuristic

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Clemence Manning
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1 Optimizi LC VCO Performaces Throuh a Heuristic Natioal eieeri school of Sfax Uiversity of Sfax TUNISIA ibtihel.krout@ieee.or, hassee.mif@ieee.or, mourad.fakhfakh@ieee.or, mourad.loulou@ieee.or Abstract: - e propose a heuristic for the optimal sizi of LC VCO s. The heuristic is a alorithm drive methodoloy that allows us determii optimal sizes of iductors ad chael widths that miimizes the VCO s phase oise while satisfyi fixed costraits (maximum cosumed power, occupied area ). The proposed optimizatio methodoloy was applied to size a cross-coupled differetial voltae cotrolled oscillator. This latter, desied usi AMS 0.35 µm techoloy, achieves dbc/hz at 1MHz offset from a.6 GHz carrier frequecy with 8.m cosumptio power ad dbc/hz at 1MHz offset from a 5.4 GHz carrier frequecy with 8.0m cosumptio power. Key-ords: - LC-VCO, Heuristic, Phase oise. 1 Itroductio The iterated iductace-capacitace (LC) voltae-cotrolled oscillator (VCO) is a commo fuctioal block i moder radio frequecy commuicatio systems. It is oe of the mai blocks formi the frequecy sythesizer used to up ad dow covert sials. Due to the evolutio of wireless commuicatio system, a hih level of performaces must be esured by VCOs, maily their phase oise ad their power cosumptio. I fact, due to the evericreasi demad for badwidth, very striet requiremets are placed o the spectral purity of local oscillators [1]. Efforts to improve the phaseoise performace of iterated LC VCOs have resulted i a lare umber of realizatios. Despite these edeavors, VCO desi is still a complicated task sice multiple iterdepedet variables ad costats have to be hadled. Besides, the rowth of the telecommuicatio market imposes shortei the desi delay. I this cotext, computer-aided optimizatio techique usi eometric prorammi has bee used to efficietly fid the optimum desi for certai LC oscillator topoloies [], [3]. Despite its efficiecy, it provides limited physical isiht ito choosi the optimum desi. To overcome these limitatios, we propose a optimizatio methodoloy based i a physical stadpoit study that allows us optimally sizi compoets composi LC VCOs, i order to miimize the phase oise while satisfyi imposed costraits. The paper is oraized as follows: sectio II presets the cross coupled LC VCOs that was chose as a applicatio example for the proposed heuristic. Sectio III details costraits ad performace fuctio models that were take ito accout i the optimizatio alorithm. Sectio IV presets the proposed heuristic. Sectio V presets the simulatio results ad compares the performace of our VCO to that of other reported LC oscillators to prove the adequacy of our desi methodoloy. Fially, i sectio VI, we ive some cocludi remarks. LC VCO Descriptio he deali with hih frequecy applicatios, LC VCO circuits are preferred to other proposed oscillator structures, such as ri oscillators [4]. Differet structures of LC oscillators have bee already studied. The compariso preseted i [5] shows that cross-coupled differetial oscillator provides better oise performace tha NMOS cross-coupled oscillator. I fact, the cross-coupled LC-VCO offers better rise- ad falltime symmetry, which results i a smaller 1/f 3 oise corer [5]. I additio, the VCO bias curret must be doubled for the NMOS structure to obtai the same amplitude as i structure. Fi.1. presets a LC VCO circuit. This oscillator is maily composed of a resoator ISSN: Issue 6, Volume 5, Jue 008

2 formed by iductors L1 ad L ad capacitors C1 ad C. The double cross-coected NMOS (M1- M) ad PMOS (M3-M4) differetial pairs provide the eative resistace to compesate the loss [1]. The oscillatio frequecy rae is cotrolled throuh two MOS accumulatio varactors i series, C1 ad C. The accumulatio mode varactor provides hiher capacitace per uit area, better quality factor ad wider tui rae whe compared to reverse-biased PN juctio ad MOS depletio/iversio varactors [6]. Cload M3 M1 L1 C Vdd Vctrl L C1 Ibias M4 M Cload Fi.1.The cross coupled LC VCO circuit.1 Varactor equivalet model LC VCO preseted at fi. 1 comprises two varactors, C1 ad C. These MOS varactors ca be modeled with a capacitor C v i series with a parasitic resistor R sv [1]. The resistace R sv for the accumulatio mode is calculated with the eometric varactor parameters: chael width ( v ), chael leth (l chael ) ad fier umber (N ); ad with the sheet resistaces of the -well (R w, ) ad silicided polysilico ate layer (R poly, ) [7]. v 1 1 l N chael R = + sv R w, R poly, (1) 1 N v l chael N. Iductor equivalet model The VCO oscillatio frequecy ad resistive loss are hihly iflueced by parasitic elemets of the iductor. That s why we adopt i our study the symmetric π-model to describe the iductor (Fi.). I this model, R pl /C pl ad R sl /C sl are respectively the parallel ad series parasitic resistaces/capacitaces of the iductor. C PL L S R PL Fi.. Iductor π-model C SL R SL C PL R PL 3 Systems Costraits ad Performace Fuctios Formulatio I additio to iheret fuctioal costraits, such as amplitude, frequecy oscillatio, tui rae ad startup coditio, the desi of VCOs requires satisfyi some other costraits that are imposed by the applicatio. Three major costraits are commoly at the aim of iterest, i.e. phase oise, power cosumptio ad occupied area. Below, we preset these coditios ad costraits. Sice maximum autoomy is required for the emissio receptio trasceiver, miimizatio of cosumed power is ecessary. This leads to the limitatio of the circuit s bias curret (I bias ), thus: Ibias I max () where I max is the maximum bias curret that is determied by the maximum allowed cosumptio power. I order to provide a hih voltae swi, V, for the stae coected at the output of the VCO, a miimum value of the amplitude V,mi is fixed: V V,mi (3) The oscillatio tui rae of the LC VCO pulsatio ω, [ω mi, ω max ] is fixed accordi to the applicatio, thus, the expressio (4) must be satisfied. 1 1 ω LC, max LC (4) mi , 4 ω mi ω max where L ad C deote the total iductor ad capacitor respectively. The startup coditio is ive by [1]: α (5) active mi,max ISSN: Issue 6, Volume 5, Jue 008

3 where α mi [,3] is the small-sial loop ai, active ad are the active ad the coductace respectively. The VCO occupied area is fixed by the used iductors. A maximum value for each iductor diameter (d max ) is imposed. This coditio is also a determied factor i the iteratio of the oscillator. Parameter raes Techoloy parameters Costats ASITIC parameters Radom eeratio of a test vector d d max (6) Each compoet formi the VCO ca be cosidered as a oise source. The total phase oise level must be less tha a specified maximum value that depeds o the applicatio specificatios. Its expressio is ive by (7) [8]: Computi compaio formula Costraits are verified y L 1 1 i = 8π foffset q max f (7) { f } offset Γ rms, L{ f offset } spec where f offset is the offset frequecy from the carrier ad q max is the total chare swi of the. The impulse sesitivity fuctio Γ (ISF), represets the time-varyi sesitivity of the oscillator s phase to perturbatios. Γ rms, is the root mea square (RMS) value of the ISF of the th oise source. The i / f terms i the sum represet the equivalet differetial oise power spectral desity issued from drai curret oise, iductor oise, ad varactor oise. Computi Objective Fuctio NF<NF max y Update of the archive Stoppi criterio verified y Display 'optimal' parameters 4 The Optimizatio Approach The proposed heuristic is based o a stochastic approach that cosists of radomly eerati test vectors formed by ukows of the optimizatio problem. This is ecessary to face the lare umber of possible combiatios of cadidate solutios. Each test vector serves to compute compaio formula, i.e. values of parasitic compoets, etc. A data base is iterated i the optimizatio process. It cosists of parasitic elemets formi the iductor. These values were computed for differet operati frequecies, usi ASITIC software [9]. If the test vector satisfies imposed costraits such as trasistor saturatio coditios, it is memorized i a archive. I order to avoid a excessive rowth of the archive, a sorti routie is added to the proram, thus oly a predetermied umber of solutios is memorized. The optimizi process takes ed the stoppi criterio is verified. i.e. if the archive is ot updated after a certai umber of iteratios. Fiure 3 presets the flowchart of the proposed heuristic. Fi.3. Flowchart of the proposed heuristic 4.1 Desi variables raes The test vector is formed by the bias curret, MOS trasistor width ad the iductor value, which variatio raes are fixed by the user/techoloy. Sice parasitic elemets are ot fixed radomly but depeded o the iductor value, we start with the optimizatio of iductor surface usi ASITIC software. So, we obtai automatically all the eometric parameters, parasitic resistors (R S ad R SL ) ad capacitors (C S ) correspodi to the model provided by ASITIC (Fi.4). The, R pl ad C pl correspodi to the parallel π-model ca be calculated usi the followi equatios: R PL ( ωr C ) 1 + S S = (8) ω R SC S ISSN: Issue 6, Volume 5, Jue 008

4 C PL S = (9) 1 + C ( ωr C ) S S L S R SL I (14), the iductor effective parallel coductace L is determied by: 1 RsL L = + R (14) π fl ( ) pl 0 s CS R S CS R S Fi.4. Iductor model provided by ASITIC 4. Costraits formulatio Maily two costraits have to be satisfied to esure the fuctioi of a VCO: the start-up coditio ad the amplitude costrait. I the followi we detail their formulatios Start-up coditio From expressio (4), with α mi =, this coditio ca be ive by (10): start_up= 0 (10) active The active ad coductaces are calculated respectively by: active 1 p = µ Cox Ibias + µ pcoxp Ibias lchael lchael 1 Ibias ( λ + λ ) + + = p v L (11) (1) where, p, µ, µ p, C ox, C oxp, λ ad λ p are respectively chael width, mobility chares, oxide capacitace ad chael leth modulatio of NMOS ad PMOS trasistors formi active part. v is the varactor effective parallel coductace ad L is the iductor effective parallel coductace. To improve the 1/f 3 corer of phase oise, a symmetric active circuit with equal trascoductaces m = mp is used [9], which establishes a relatio betwee p ad. µ P = (13) µ p Both chael leth l ad l p of the NMOS ad PMOS trasistors are set to the miimum allowed by the techoloy (l chael ) to reduce parasitic capacitace ad et the hihest trascoductace. where R sl ad R pl are respectively the iductor parasitic series ad parallel resistaces. Ad the varactor effective parallel coductace v is ive by: v ( C v,max π f 0 ) R sv = (15) where C v,max is the maximum MOS varactor value ad R sv is the MOS varactor parasitic series resistace ive by (1). Sice the maximum total capacitace value C,max, is the sum of varactors capacitace C v, parasitic capacitaces of iductors C pl, NMOS ad PMOS ate to source capacitaces (C s, ad C s,p ) ad the load, the maximum MOS varactor value C v,max ca be expressed as: ( C + C + C ) C + v, max = C, max s, s, p pl Cload (16) where the total capacitace value C,max, ca be ive by: 1 C = (17), max ( π fmi) L Kowi that the maximum MOS varactor value equals C ox v l chael, the trasistor chael width is ive by: C v,max v = (18) Coxplchael 4.. Tak amplitude costrait From expressio (), this costrait is expressed by: V V 0 (19), mi where the amplitude is ive by [5]. 4 π I bias V = (0) 4..3 Objective fuctio The objective fuctio is the phase oise L{f offset } which must be less tha the phase oise ISSN: Issue 6, Volume 5, Jue 008

5 specificatio required by the applicatio L{f offset }(spec). { offset} 10 ( AB) L{ f } ( spec ) Lf = 10lo offset (1) where A is ive by: ( π f ) 4 1 L 0 A = 16π f offset V ad B is ive by: ( L V ( d0, d0,p )) () B = KT + KT + KTγ + (3) where d0, ad d0,p, the chael coductaces at zero V DS for NMOS ad PMOS trasistors respectively [10], are expressed for short-chael trasistors by: d0 = l = d0p l I chael I chael bias E bias E sat, sat, p () (3) with E sat, ad E sat,p are the saturatio electric field for NMOS ad PMOS trasistor respectively. 5 Optimized ad Simulatio Results The proposed heuristic was implemeted i C ++. Desi parameters raes are ive i Table 1. The parameters optimizatio will be doe for two frequecy raes: - The first oe betwee, ω mi =.4GHz ad ω max =.8GHz - The secod oe betwee, ω mi =5GHz ad ω max =5.8GHz. The parasitic elemets values of iductor, i.e. resistaces ad capacitaces, were determied usi ASITIC software for differet values of iductor. These values correspod to the discretizatio of the iductor s value rae. Table ad Table 3 preset these iductors parameters respectively for the first ad secod applicatios cited above. Table 1. Desi Parameters Raes 1mA, Bias curret I bias [ 4mA ] NMOS width [ 10µm, 100µm] Iductor value L [ 1H, 6H] tot Optimal obtaied parameters values ad performaces correspodi to the first ad secod applicatio are preseted respectively i tables 4 ad 5. Table. Iductor parameters at.6 GHz L 1 =L [H] R SL [Ω] R S [KΩ] C S [ff] Q L Table 3. Iductor parameters at 5.4 GHz L 1 =L [H] R SL [Ω] R S [KΩ] C S [ff] Q L Table 4. Optimal parameters values for the frequecy rae.4 Ghz to.8 Ghz I bias (ma) L tot (H) p v L{1Mhz} (dbc/hz) Table 5. Optimal parameters values for the frequecy rae 5 Ghz to 5.8 Ghz I bias (ma) L tot (H) p v L{1Mhz} (dbc/hz) ISSN: Issue 6, Volume 5, Jue 008

6 ADS simulatio results usi AMS 0.35µm techoloy ad.5v voltae power supply are preseted i Fi.5, Fi.7 ad Fi.9 correspodi to the secod row of table IV optimized parameters, ad i Fi.6, Fi.7 ad Fi.8 correspodi to the secod row of table 5 optimized parameters. Fi.5 shows that the VCO output sial oscillates betwee 0.83V ad.9v ivi amplitude equals to 1.49V for the first frequecy rae, while Fi.6 shows that the VCO output sial oscillates betwee 0.7V ad.45v ivi a amplitude equals to 1.75V for secod frequecy rae. var("tran.vout-"), V var("tran.vout+"), V Fi.5. Output sial at.6 Ghz var("tran.vout-"), V var("tran.vout+"), V time, sec time, sec Fi.6. Output sial at 5.4 GHz I Fi.7 ad 8, the frequecies versus cotrol voltae yieldi respectively a tui rae of 15% uder.5vpower voltae supply for the first frequecy rae ad a tui rae of 10.5% uder.8v supply for secod frequecy rae are preseted. At the ceter frequecy, i.e f 0 =.6 GHz, the oscillator phase oise, illustrated i Fi.11, achieves dbc/hz, dbc/hz ad -104 dbc/hz respectively at 1MHz, 600KHz ad 100KHz offset frequecies. hile at the ceter frequecy, i.e f 0 =5.4 GHz, the oscillator phase oise, which is preseted i Fi.10, achieves dbc/hz, dbc/hz ad dbc/hz respectively at 1MHz, 600KHz ad 100KHz offset frequecies. Frequecy (GHz) cotrol voltae(v) Fi.7. First applicatio VCO characteristic Frequecy (GHz) cotrol voltae (V) Fi.8. imax VCO characteristic pmx, dbc m3 m oisefreq, MHz Fi.9. Oscillator phase oise at.6ghz. pmx, dbc m3 m oisefreq, MHz Fi.10. Oscillator phase oise at 5.4GHz. m3 oisefreq= 100.9kHz pmx= dbc m oisefreq= 600.4kHz pmx=-10.4 dbc m1 m1 oisefreq= 1.000MHz pmx=-14.9 dbc m3 oisefreq= 100.9kHz pmx= m oisefreq= 600.4kHz pmx= dbc m1 m1 oisefreq= 1.000MHz pmx= Table 6 presets a compariso betwee theoretical (proposed heuristic) ad simulatio (ADS software) results. e otice the ood areemet betwee both results. Commoly, a fiure of merit (FOM) is used to compare obtaied performaces. Its expressio is ive by (4) [1]: ISSN: Issue 6, Volume 5, Jue 008

7 FOM= L f 0 { } ( ) offset [dbc/hz] + 10lo P[mw] 0lo foffset f (4) Table 7 presets a compariso betwee performaces obtaied usi the proposed heuristic ad some of published papers. Table 6.Compariso betwee theoretical ad simulatio results ADS Heuristic software L{1Mhz}.6 GHz (dbc/hz) 5.4 GHz Table 7. Compariso betwee VCOs Performaces Ref. Tech. Phase F 0 P [GHz] [m] oise [dbc/hz] This work µm [11] [1] [1] [13] [14] [15] [16] SiGe BJT process 0.35µm 0.35µm 0.18µm 0.13µm 90m 0.18µm 6 Coclusio FOM [dbc/hz] A optimizatio approach was proposed for the sizi of LC voltae cotrolled oscillators. It is a stochastic approach that cosists of computi optimal values of LC VCO compoets that miimizes the phase oise while satisfyi start-up ad amplitude costraits. Two applicatios examples were preseted. The preseted applicatio cosists of optimizi phase oise of a cross coupled LC VCO. Good performaces were reached for the frequecy rae [.4GHz,.8GHz] ad the frequecy rae [5.GHz, 5.8GHz]. They were compared to simulatio results ad to published works deali with this kid of VCO s lie. Refereces: [1] D. Ham ad A. Hajimiri, Cocepts ad Methods i Optimizatio of Iterated LC VCOs, IEEE joural of solid-state circuits, Vol. 36, No 6, 001, pp [] M. Hersheso, S. S. Moha, S. P. Boyd, ad T. H. Lee, Optimizatio of iductor circuits via eometric prorammi, i Proc. Desi Automatio Cof., 1999, pp [3] M. Hersheso, A. Hajimiri, S. S. Moha, S. P. Boyd, ad T. H. Lee, Desi ad optimizatio of LC oscillators, i Proc. IEEE/ACM It. Cof. Computer Aided Desi, Sa Jose, CA, Nov. 1999, pp [4] F. Herzel, H. Erzräber, et P. eer, Iterated widebad oscillator for RF applicatios, IEE Electroics Letters, Vol. 37, No. 6, 001. [5] A. Hajimiri, T. H. Lee; Desi Issues i Differetial LC Oscillators, IEEE Joural of Solid-State Circuits, Vol. 34, No 5, 1999, pp [6] J. Bhattacharjee, D Mukherjee, E. Geber, S. Nuttick ad J. Laskar, A 5.8 GHz Fully Iterated Low Power Low Phase oise LC VCO for LAN applicatios. IEEE Radio Frequecy Iterated Circuits (RFIC) Symposium, 00, pp [7] C.-M. Hu, Y.-C. Ho, I-C. u, ad K. O, Hih-Q Capacitors Implemeted i a Process for Low-Power ireless Applicatios; IEEE Trasactios o microwave theory ad techiques, Vol 46,No 5, [8] A. Hajimiri ad T. Lee, A eeral theory of phase oise i electrical oscillators, IEEE Joural of Solid-State Circuits, Vol. 33, No., 1998, pp [9] c.html [10] Y. P. Tsivids, Operatio ad Modeli of the MOS Trasistor, New York: McGraw-Hill, [11] P-. Lai, L. Dobos, S. Lo, A.4GHz SiGe low phase oise VCO usi o chip Tapped iductor, Solid-State Circuits Coferece, ESSCIRC, Sept. 003, pp [1] H-C. Che, C-H. Chie, H. Chiu, S. Lu, K. Cha, K. Che, ad S. Che, A Low-Power Low-Phase-Noise LC VCO with MEMS Cu Iductors, IEEE Microwave ad ireless Compoets letters, Vol. 15, No. 6, 005. [13] Y.-K. Chu ad H.-R. Chua, A fully iterated 5.8 GHz U-NII bad 0.18µm ISSN: Issue 6, Volume 5, Jue 008

8 VCO, IEEE Microwave ireless Compoet Letter, Vol. 13, No 7, 003, pp [14] D. Hauspie, E- C. Park, ad J. Craickx, idebad VCO with simultaeous Switchi of Frequecy Bad Active core ad Varactors Size, IEEE Joural of solid state circuits, Vol 4, No. 8, 007. [15] B. Soltaia, H. Aispa,. Rhee, A ultra compact differetially Tued 6 GHz LC-VCO with dyamic Commo Mode Feedback, IEEE Joural of solid state circuits, Vol 4,No, 8, 007. [16] T. So, S. Ko, D-H. Cho, H-S Oh, C-E. Yoo, A 5GHz Trasformer coupled VCO usi Bias level Shifti techique, IEEE Radio Frequecy Iterated Circuits Symposium, 004, pp ISSN: Issue 6, Volume 5, Jue 008

(2) The MOSFET. Review of. Learning Outcome. (Metal-Oxide-Semiconductor Field Effect Transistor) 2.0) Field Effect Transistor (FET)

(2) The MOSFET. Review of. Learning Outcome. (Metal-Oxide-Semiconductor Field Effect Transistor) 2.0) Field Effect Transistor (FET) EEEB73 Electroics Aalysis & esig II () Review of The MOSFET (Metal-Oxide-Semicoductor Field Effect Trasistor) Referece: Neame, Chapter 3 ad Chapter 4 Learig Outcome Able to describe ad use the followig: