Quad PIN-Electronics Drivers / Comparators / Analog Switches

Transcription

1 Quad PIN-Electronics Drivers / Comparators / nalog Switches GENERL DESCRIPTION NJU6496 includes four-channel PIN Driver, Comparator, and nalog Switch for kelvin connection. It is designed specifically for Test During Burn-In (TDBI) applications where cost, functional density, and power are all at a premium. Driver is able to set up threshold voltage, and control high level and low level output voltage, and high impedance independently. Comparator is able to control threshold voltage independently at each channel, and set up high level and low level output voltage. nalog Switch that includes two switches for a SENSE and FORCE in each channel is a switch for making Kelvin connection for current detection. This device has a 1V driver output range and comparator input range. NJU6496 is suitable for an interface to circuits, such as TTL, ECL, CMOS (3V, V and 7V), and LVCMOS, not only various tests of a Flash Devices. FETURES 1V Input and Output Voltage Range Low Consumption Current Low Output Leakage Current : Ileak<n 4 MHz Operation Driver DC Output Current : Io=1m Package : QFN84-D4 (1.mm x 1.mm, t=.mm) CMOS Structure PCKGE OUTLINE NJU6496KD4 PPLICTION Burn-In Testers TE Measuring Instrument BLOCK DIGRM *1) Driver, Comparator and SW shows per 1 channel. *) (-3) is applied to one of a figure to 3, and it shows each channel. *3) (-1) and (-8) is applied to one of a to 1 or to 8, and it is shortened within the IC. ver.1-1 -

2 NJU6496 PIN INFORMTION -- ver.1

3 No Symbol Function 39,4,66,67 DT(-3) Driver Mode Input (-3ch) 4,8,1,16,9,13,17 EN(-3) ENB(-3) Driver Output Enable / Hi-Z Setting Input(-3ch) 47,1,6,6 DOUT(-3) Driver Output, Comparator Input(-3ch) 48,,7,61 VIH(-3) Driver Output High Level Voltage Input (-3ch) 46,,,9 VIL(-3) Driver Output Low Level Voltage Input (-3ch) 34,7 VBB(-1) Driver Input (DT,EN) Threshold Voltage Input 7,9,78,8 CV(-3) Comparator Threshold Voltage Input (-3ch),1 VOH(-1) Comparator Output High Level Voltage Input 3, VOL(-1) Comparator Output Low Level Voltage Input 6,1,14,18 Q(-3) Comparator Output (-3ch) 4,49,4,8 DUT(-3) DUT Connecting (-3ch) 41,43,63,6 SENSE(-3) PMU Sense Connecting (-3ch) 4,44,6,64 FORCE(-3) PMU Force Connecting (-3ch) 81 DO Serial Data Output 8 DIN Serial Data Input 83 DLOD Serial Data Load 84 DTEN Serial Data Input Enable 1 CLK Serial Data Input Clock,3,31,3,36,7,71,7,76 VDD(-8) Positive Power Supply 4,3,33,37,38,68,69,73,74 VSS(-8) Negative Power Supply TEMP Thermal Diode (node) 3 TEMPK Thermal Diode (Cathode) 3 DGND Digital GND 7,11,1,19,6,8,77,79 NC not connected to internal circuits ver.1-3 -

4 BSOLUTE MXIMUM RTINGS (Ta= C) PRMETER SYMBOL CONDITION RTINGS UNIT Supply Voltage V DD - V SS V DD,V SS total Voltage 17. V Input Voltage V IN Each Input Terminal (Note 1 ) For supply voltage less than 17V, the maximum input voltage is equal to the supply voltage. (Note ) Mounted on glass epoxy board. ( mm:based on EI/JDEC standard, 4Layers) Back side center PD mounting (For 4Layers: pplying mm inner Cu area and a thermal via hole to a board based on JEDEC standard JESD1-) RECOMMENDED OPERTION CONDITIONS (Ta= C) V SS.3 to V DD (Note1) Power Dissipation P D (Note) 44 mw Output Current I OUT 13 m Operating Temperature Range T opr - to +8 Storage Temperature Range T stg -4 to +1 C PRMETER SYMBOL RTINGS UNIT Power Supply V DD - V SS 1. to 1. (total) V V ELECTRICL CHRCTERISTICS VDD=1V, VSS=-3V, VBB=1.V, DT=1.±1.V, VIH=V,VIL=V, EN=ENB=V, CL=33pF, RL=1kΩ, Ta= C unless otherwise noted. PRMETER SYMBOL TEST CONDITION MIN TYP MX UNIT Driver DC Characteristics High Level Output Voltage D OUTH DT=.V V Low Level Output Voltage D OUTL DT=V - -. V Output Leak Current (HiZ) Ileak EN=3V, DUT=9.V or 3V - - n Output Resistance Rout Ω DC Output Current (source) Isource DC m DC Output Current (sink) Isink DC m High Level Input Voltage V IH. - - V Low Level Input Voltage V IL V Input Bias Current Iin -1-1 n Driver C Characteristics (f=1mhz) Propagation Delay DT to DUT Fig.1 Tpdr,Tpdf VIH=3V, VIL=V ns EN to DUT (ctive to HiZ) Fig. Taz VIH=3V, VIL=V, DT=3.V, EN=V to 3.V,f =khz ns EN to DUT (HiZ to ctive) Fig. Propagation Delay Mismatch Fig.1 Tza VIH=3V, VIL=V, DT=3.V, EN=3.V to V,f =khz ns Tpdr - Tpdf VH=3V, VL=V ns ver.1

5 VDD=1V, VSS= -3V, VBB=1.V, DT=1.±1.V 1MHz, VIH=3V,VIL= V, EN=ENB=V, CL=33pF, RL=1kΩ,Ta= C, unless otherwise noted PRMETER SYMBOL TEST CONDITION MIN TYP MX UNIT Driver C Characteristics (f=1mhz) Rise / Fall Time 1V Swing Fig.3 Tr 1/ Tf1 VIH=1V, VIL=V, % to 8% ns 3V Swing Fig.3 Tr 3/ Tf3 VIH=3V, VIL=V, 1% to 9% ns V Swing Fig.3 Tr / Tf VIH=V, VIL=V, 1% to 9% ns 1V Swing Fig.3 Tr 1/ Tf1 VIH=1V, VIL=V,1% to 9% ns 1V Swing Fig.3 Tr1 / Tf1 VDD=1V,VIH=1V VIL= 3V, 1% to 9% ns Rise / Fall Time Mismatch Fig.3 Tr - Tf - - ns Overshoot, Undershoot, Preshoot Vshoot VIH=3V, VIL=V,CL=33pF mv Max. Operating Frequency Fig.4 Fmax VIH=V, VIL=V MHz Min. Pulse Width Fig.4 Tpw VIH=V, VIL=V ns DT % EN % % Tpd+ Tpd- Taz Tza DOUT % DOUT 9% % Fig.1 Fig. 9%(8%) D OUTH %.9*Vopp 1%(%) D OUTL Fmax Tr Tf Tpw + Tpw - Vopp=D OUTH -D OUTL (at f=1mhz) Fig.3 Fig.4 ver.1 - -

6 VDD=1V, VSS= -3V, EN=ENB=3V, CV=1.V, DOUT=1.±1.V 1MHz, VOH=3V, VOL= V, CL=33pF, RL=1kΩ, Ta= C, unless otherwise noted PRMETER SYMBOL TEST CONDITION MIN TYP MX UNIT Comparator DC Characteristics High Level Output Voltage Vch.7 3. V Low Level Output Voltage Vcl. V Input Offset Voltage Voff - mv Output Resistance Rcout 3 4 Ω Comparator C Characteristics Propagation Delay DUT to Q,QB Tcpdr, Tcpdf ns Overdrive Voltage Variation Common Voltage Variation ΔTpd/ ΔDUTamp1 ΔTpd/ ΔDUTamp. ΔTpdcm DOUT=1.V±[1mV~1V] ns/v DOUT=1.V±[1V~.V] ns/v CV=V~3.V, DOUT=CV±1.V - - ns Propagation Delay Mismatch Tcpdr-Tcpdf - - ns Others Rise / Fall Time Fig.3 Tcr / Tcf 1% to 9% ns Max. Operating Frequency Fig.4 Fmax VOH=3V, VOL=V MHz Min. Pulse Width Fig.4 Tpw VOH=3V, VOL=V ns VDD=1V, VSS= -3V, Ta= C, unless otherwise noted PRMETER SYMBOL TEST CONDITION MIN TYP MX UNIT nalog Switch Characteristics FORCE Switch Resistance Rf V FORCE=V, I DUT=1m Ω SENSE Switch Resistance Rs V SENSE=V, I DUT=1m kω FORCE Capacitance Cf SW open 9 pf SENSE Capacitance Cs SW open 8 pf DUT Capacitance Cd SW open 1 pf Switch Current Leakage Iswleak V DUT=V, V SENSE=-3 or 9.V, V FORCE=-3 or 9.V - - n ver.1

7 VDD=1V, VSS= -3V, VBB=1.V, DT=V, VIH=3V, VIL=V, EN=ENB=V, RL=1kΩ, CL=33pF, CV=1.V, VOH=3V, VOL=V, Ta= C, unless otherwise noted PRMETER SYMBOL TEST CONDITION MIN TYP MX UNIT Power Supplies Positive Power Supply DC Current Negative Power Supply DC Current I DD No Signal m I SS No Signal m VDD=1V, VSS= -3V, Ta= C, unless otherwise noted PRMETER SYMBOL TEST CONDITION MIN TYP MX UNIT Data Interface Setup Time Tst - - ns High Level Data Pulse Width Low Level Data Pulse Width DTEN Low Hold Timing DTEN High Hold Timing Tpwh ns Tpwl ns Tcel - ns Tceh - ns CLK Max. Input Frequency Fclk MHz DO Output Propagation Delay Max. Logic Setting Time DLOD Data Pulse Width Tco ns Tel - - ns Tlw ns High Level Input Voltage Vdh.4-1 V Low Level Input Voltage Vdl V DO Rise / Fall Time Trdo, Tfdo CL=1pF ns ver.1-7 -

8 TRUTH TBLES Driver DT, EN, ENB VBB+.V VBB-.V Status H L EN ENB DT DOUT H X X HiZ(OPEN) X H X HiZ(OPEN) L L H VIH L L L VIL Comparator DOUT Status DOUT Q CV+.1 H H VOH CV-.1 L L VOL SWITCH CONTROL Timing Table Tpwh CLK Tpwl Tceh DTEN Tcel Tel DLOD Tlw DIN D7 D6 D D4 D3 D D1 D D7 B D6 B D B D1 Z D Z DO D7 D6 D D1 Y D Y Tco Data Input Timing Table ver.1

9 Input Data Table DT FUNCTION BIT STTE 1 DEFULT D CH3 FORCE SW OPEN CLOSE D1 CH3 SENSE SW OPEN CLOSE D CH FORCE SW OPEN CLOSE D3 CH SENSE SW OPEN CLOSE D4 CH1 FORCE SW OPEN CLOSE D CH1 SENSE SW OPEN CLOSE D6 CH FORCE SW OPEN CLOSE D7 CH SENSE SW OPEN CLOSE Data Interface NJU6496 includes the serial interface for analog switch control. This serial interface consists of an 8-bit shift register and a switch control register. Data input is CLK, DTEN, DLOD, and DIN, and a data output is DO. - Data input While DTEN is set as LOW, data input and an output will be in an active state. DIN is loaded to a shift register by the rising edge of CLK. - Data output The data of a shift register is outputted through DO. DO is a buffer output of the last bit of a shift register, and is outputted with the voltage level of VDD and VSS. It is possible to carry out daisy chain connection of multiple devices using DO. - Loading of switch (or Switch Loading) The load timing of an analog switch is controlled by DLOD. The data of a shift register is loaded to a switch control register with the falling edge of DLOD, and the state of an analog switch is changed. The data loaded to the switch control register holds data, as long as there is no rewriting of data. - OFF state While DTEN is set as HIGH, data is not loaded but DO is simultaneously fixed to LOW. Moreover, it is not necessary to input CLK. - Power-on state The switch control register immediately after power activation is set as LOW, and an analog switch will be in a CLOSE (OFF) state. ver.1-9 -

10 TYPICL CHRCTERISTICS VDD=1V, VSS=-3V, VBB=1.V, ENx=ENBx=V, VIHx=3V, VILx=V, CVx=1.V, VOH=3V, VOL=V, RL=1k Ω, CL=33pF, Ta= unless otherwise specified. 6 [Driver] Output Response [Driver] 出力波形 VIH=1, 3, V VIL=V VIH=1, 3, V VIL=V 14 [Driver] Output Response [Driver] 出力波形 VIH=1, 1V VIL=V VIH=1, 1V VIL=V DOUT [V] VIH=V VIH=3V VIH=1V DOUT [V] VIH=1V VIH=1V ns/div ns/div [Driver] Propagation Delay, Rise/Fall Time [Driver] 伝達遅延 立上り立下り時間 vs Power Supply Voltage 対電源電圧特性 [Driver] Propagation Delay, Rise/Fall Time [Driver] 伝達遅延 立上り立下り時間 vs Temperature 対周囲温度特性 Tpdf Tpdf [ns] 1 Tpdr [ns] 1 Tpdr 1 Tr 1 Tr Tf Tf DOUT [V] VDD [V] [Driver] Output Response [Driver] 出力波形 ENx=ENBx=3V EN=ENB=3V ns/div Ileak [n] Ta [ºC] [Driver] DOUT Output Leakage Current [DRV] DOUT 端子出力リーク電流対出力電圧特性 vs ENx=ENBx=3V Output Voltage Ta=8 4 - Ta=ºC DOUT [V] ver.1

11 3. [Comparator] Output 出力波形 Response [Comparator] Propagation Delay, Rise/Fall Time [Comparator] 伝達遅延 立上り立下り時間対電源電圧 vs Power 特性 Supply Voltage 3. 1 Tcpdr Q [V] 1. 1 [ns] 1 Tcpdf Tcr ns/div VDD [V] Tcf [Comparator] Propagation Delay, Rise/Fall Time [Comparator] 伝達遅延 vs Temperature, 立上り立下り時間温度依存 [Comparator] Propagation Delay Overdrive Voltage Variation [Comparator] 伝達遅延 DOUT=1.V±Vin オーバードライブ特性 DOUT=1.V±Vin 4 1 Tcpdr [ns] 1 Tcr Tcpdf Tcpd [ns] Tcpdf Tcpdr Tcf Ta [ºC] Vin [±V] Tcpd [ns] [Comparator] Propagation Delay Common Voltage Variation [Comparator] 伝達遅延コモン電圧特性 DOUT=1.V±1.V, VOH=3V, VOL=V DOUT=1.V±1.V VOH=3V VOL=V 3 Tcpdf 1 1 Tcpdr CV [V] Rs [kω] [SW] Switch Resistance vs Temperature [SW] スイッチ抵抗対周囲温度特性 Rf Rs Ta [ºC] 3 Rf [Ω] ver

12 Ileak [n] [SW] FORCE Leakage Current [SW] FORCE 端子リーク電流特性 Ta=8 - Ta=ºC FORCE [V] Ileak [n] [SW] SENSE Leakage Current [SW] SENSE 端子リーク電流特性 Ta=8 - Ta=ºC SENSE [V] Supply Current vs Temperature Supply Current vs Operating Frequency 消費電流対 No 周囲温度特性 Signal 無信号時 1 消費電流対 4ch 動作周波数特性 Operation 4ch 動作時 1 IDD [m] / ISS [-m] IDD ISS IDD [m] Ta [ºC] fin [MHz] ver.1

13 NOTICE, CUTIONS 1) Short pins in IC and connection to them on the board VSS(-8),VDD(-8),VBB(-1) and VOH(-1),VOL(-1) are shorted in the IC, respectively. But you should connect all of the pins to decrease the impedance of power supplies. ) Power-on Sequence You should power on with the following sequence: first VSS(-8), second VDD(-8), third VBB(-1) and CV(-3), then power on the other inputs. Otherwise sequence may cause a permanent damage to the IC. 3) Leak Current in HiZ Mode The leak current might exceed n in case of the following: 1. When DOUT(-3) or VIH(-3) or VIL(-3) voltage set near VDD voltage. When the junction temperature is high. [CUTION] The specifications on this data book are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this data book are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. ver