COMPACT HIGH PERFORMANCE ANALOG CMOS BASEBAND DESIGN SOLUTIONS FOR MULTISTANDARD WIRELESS TRANSCEIVERS

Transcription

1 COMPACT HIGH PERFORMANCE ANALOG CMOS BASEBAND DESIGN SOLUTIONS FOR MULTISTANDARD WIRELESS TRANSCEIVERS DISSERTATION Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University By Seok-Bae Park, B.S., M.S. ***** The Ohio State University 2006 Dissertation Committee: Approved by Mohammed Ismail El-Naggar, Adviser Patrick Roblin Steven B. Bibyk Adviser Graduate Program in Electrical and Computer Engineering

2 c Copyright by Seok-Bae Park 2006

3 ABSTRACT In this dissertation, a novel compact wireless radio transceiver architecture reusing a baseband chain so as to significantly reduce the die area is proposed. The proposed architecture employs a direct conversion architecture with a shared baseband chain and is suitable for wireless standards based on time-division duplexing air interface. In direct conversion architectures, baseband channel selection filters and variable gain amplifiers are placed in the receive path as well as in the transmit path. Here, it is proposed to use the same baseband filters and variable gain amplifiers in both the receive path and the transmit path to reduce the die area. To realize a high performance direct conversion receiver for multistandard wireless communications, the limiting factors in the direct conversion receiver should be identified and removed. In this dissertation, among many problems in direct conversion receivers, the DC offset problem is addressed. The origins of the DC offset are summarized, and three self-mixing mechanisms generating the DC offset are modeled to understand how the static and dynamic DC offsets are produced from the mechanisms. A DC offset cancellation scheme consisting of a static DC offset canceller and a dynamic DC offset canceller is proposed. For the static DC offset canceller, a DC feedback loop is proposed to use and verified through simulation, fabrication, and measurement. A novel dynamic DC offset canceller utilizing an adaptive filtering technique is also proposed and verified through simulation. ii

4 An analog baseband chain for the proposed compact wireless transceiver is designed in this dissertation. A fully balanced differential difference amplifier is designed as a core amplifier to be used in both a baseband filter and a variable gain amplifier. A fully differential Sallen-Key channel selection filter and a fully differential variable gain amplifier using attenuators which can be shared for both the transmit path and the receive path are designed. A DC feedback loop is designed to cancel the static DC offset. This baseband chain is realized in a 0.5 μm standard CMOS process and verified through simulation, fabrication, and measurement. iii

5 This is dedicated to my parents and my wife... iv

6 ACKNOWLEDGMENTS First of all, I deeply thank Prof. Mohammed Ismail, my advisor, for giving me a chance to join the Analog VLSI Lab., for his invaluable advice on my research and my future, for his constant guidance and numerous discussions on my dissertation research, and for all the support and opportunities. I heartily thank Prof. Patrick Roblin and Prof. Steven Bibyk for being on my dissertation committee. I greatly appreciate their kindness and their precious time for me. I thank Eisenhower National Clearinghouse (ENC) and Semiconductor Research Corporation (SRC) for their financial support throughout my graduate studies. I express my special thanks to Karen Abhari and Roger Cunningham at ENC for their giving me opportunities. I also thank many members of the Analog VLSI Lab. for numerous technical discussions, inspiration, and help. From the bottom of my heart, I thank my parents, my sisters, and my wife, Yonghee, for their love, encouragement, guidance, and support. v

7 VITA May Born - Pusan, Korea February B.S. Electrical Engineering, Seoul National University, Seoul, Korea August M.S. Electrical Engineering, Seoul National University, Seoul, Korea December M.S. Computer Engineering, Ohio State University, Columbus, Ohio April September Graduate Research Associate, Ohio State University, Columbus, Ohio PUBLICATIONS Research Publications Mohammed Ismail, Seok-Bae Park, Ayman A. Fayed, and R. F. Wassenaar, Operational Transconductance Amplifiers, Chapter 22, The VLSI Handbook, 2nd Ed., CRC Press, Seok-Bae Park and Mohammed Ismail, A Reconfigurable CMOS Analog Baseband for Compact TDD Wireless Radio Transceivers, Proc. of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 05), pp , August Seok-Bae Park and Mohammed Ismail, DC Offset Cancellation in Direct Conversion Multistandard Wireless Receivers, Proc. of International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 05), pp , June Seok-Bae Park, Hyang-Beom Lee, Il-Han Park, and Song-Yop Hahn, Stator Slot Shape Design of Induction Motors for Iron Loss Reduction, IEEE Transactions on Magnetics, Vol. 31, No. 3, pp , May vi

8 FIELDS OF STUDY Major Field: Electrical Engineering Studies in: Analog VLSI RF and Microwave Prof. Mohammed Ismail El-Naggar Prof. Patrick Roblin vii

9 TABLE OF CONTENTS Page Abstract Dedication Acknowledgments Vita List of Tables ii iv v vi xi List of Figures xii Chapters: 1. Introduction Motivation and Objectives Organization of the Dissertation Wireless Receiver Architectures Introduction Heterodyne Receiver Architecture Direct Conversion Receiver Architecture Low-IF Receiver Architecture Digital-IF Receiver Architecture Summary viii

10 3. Compact TDD Wireless Transceiver Architecture Introduction Transceiver Architecture Description and Design Issues Summary DC Offset Problem in Direct Conversion Receivers Introduction DC Offset Modeling DC Offset Generation DC Offset Model DC Offset Cancellation for Multistandard Receivers Static DC Offset Cancellation Dynamic DC Offset Cancellation Dynamic DC Offset Cancellation Using Adaptive Filtering Adaptive Filtering Techniques Adaptive Dynamic DC Offset Cancellation Simulation Studies Summary Design of Analog Baseband Prototype Introduction Fully Balanced Differential Difference Amplifier Circuit Implementation Simulation Results Channel Selection Filter Fully Differential Sallen-Key Low Pass Filter Simulation Results Measurement Results Static DC Offset Cancellation using DC Feedback Loop DC Feedback Loop Design Simulation Results Measurement Results Variable Gain Amplifiers Fully Differential Variable Gain Amplifier Using Attenuators Simulation Results Measurement Results Summary ix

11 6. Conclusion Contribution of the Dissertation Future Work Appendices: A. Wireless Communication Standards B. MatLab Codes Bibliography x

12 LIST OF TABLES Table Page 4.1 Maximum Doppler shift Performance of the fully balanced differential difference amplifier Performance of the fully differential sixth-order Sallen-Key low pass filter Performance of the fully differential variable gain amplifier A.1 3G Standards A.2 Wireless LAN Standards xi

13 LIST OF FIGURES Figure Page 2.1 Heterodyne architecture Direct conversion architecture Low-IF architecture Digital-IF architecture Die photo example from [1] Die photo example from [2] Direct conversion transceiver architecture Compact TDD wireless radio transceiver architecture Reconfigurable compact TDD wireless radio transceiver architecture Spectrum for direct conversion Generation of DC offsets due to self-mixing I-branch of direct conversion receivers Self-mixing models in direct conversion receivers Multistandard DCR with DC offset cancellation Static DC offset canceller xii

14 4.7 Ideal frequency response of the static DC offset canceller Adaptive filtering problem classification Dynamic DC offset canceller Simulation setup with ideal channel Simulation setup with AWGN channel symbol BPSK simulation results with ideal channel: part symbol BPSK simulation results with ideal channel: part symbol BPSK simulation results with AWGN channel (E b /N 0 = 3): part symbol BPSK simulation results with AWGN channel (E b /N 0 = 3): part BER performance of the dynamic DC offset canceller A buffer configuration Fully balanced differential difference amplifier (FBDDA) symbol Fully differential buffer configuration using FBDDA Realization of FBDDA with common-mode feedback (CMFB) circuits Layout view of the FBDDA in the buffer configuration AC response of the fully balanced differential difference amplifier AC response of the FBDDA in the buffer configuration Noise response of the FBDDA Step response of the FBDDA in the buffer configuration Input 1dB compression point of the FBDDA in the buffer configuration 59 xiii

15 5.11 Third-order Sallen-Key low pass filter Fully differential third-order Sallen-Key low pass filter using FBDDA Fully differential third-order Sallen-Key low pass filter for multistandard operation Fully differential sixth-order multistandard Sallen-Key low pass filter AC response of the sixth-order Sallen-Key low pass filter Group delay response of the sixth-order Sallen-Key low pass filter Noise response of the sixth-order Sallen-Key low pass filter Input 1dB compression point of the sixth-order Sallen-Key low pass filter IIP3 of the sixth-order Sallen-Key low pass filter Step response of the sixth-order Sallen-Key low pass filter Fully differential third-order Sallen-Key low pass filter with a buffer for measurement Measured frequency response of the fully differential Sallen-Key low pass filter Measured intermodulation test of the fully differential Sallen-Key low pass filter Die photo of the fully differential Sallen-Key low pass filter with a measurement buffer Magnified die photo of the fully differential Sallen-Key low pass filter with a measurement buffer Static DC offset canceller Implementation of g m cell in the static DC offset canceller xiv

16 5.28 Implementation of capacitance Frequency response of the OTA Frequency response of the static DC offset canceller Static DC offset canceller around the Sallen-Key low pass filter with measurement buffer Measured frequency response of the static DC offset canceller Die photo of the static DC offset canceller Magnified die photo of the static DC offset canceller with a buffer for measurement Fully differential variable gain amplifier using non-inverting amplifier Frequency response of the VGA using non-inverting amplifier Fully differential variable gain amplifier (VGA) using attenuators and FBDDA Fully differential variable gain amplifier (VGA) chain using attenuators and FBDDAs AC response of the VGA Noise response of the VGA Input 1dB compression point of the VGA IIP3 of the VGA Step response of the VGA Fully differential VGA using attenuators and FBDDAs with a measurement buffer Measured frequency response of the fully differential variable gain amplifier xv

17 5.46 Measured intermodulation test of the fully differential variable gain amplifier Die photo of the fully differential variable gain amplifier Magnified die photo of the fully differential variable gain amplifier with a buffer for measurement xvi

18 CHAPTER 1 INTRODUCTION 1.1 Motivation and Objectives A great deal of effort in academia and industry has been made to meet the ever-growing demands for low-cost, low-power, and single-chip transceivers for multistandard wireless communications. The explosive growth in the mobile phone market has fueled the transition from the second generation (2G) to the third generation (3G), and the growing demand for wireless access to the Internet in buildings has called for the development of wireless local area network (LAN) standards. Even short range wireless communication devices for connecting peripherals to a computer or speakers to an audio amplifier are in great demand recently. Therefore, to develop a single-chip wireless transceiver working for as many wireless standards as possible has been a challenging problem. To reach the ultimate goal, the first step would be the choice of an appropriate transceiver architecture for effectively processing the signal received at the antenna. The right selection of the transceiver architecture is the key to success in developing a multistandard single-chip wireless transceiver. The first objective of the dissertation is to propose a novel wireless transceiver architecture which occupies a smaller area 1

19 and can work for many wireless standards. The proposed transceiver architecture is especially designed for time-division duplexing systems. Among many transceiver architectures, the direct conversion, alsoknownasho- modyne or zero-if, is the most attractive choice for multistandard wireless transceivers because of its simplicity and suitability for monolithic integration as well as multistandard operation [3]. Though the direct conversion architecture possesses many preferable characteristics, it still has some critical drawbacks which should be mitigated in order to be successfully implemented. The second objective of the dissertation is to address the DC offset problem, which is one of the inherent problems in the direct conversion architecture. In this dissertation, the DC offset generation mechanisms are modeled and the DC offset cancellation methods for multistandard wireless transceivers are discussed. A DC offset canceller which can track and cancel a fast varying DC offset is also proposed. Here, adaptive filtering techniques are utilized to cancel the fast varying DC offset. The third objective of the dissertation is to design a prototype of an analog baseband chain for the proposed compact wireless transceiver. The idea is to design a single core amplifier and then use it to implement a channel selection filter as well as a variable gain amplifier. This reduces a design time and can contribute toward a smaller die area by choosing an appropriate filter structure and a variable gain amplifier topology. The design of a DC feedback loop is included to cancel the DC offset which varies very slowly or does not change over time. The design of this baseband chain is realized in a 0.5 μm standard CMOS process and verified through simulation, fabrication, and measurement. 2

20 1.2 Organization of the Dissertation The dissertation is organized as follows. Chapter 2 briefly summarizes a variety of wireless communication receiver architectures. In Chapter 3, a compact wireless transceiver architecture suitable for time-division duplexing systems is proposed and its design issues are discussed. Chapter 4 addresses the DC offset problem in direct conversion receiver architecture. How the DC offset can be generated and how it can be modeled are presented. A DC offset cancellation scheme for multistandard direct conversion receivers is proposed and a novel fast varying DC offset cancellation scheme using an adaptive filtering technique is presented. In Chapter 5, the design of analog baseband circuits for the proposed compact wireless transceiver architecture is presented. To realize the baseband chain, a core amplifier is designed first and then we use the core amplifier for designing a channel selection filter and a variable gain amplifier. To cancel a very slowly or not varying DC offset, a DC feedback loop is designed and placed around the baseband filter. All the simulation results as well as measurement results are presented in this chapter. Chapter 6 concludes the dissertation and identifies future work. 3

21 CHAPTER 2 WIRELESS RECEIVER ARCHITECTURES 2.1 Introduction In wireless communication receivers, the received radio frequency (RF) signal should be downconverted to baseband and sampled for further processing in digital domain. The received signal is processed first in the analog domain and passed on to the digital domain, and thus analog-to-digital and digital-to-analog conversions should occur somewhere in the receiver path. So, there are choices of receiver architectures according to where to put the analog-to-digital converter (ADC) and the digital-toanalog converter (DAC) and how to downconvert the received signal. It ranges from the traditional heterodyne architecture to digital-if architectures. In this chapter, some of the important receiver architectures such as heterodyne, direct conversion, low-if, and digital-if receiver architectures are briefly summarized. 2.2 Heterodyne Receiver Architecture In the heterodyne receiver architecture shown in Figure 2.1, an RF signal is downconverted to an intermediate frequency (IF) by the first mixer. Then the signal is I/Q separated and downconverted to baseband by the second mixers. The first band 4

22 Channel Select LPF ADC I Band Select Image Reject Channel Select BPF LNA BPF BPF IF Amp LO2 90 o LO1 LPF Channel Select ADC Q Figure 2.1: Heterodyne architecture pass filter (BPF) located in front of the low noise amplifier (LNA) is for frequency band selection. The second BPF is for image rejection, and the third BPF and a low pass filer (LPF) are for channel selection. After low pass filtering for channel selection, the signal is sampled at baseband, which is called baseband sampling. As shown in Figure 2.1, the channel selection is done at IF as well as at baseband before ADC, which relaxes the Q required of each channel selection filter. The heterodyne architecture has been the most popular receiver architecture for a long time due to its good selectivity and sensitivity and can be found in many commercial RF transceivers. It relaxes the dynamic range of the baseband circuits. But, normally the IF band pass filter and the image reject (IR) filter are external components, which makes this architecture not suitable for monolithic integration. 2.3 Direct Conversion Receiver Architecture Fig. 2.2 shows a direct conversion receiver (DCR) architecture which is also known as homodyne or zero-if receiver architecture. In practice, an RF band selection filter is placed between an antenna and an LNA, but it is not shown in the figure 5

23 LPF VGA ADC I LNA DSP o 90 LPF VGA ADC Q Figure 2.2: Direct conversion architecture for simplicity. The DCR downconverts the desired signal directly from RF to DC and utilizes the baseband sampling. Thus, the DCR eliminates the need for discrete image rejection (IR) as well as intermediate frequency (IF) filters, which makes it suitable for monolithic integration. In addition, as the desired signal band is downconverted to the baseband at the early stage in the receiver chain, it is relatively easy to design the baseband circuits for multistandard operation. That is, the channel selection and automatic gain control (AGC) in DCRs are done at baseband using on-chip low pass filters and variable gain amplifiers which can be made to work for multiple wireless communication standards with low cost and less current consumption. Since the information bearing signal and blockers are translated to baseband together and channel selection is done at baseband, the DCR usually requires high dynamic range baseband circuits. This architecture becomes the most popular architecture in implementing an integrated single-chip receivers, but the main problems are DC offset problem and I/Q mismatch. 6

24 VGA BP ADC I Band Select BPF LNA o 90 LO Poly Phase Filter VGA BP ADC Q Figure 2.3: Low-IF architecture 2.4 Low-IF Receiver Architecture As shown in Fig. 2.3, the low-if architecture looks quite similar to the direct conversion architecture except that it downconverts the received signal not to DC but to a low intermediate frequency (IF). The low-if architecture also does not need external IF and IR filters, which makes it suitable for monolithic implementation. In addition, it does not suffer from DC offset problem which is the main problem in DCRs. But it has an image problem, so it needs integrated poly-phase filter for image rejection. 2.5 Digital-IF Receiver Architecture Fig. 2.4 shows the digital-if architecture [4] where an RF signal is downconverted to IF by an analog mixer and directly sampled at IF. Low frequency operations such as the second mixing and filtering are performed in digital domain, which is called IF sampling. Since the I and Q are not separated in the analog domain, only one ADC 7

25 Channel Select LPF I Band Select BPF LNA Image Reject BPF Channel Select BPF IF Amp ADC 0 o o 90 Digital Sinewave Generator LO LPF Channel Select Q Figure 2.4: Digital-IF architecture is necessary instead of two ADCs and I/Q mismatch problem is avoided. At least one analog IF stages can be eliminated compared to heterodyne architecture. Since analog-to-digital conversion is done at IF, the baseband can be very easily made programmable. So, this architecture is suitable for multistandard operation. The main difficulty in this architecture is to achieve very high ADC requirements such as very low quantization and thermal noise, very high clocking rate, high linearity, wide dynamic range, wide input bandwidth. Heavy anti-aliasing filtering may be costly for mobile units. 2.6 Summary In this chapter, some of the important receiver architectures such as heterodyne, direct conversion, low-if, and digital-if receiver architectures were briefly summarized and their advantages and drawback were discussed. 8

26 CHAPTER 3 COMPACT TDD WIRELESS TRANSCEIVER ARCHITECTURE 3.1 Introduction To realize high performance wireless radio transceivers in a smaller die area has been a challenging problem. In particular, reducing the silicon area is extremely crucial in implementing a multistandard transceiver in a single chip because baseband circuitry processing both in-phase (I) and quadrature-phase (Q) signals in both the receive and transmit paths end up occupying a significant part of the transceiver die area that could reach up to 50 % of the total die in some applications. Fig. 3.1 and Fig. 3.2 show die microphoto examples from [1] and [2], respectively. Both chips are for wireless LAN applications and the figures illustrate that the I and Q analog baseband circuits take up at least 35 or 40 % of the total die area. In this chapter, a novel compact wireless radio transceiver architecture reusing a baseband chain so as to reduce a considerable die area is proposed. This transceiver architecture is especially suitable for time-division duplexing (TDD) systems but can be used for frequency-division duplexing (FDD) systems too. 9

27 Figure 3.1: Die photo example from [1] 10

28 Figure 3.2: Die photo example from [2] 11

29 3.2 Transceiver Architecture Description and Design Issues The proposed architecture employs a direct conversion architecture with a shared baseband chain. Due to its simplicity and suitability for single-chip implementation as well as multistandard operation, the direct conversion architecture [4] [5] is chosen. Fig. 3.3 shows a generic direct conversion transceiver architecture with DC feedback loops for DC offset cancellation. A radio frequency (RF) transmit/receive (T/R) switch is placed after an antenna to switch between the receive path and the transmit path for TDD systems. Before a low noise amplifier (LNA), an RF band selection filter may be also placed. The order of the baseband filter and the variable gain amplifiers (VGAs) may vary according to the wireless standards and corresponding system designs. In some applications, VGAs may not be necessary in the transmit path. However, in general, direct conversion architectures have baseband filters and VGAs placed in the receive path as well as in the transmit path as shown in Fig Here, it is proposed to use the same baseband filters and VGAs in both the receive path as well as the transmit path to reduce the die area. Fig. 3.4 shows the proposed transceiver architecture employing a direct conversion architecture with a shared baseband chain. The same baseband filters and VGAs are utilized in both the receive path and the transmit path to reduce the die area. In order for the baseband filters and the VGAs to be shared, switches are deployed in front of and at the end of the baseband chain. So, in the receive mode, the switches are connected such that the signal from down-conversion mixers is fed to the baseband chain and its output goes to analog-to-digital converters (ADCs). On the other hand, in the transmit mode, the switches are connected such that the 12

30 DC Offset Cancellation LPF VGA ADC I LNA LPF VGA ADC Q Frequency Synthesizer DC Offset Cancellation PA VGA LPF DAC I VGA LPF DAC Q Figure 3.3: Direct conversion transceiver architecture ADC I DC Offset Cancellation LNA LPF VGA ADC Q Frequency Synthesizer PA LPF VGA DAC I DC Offset Cancellation DAC Q Figure 3.4: Compact TDD wireless radio transceiver architecture 13

31 ADC I DC Offset Cancellation LNA LPF VGA ADC Q Frequency Synthesizer LPF VGA DC Offset Cancellation (a) Receiver configuration DC Offset Cancellation LPF VGA Frequency Synthesizer PA LPF VGA DAC I DC Offset Cancellation DAC Q (b) Transmitter configuration Figure 3.5: Reconfigurable compact TDD wireless radio transceiver architecture 14

32 signal from digital-to-analog converters (DACs) is fed to the baseband chain and up-conversion mixers get its output. As reported in [6], baseband filters and VGAs can be designed to be further reconfigurable for multistandard operation. That is, the number of filters and VGAs as well as the order of filters and VGAs can be made reconfigurable for each wireless standard. For some applications that VGAs are not necessary in the transmit path, the proposed transceiver can be reconfigured such that the transmit path does not have VGAs. DC feedback loops for DC offset cancellation can be also reconfigurable for each of the receive and transmit mode as well as for each wireless standard. The dynamic behavior of this technique should be carefully considered. When we switch from the receive mode to the transmit mode, we may be able to turn off the DC feedback loops to save power since DC offset compensation may not as critical in the transmit path in some applications. However, we should also make sure that the turn on time of the DC offset compensation loop is adequate for proper operation when we switch back to the receive mode. This has to be determined based on the application at hand. The same argument could be made for the automatic gain control (AGC) loop in which case one should consider the settling time of such a loop in the receive mode. Also, the switches at baseband must be tightly synchronized with the switch at the RF front end and their parasitics must be modeled carefully and incorporated into the design process. The proposed compact wireless transceiver architecture can be used for any wireless applications to achieve small die area as long as the system is designed to meet the required specifications. Since this architecture employs switches operated by control signals from digital signal processing units, the baseband circuits should be 15

33 designed to be settled fast enough. As the proposed architecture shares a single analog baseband chain for both the receive and transmit paths, it should be used with timedivision duplexing (TDD) systems. Applications using TDD systems include IEEE a/b/g [7][8][9], Bluetooth [10], and TD-CDMA (UTRA/TDD). However, it can be also used in frequency-division duplexing (FDD) systems if continuous reception is not necessary. As long as transmission and reception do not occur at the same time, this compact wireless transceiver architecture can be utilized. 3.3 Summary In this chapter, a novel compact wireless radio transceiver architecture reusing a baseband chain was presented. By sharing the baseband chain, the proposed architecture can reduce a considerable die area. Since this transceiver architecture shares a single analog baseband chain which is configured for the receive mode or transmit mode, it is especially suitable for time-division duplexing systems. 16

34 CHAPTER 4 DC OFFSET PROBLEM IN DIRECT CONVERSION RECEIVERS 4.1 Introduction Among many architectures, the direct conversion architecture is the most attractive choice of architecture for multistandard wireless transceivers due to its simplicity and suitability for monolithic integration as well as multistandard operation. As mentioned in Section 2.3, in spite of many merits in using DCRs, a set of problems inherent in DCRs such as DC offset, I/Q mismatch, flicker noise (1/f noise), and even-order distortion, have been difficulties in deploying DCRs [11][3][12]. Among the problems mentioned above, DC offset problem has been known as the most serious problem [11]. In DCRs, since the desired signal band is downconverted directly to baseband as shown in Figure 4.1, any DC offset can corrupt the desired signal. In addition, as most of amplification in DCRs takes place in the baseband chain, a small DC offset can be amplified by baseband amplifiers to a level that saturates the following stages and consequently prohibits the amplification of the desired signal [4]. Therefore, it is necessary to cancel the DC offset to successfully implement the DCR. Thus far, to use AC coupling, high pass filtering (HPF), or DC feedback 17

35 0 ω c ω 0 ω Figure 4.1: Spectrum for direct conversion loop is the most popular and common solution [13][14][15][16]. They can be effective in eliminating the DC offset which is not changing over time, but cannot cancel a fast varying DC offset. Some digital cancellation methods have been also introduced in [17][18][19]. However, the cancellation methods have been developed mostly for a specific standard or a modulation scheme, and little work has been done for multistandard wireless receivers. In this chapter, we investigate the origin of the DC offset and then model the DC offset. Based upon the modeling, we propose a novel digital DC offset cancellation method using an adaptive filtering technique and also consider issues for multistandard operation. Two types of DC offset have been identified. DC offset can be considered constant over time (called static or time-invariant) or changing over time (called dynamic or time-varying). As pointed out in [20], time-varying DC offset may not be a precise expression in some sense because it is not DC any more. We use the term static/dynamic DC offset throughout the dissertation as the term can be found more often in the literature. 18

36 4.2 DC Offset Modeling In this section, we summarize the DC offset generation mechanisms in DCRs and present the modeling of the DC offset to better understand the DC offset problem DC Offset Generation DC offsets in DCRs can be generated by the following mechanisms [3][11][12]: 1. transistor mismatches in the signal path, 2. self-mixing of local oscillator (LO) signals leaking into the RF port of the mixer and the input port of the LNA as shown in Fig. 4.2(a), 3. self-mixing of LO signals leaking into, radiated from, and reflected back to the antenna as shown in Fig. 4.2(b), 4. self-mixing of strong in-band interferers leaking into the LO port of the mixer from the output of the LNA as shown in Fig. 4.2(c), and 5. second-order intermodulation (IM2) of the components such as LNAs, mixers, and filters. Though only the I-branch is shown in Fig. 4.2, the Q-branch undergoes the same phenomenon. The main source of DC offset is self-mixing which is the signal multiplied by itself. Considering a simple sinusoidal local oscillator (LO) signal with frequency ω and ignoring the delay in leakage signal, from the trigonometric identities, self-mixing yields cos(ωt) cos(ωt) = cos(2ωt) 19

37 LNA LO Leakage (a) Self-mixing due to LO leakage LNA LO Leakage (b) Self-mixing due to LO leakage radiated LNA Interferer Leakage (c) Self-mixing due to interferer leakage Figure 4.2: Generation of DC offsets due to self-mixing 20

38 where we see that the DC term and the twice frequency term are generated. The higher frequency term is removed from the following low pass filter, but the DC term remains and may corrupt the desired signals and saturate the following stages if no cancellation method is applied. LO leakage is defined as the finite amount of feedthrough existing from the LO port to the RF port of the mixer, to the input port of the LNA, and to the antenna, and it arises from capacitive coupling, substrate coupling, and bond wire coupling if the LO signal is externally provided [4]. The DC offsets generated by the mechanism 1 and 2 can be considered as static whereas those by the mechanism 3 and 4 as dynamic, which will be clearer from the modeling presented in the next section DC Offset Model In this section, we present mathematical formulation of DC offset problem. We employ the similar approach used in [21]. As the main source of DC offset is selfmixing which is the signal multiplied by itself, we analyze the DC offset generated by self-mixing mechanisms here. Thus we assume that the components such as LNAs, mixers, and filters are ideal and do not exhibit nonlinearities. Particularly, we assume that the above circuits are well-balanced so that the DC offset produced by the evenorder nonlinearity would not be an issue here. Usually, LNAs and mixers should be designed such that their even-order nonlinearity could be low enough. In this way, we can simplify the problem and separate the DC offset due to self-mixing from the DC offset due to IM2. The analysis for second-order intermodulation in mixers can be found in [22] and [23]. The DC offset produced by mechanism 1 is not significant and may be considered as a static DC offset so that it is not modeled in this dissertation. 21

39 u(t) LNA s(t) y(t) LPF x(t) l(t) Figure 4.3: I-branch of direct conversion receivers It can be reduced by better matching in layout and can be cancelled out using the static DC offset canceller which will be discussed in Section 5.4. Fig. 4.3 shows the I-branch of DCR. Using complex envelope representation [24], the local oscillator (LO) signal l(t) in the figure can be expressed as l(t) = 2Re{e j2πfct } where Re{ } represents the real part of a complex variable and f c is a carrier frequency. For simplicity, a unit amplitude of LO signal is assumed. Assuming that the channel is ideal, the received signal u(t) from the antenna is a real-valued passband signal given as u(t) = 2Re{b(t) e j2πfct } where b(t) is a complex-valued baseband signal. 2 is to ensure that the passband signal has the same energy as the baseband signal. Ideally, the mixer input signal s(t) is s(t) =Au(t) 22

40 where A is the gain of the LNA and the mixer output signal y(t) issimply y(t) =s(t) l(t). Therefore, in ideal case, the filtered output x(t) is written as x(t) =A Re{b(t)}. (4.1) Now, we analyze the DC offset generated by three self-mixing mechanisms. The models corresponding to the three self-mixing mechanisms are shown in Fig DC Offset Generated by Self-Mixing due to LO Leakage In Fig. 4.4(a), the mixer input signal s(t) which is now corrupted by the LO leakage can be written as s(t) =Au(t)+(K 1 + AK 2 ) l(t) where A is the LNA gain and K 1 and K 2 represent the attenuation of the LO signal leaking into the mixer and the LNA. Then, y(t) issimplyequaltos(t) l(t) andthe output of the low pass filter, x(t) is x(t) =A Re{b(t)} +(K 1 + AK 2 ). (4.2) From (4.2), we see that the DC terms K 1 and AK 2 have been generated by this selfmixing mechanism. As A, K 1 and K 2 are not expected to be changing over time, the DC offset in (4.2) can be considered as static DC offset. Obviously, the LO leakage reached the LNA input port creates a larger DC offset due to the gain of the LNA. DC Offset Generated by Self-Mixing due to LO Leakage Radiated When the LO leakage is radiated from the antenna and reflected back from moving objects or buildings, we can model the problem as shown in Fig. 4.4(b). When 23

41 u(t) LNA s(t) y(t) LPF x(t) K 2 K 1 l(t) (a) Self-mixing model due to LO leakage u(t) LNA s(t) y(t) LPF x(t) l(t) Doppler Shift K 3 (b) Self-mixing model due to LO leakage radiated u(t) LNA s(t) y(t) LPF x(t) K 4 l(t) (c) Self-mixing model due to interferer leakage Figure 4.4: Self-mixing models in direct conversion receivers 24

42 Carrier Frequency Maximum Doppler shift Maximum Doppler shift from a person from a vehicle 800 MHz 4.2 Hz 71.5 Hz 1.9 GHz 9.9 Hz Hz 2.4 GHz 12.5 Hz Hz 5.15 GHz 26.9 Hz Hz Table 4.1: Maximum Doppler shift an electromagnetic wave reflected from a moving object, it undergoes the Doppler effect [25], i.e. when the reflecting object is moving toward or away from the receiver, the frequency of the signal reflected back to the receiver increases or decreases. The Doppler shift (f DS ) is a function of the relative speed (v) of the reflecting object and the receiver, a carrier frequency (f c ), and the angle of arrival (α) of the reflected signal such as f DS [Hz] = vf c c cos(α) where c is [m/s]. When the average human walking speed is 3.5 [mph] and the average vehicle driving speed is 60 [mph], assuming the receiver is stationary, the maximum Doppler shifts (when α is equal to zero) for four carrier frequencies are computed in Table 4.1. To simplify the analysis, we assume that the radiated LO leakage experiences an ideal channel ignoring multipath fading, noise, and time delay. As shown in Fig. 4.4(c), we consider only Doppler effect in this analysis. Then, the received signal u(t) corrupted by the radiated LO leakage experiencing Doppler shift can be written as u(t) = 2Re{b(t) e j2πfct } + K 3 2Re{e j2π(f c+f DS )t } 25

43 where K 3 models the attenuation of the LO signal leaking into the antenna and f DS represents the maximum Doppler effect experienced by the leakage. As s(t) is equal to Au(t), the filtered output x(t) is x(t) =A Re{b(t)} + AK 3 Re{e j2πf DSt }. (4.3) We see from (4.3) that this mechanism does produce a time-varying DC offset term with the frequency of f DS, and we also know from Table 4.1 that the DC offset varies very slowly. Though we pick the largest maximum Doppler shift in the table which is Hz, the duration of one period is msec which is quite long compared to the preamble or symbol duration of wireless standards such as IEEE a [7] in Appendix A. DC Offset Generated by Self-Mixing due to Interferer Leakage Self-mixing due to interferer leakage can be formulated in the same manner as in [21]. The received signal u(t) corrupted by the interferer can be written as u(t) = 2Re{b(t) e j2πfct } + 2Re{a(t) e j2πf it } where a(t) is an interference signal centered at f i. The LO signal l(t) corrupted by the interferer leakage is expressed as l(t) = 2Re{e j2πfct } + AK 4 u(t). Since s(t) isequaltoau(t), the output of the low pass filter x(t) is x(t) =ARe{b(t)} + A Re{a(t) e j2πfot } + A 2 K 4 [ a(t) 2 + b(t) 2 +2 Re{a(t) b (t) e j2πfot }] (4.4) 26

44 where f o = f i f c and denotes complex conjugate. From (4.4), we identify the DC terms A 2 K 4 a(t) 2 and A 2 K 4 b(t) 2, and time-varying terms A Re{a(t) e j2πfot } and 2 A 2 K 4 Re{a(t) b (t) e j2πfot } from interferer self-mixing mechanism. Here, f o should be less than the cut off frequency of the low pass filter (LPF) as x(t) has passed the LPF. Therefore, the interferers producing dynamic DC offset are nearby user signals or any other strong signals in the same channel. Consequently, the range of f o is from 0 Hz to the LPF cut off frequency, and f o cannot be known in advance. 4.3 DC Offset Cancellation for Multistandard Receivers From the DC offset modeling in the previous section, we learn that how much static as well as dynamic DC offsets in the DCR can be generated by self-mixing due to LO and interferer leakages. Based upon the models presented, we propose a multistandard DCR architecture with DC offset cancellation in Fig Since it is a multistandard DCR, the DCR is controlled by many control signals from the DSP as shown in the figure. As shown in Fig. 4.5, the static and dynamic DC offsets are cancelled separately in the proposed architecture. To prevent the back-end in the receiver from saturation, the large DC offsets that are constant or varying very slowly have to be removed in the analog domain right after the mixer. In other words, the static DC offsets generated by the self-mixing mechanisms analyzed in Section and Section as well as theveryslowlyvaryingdcoffsetobservedin Section should be cancelled before LPF. The same DC feedback loop can also be deployed around VGAs to cancel the DC offset generated by the VGAs, but it must be placed around the LPF to effectively cancel the DC offset generated by the down-conversion mixers. In our proposed 27

45 Static DC Offset Canceller DC Feedback LPF VGA ADC I Dynamic DC Offset Canceller LNA o 90 Control Signals DSP LPF VGA ADC Q Dynamic DC Offset Canceller DC Feedback Static DC Offset Canceller Figure 4.5: Multistandard DCR with DC offset cancellation architecture, DC feedback loops are employed as our static DC offset cancellers as shown in Fig More detailed discussion on the static DC offset cancellation will follow in Section The residual dynamic DC offsets generated by the self-mixing mechanism analyzed in Section can be removed in the digital domain. The fast varying dynamic DC offset generated by self-mixing due to interferer leakage cannot be easily measured and subtracted because it cannot be known when the dynamic DC offset is produced. For some wireless communication standards receiving signals continuously, the longterm averaging method can be used for canceling the dynamic DC offset. That is, the received signals are stored during a certain time period and the mean value of them is subtracted from each data. But this is not capable of cancelling rapidly varying 28

46 DC offset. Therefore, we need a more sophisticated and refined technique in digital domain to cancel the dynamic DC offset. For a multistandard DCR, the cancellation scheme should work for both continuous reception and burst reception cases. Section and Section 4.4 will discuss on the dynamic DC offset cancellation Static DC Offset Cancellation To cancel the static DC offset, we have to cut out some portion of the spectrum around DC using high pass filtering. Thus, the main issue here is whether or not we can do so without degrading the performance. Consequently, a modulation scheme is the most critical issue for the static DC offset cancellation in multistandard DCRs. Modulation schemes such as FSK have little energy around DC, so we can use high pass filtering to cancel the static DC offset. Modulation schemes like PSK have considerable amount of energy near DC, but for wideband systems, the performance degradation due to high pass filtering may not be critical. It is reported in [12] that the cutoff frequency of the high pass filtering should be about 0.1 % of data rate to avoid significant degradation. For multistandard operation, we need to either adjust the high pass cutoff frequency according to each standard or set it to the lowest one which corresponds to the lowest data rate. In this dissertation, we propose to use a DC feedback loop [13][26][27] shown in Fig. 4.6 as a static DC offset canceller. A DC feedback loop creates a high pass pole at a frequency close to DC to remove a static DC offset. We could use an AC coupling capacitor or a high pass filter instead of a DC feedback loop to create a high pass pole. But, to use DC feedback loops is more apt for multistandard operation as well as monolithic implementation 29

47 C g m Vin LPF Vout Figure 4.6: Static DC offset canceller because we can easily control the high pass cutoff frequency with smaller capacitance values. be found as The transfer function of the static DC offset canceller shown in Fig. 4.6 can V out (s) V in (s) = 1+s(r o C) (1 + g m r o )+s ( ) ( ) r o C + 1 S LP F + s 2 roc S LP F where r o is the output resistance of the transconductance (g m ) cell and S LP F is the low pass pole created by the low pass filter (LPF). Assuming 1 r oc S LP F, the transfer function can be approximated near DC as ( ) V out (s) V in (s) 1 1+s(ro C) 1+g m r o 1+s ( ) r oc 1+g mr o which clearly shows that the DC feedback loop functions as a high pass filter. Fig. 4.7 shows the ideal frequency responses for the static DC offset canceller shown in Fig By fixing the value of g m and r o and changing the value of C, we can easily change the high pass cutoff frequency of the static DC offset canceller according to each wireless standard. As we can see from Fig. 4.7, we need to have g m smaller to achieve a lower high pass cutoff frequency with a reasonable size of integrated 30

48 1 1 1+g m r o 1 r o C m g C S LPF s Figure 4.7: Ideal frequency response of the static DC offset canceller capacitors. In addition, we observe that we need to have r o larger to have enough attenuation around DC Dynamic DC Offset Cancellation In order to effectively cancel the dynamic DC offset, we should estimate the DC offset and subtract it from the original signal in real-time in the digital domain. Also, to make the cancellation scheme work for multistandards, the technique should not be sensitive to the modulation schemes. Adaptive filtering would be the best technique to track and cancel the dynamic DC offset in multistandard environment. In particular, the dynamic DC offset can be effectively cancelled by using the adaptive noise cancellation technique [28]. In the next section, a detailed description of the proposed dynamic DC offset cancellation mechanism will be presented. 31

49 4.4 Dynamic DC Offset Cancellation Using Adaptive Filtering In this section, a dynamic DC offset cancellation scheme using adaptive filtering technique is presented. A brief summary on adaptive filtering techniques is introduced first, and then we explore the dynamic DC offset cancellation technique using adaptive noise cancellation techniques Adaptive Filtering Techniques An adaptive filter has been a powerful tool in signal processing and control applications due to its ability to operate satisfactorily in an unknown environment and track time variations of input statistics [28]. The adaptive filtering problems can be classified into 4 classes. Identification: In Fig. 4.8(a), the plant represents an unknown system. The plant and the adaptive filter are fed by the same input u(n). By adjusting the filter coefficients, the adaptive filter provides a linear model of the unknown plant. Channel estimation in communication systems falls into this class. Inverse modeling: In Fig. 4.8(b), the plant is an unknown system and the adaptive filter provides an inverse model of the unknown plant. In the case of a linear system, the inverse model has an inverse transfer function of the unknown plant. Channel equalization in communication systems is classified into this class. Prediction: As shown in Fig. 4.8(c), the filter provides the prediction of the present value of the random input based on the past values of the input u(n). Source 32

50 coding, channel prediction, and de-noising are some of the applications of this class. Interference cancellation: As shown in Fig. 4.8(d), the filter has two inputs, d(n) and u(n). d(n) is called a primary signal containing an information bearing signal and an unknown interference or noise signal. u(n) is called a reference signal which is derived from the interference or noise source. The adaptive filter can cancel the unknown interference or noise in the primary signal using the reference signal. Applications of this class include noise cancellation, echo cancellation, and beamforming. Thus, adaptive filters in all four classes have the same elements: desired response d(n), adaptive filter output y(n), adaptive filter input u(n), and the estimation error e(n) which is calculated as e(n) =d(n) y(n). The adaptive filter adjusts the filter coefficients so that the estimation error is minimized in some sense. In other words, a recursive algorithm is employed to update the filter coefficients. Basically, there are two kinds of popular recursive algorithms: the Least-mean-square (LMS) algorithm and the Recursive least-square (RLS) algorithm. The RLS algorithm is based on the least-square (LS) algorithm which is deterministic. The RLS converges faster than the LMS, but it is more complex and could have a stability issue. On the other hand, the LMS is the stochastic gradient decent algorithm. In the LMS, the filter coefficients are updated according to w(n +1)=w(n)+μ u(n) e (n) 33

51 u(n) Plant d(n) e(n) Adaptive Filter y(n) (a) Identification d(n+ Δ ) Delay d(n) e(n) (Δ) Plant u(n) Adaptive Filter y(n) (b) Inverse modeling u(n+ Δ ) d(n) e(n) y(n) Delay (Δ) u(n) Adaptive Filter (c) Prediction d(n) e(n) u(n) Adaptive Filter y(n) (d) Interference cancellation Figure 4.8: Adaptive filtering problem classification 34

52 where w(n) represents the adaptive filter coefficient at time index n, μ the step size, and * complex conjugate. The LMS is simpler and more stable than the RLS, and it has a good tracking performance. But it takes longer to converge than the RLS. By far, the LMS is the most popular adaptive filtering algorithm and will be used in our case too Adaptive Dynamic DC Offset Cancellation The main target DC offset to be cancelled in the digital domain is the dynamic DC offset generated by self-mixing due to interferer leakage. From the DC offset models, we know that the dynamic DC offset is a sinusoid with the frequency f o. Thus, our dynamic DC offset cancellation problem is reduced to an adaptive noise cancellation problem with the primary input (d(n)) consisting of the desired signal (s(n)) and a dynamic DC offset (o(n)). As shown in the Fig. 4.8(d), the original adaptive noise canceller needs a primary input d(n) as well as a reference input u(n) which is correlated to the offset signal o(n). When we denote the primary input d(n) as d(n) =s(n)+o(n), the reference signal as u(n) =o 1 (n), and the adaptive filter output as y(n),the error signal e(n) will be equal to d(n) y(n). Here, we know that the desired signal s(n) is uncorrelated to o(n) andtoo 1 (n), but the offset signals o(n) ando 1 (n) are correlated to each other. So, by adapting the adaptive filter using some algorithm, we can get the filter output y(n) o(n), 35

53 s(n) + o(n) Primary Input d(n) y(n) e(n) Delay (Δ) u(n) Reference Input Adaptive Filter Adaptive Noise Canceller Figure 4.9: Dynamic DC offset canceller which means e(n) s(n). But the reference input is not available in our problem. Thus, we should employ the adaptive noise canceller without an external reference source [29] shown in Fig As shown in Fig. 4.9, the reference signal u(n) in our problem is the delayed version of the input signal d(n) consisting of the desired signal s(n) andthe dynamic DC offset o(n) which is a sinusoid, that is, u(n) =d(n Δ) = s(n Δ) + o(n Δ). As a whole, this is also called an adaptive linear forward predictor [29][30] which can cancel a sinusoid from a broadband signal. In modern digital communication systems, the modulated signal can be considered as broadband signal, so that this dynamic DC offset canceller can work for wireless multistandard. Since the desired signal s(n) is a broadband signal and the dynamic DC offset o(n) is a sinusoid, s(n) and s(n Δ)) are uncorrelated and o(n) ando(n Δ)) are correlated. Therefore, the delayed version of the input signal can be an effective reference signal for the adaptive 36

54 (1 or 0) (1 or 1) Data Generation BPSK Modulation Upsampling TX Filter RX Filter Adaptive Offset Canceller Downsampling BPSK Demodulation Figure 4.10: Simulation setup with ideal channel noise canceller. By adapting the adaptive filter using some algorithm, we can make the signal e(n) equal to our desired signal s(n) which is free from the dynamic DC offset Simulation Studies Simulations were performed with 1 Mbps binary phase shift keying (BPSK) signals and 1 MHz of a dynamic DC offset. The magnitude of the offset is bigger than that of the desired signal by 30 db. An ideal channel is assumed first and later the additive white Gaussian noise (AWGN) channel is considered. Fig shows the Matlab simulation setup which models a digital communication transmitter (TX) and a receiver (RX) [31] in an ideal channel environment. To make the simulation setup more realistic, the BPSK modulated signal is upsampled at the TX and downsampled at the RX. The number of oversamples used here is 10. The TX and RX filters are Nyquist filters with roll-off factor 0.5 and 21 taps. The adaptive dynamic DC offset canceller is located between the RX filter and the downsampler. The dynamic DC offset signal is added to the receiver signal, which is not shown in the figure. In 37

55 (1 or 0) (1 or 1) AWGN Data Generation BPSK Modulation Upsampling TX Filter RX Filter Adaptive Offset Canceller Downsampling BPSK Demodulation Figure 4.11: Simulation setup with AWGN channel Fig. 4.11, the Matlab simulation setup in an additive white Gaussian noise (AWGN) channel environment. The white Gaussian noise is added to the channel in the model. Among many algorithms to update the adaptive filter, we used the normalized least mean square (NLMS) algorithm [28] in which the adaptive filter coefficient w(n) is updated using w(n +1)=w(n)+μ NLMS u(n) e (n) where μ NLMS =1/(μ 1 + u(n) 2 ) and * denotes complex conjugate. μ was chosen to be Two important parameters in designing the adaptive dynamic DC offset canceller are the adaptive filter length and the value of the delay, Δ. The choice of the optimal filter length in an adaptive linear forward predictor has been studied in [30] and it is shown that the optimal filter length is dependent on input SNR and signal bandwidth α. Under low SNR conditions, L opt = 1/α, and under high SNR conditions, L opt < 1/α. Thus, L opt 1/α 38

56 where α is the signal bandwidth [30]. This gives an idea on the upper bound of L. Attempting to over-resolve narrowband signal by increasing L eventually degrades the performance because of larger misadjustment noise. The value of the delay, Δ, which is known as the prediction distance of the filter or decorrelation parameter, should be chosen in such a way that the broadband signal can be effectively decorrelated and disappeared at the filtered output, y(n). In adaptive linear forward predictor, the optimum Δ, Δ opt, which minimizes the prediction error (e(n)) power is derived and given by ω(2δ opt + L 1) = nπ where n is integer. Thus, the optimum value of Δ is a function of the filter length (L) and the frequency (ω) of the input sinusoid which are not known apriori[32]. So, it is difficult to use this in our problem. It is also reported that the optimum value of Δ for noise suppression lies in an interval between the correlation distance of the noise and the correlation distance of the signal [30]. A series of simulations were performed to get an optimum length with Δ = ceil(l/2) and then to find an optimum delay. In our case, the adaptive filter length (L) is chosen to be 9 and the delay (Δ) is set to 5, which gives the best performance from the simulation studies. Fig. 4.12(a) shows the offset corrupted signal which is input to the DC offset canceller and Fig. 4.12(b) shows its output. Fig. 4.13(a) and Fig. 4.13(b) show the squared data error with offset canceller and without offset canceller, respectively. Right at the moment that the DC offset was applied, the error occurred, but soon it cancelled all the dynamic DC offset. Fig. 4.14(a), Fig. 4.14(b), Fig. 4.15(a), and Fig. 4.15(b) show the simulation results with AWGN channel. In this case, the DC offset was applied from the beginning. Since the channel is no longer ideal, there are 39

57 some errors even with the DC offset canceller. However, compared to the case without the offset canceller, we still see that the offset canceller can effectively cancel the offset. Fig shows the BER performance in AWGN channel. The simulation results show that the BER performance was much improved with this dynamic DC offset cancellation scheme compared to the case without the dynamic DC offset cancellation. The MatLab codes developed for simulations appear in Appendix B. 4.5 Summary In this chapter, three self-mixing mechanisms generating the DC offset in direct conversion receivers were modeled. A DC offset cancellation technique suitable for multistandard wireless direct conversion receivers was proposed. The proposed cancellation scheme suggests to separate the dynamic DC offset cancellation from the static DC offset cancellation. A dynamic DC offset canceller utilizing an adaptive filtering technique was proposed and verified through simulation. The simulation results demonstrate that the proposed dynamic DC offset technique can effectively cancel a very fast varying DC offset. 40

58 40 AFP input signal d(n) corrupted by offset (a) offset corrupted input d(n) corrected signal and desired signal e s (b) offset canceller output e(n) Figure 4.12: 1000-symbol BPSK simulation results with ideal channel: part 1 41

59 2 (raw data demodulated data) (a) squared data error with offset cancellation 2 (raw data demodulated data) (b) squared data error without offset cancellation Figure 4.13: 1000-symbol BPSK simulation results with ideal channel: part 2 42

60 40 AFP input signal d(n) corrupted by offset (a) offset corrupted input d(n) 20 corrected signal and desired signal e s (b) offset canceller output e(n) Figure 4.14: 1000-symbol BPSK simulation results with AWGN channel (E b /N 0 =3): part 1 43

61 2 (raw data demodulated data) (a) squared data error with offset cancellation 2 (raw data demodulated data) (b) squared data error without offset cancellation Figure 4.15: 1000-symbol BPSK simulation results with AWGN channel (E b /N 0 =3): part 2 44

62 10 0 BER BPSK BER theory w/o offset offset with cancellation offset w/o cancellation Eb/N0 [db] Figure 4.16: BER performance of the dynamic DC offset canceller 45

63 CHAPTER 5 DESIGN OF ANALOG BASEBAND PROTOTYPE 5.1 Introduction In this chapter, the design of a fully differential analog baseband chain is presented. A fully differential architecture has been chosen for improving the performance in terms of supply noise rejection, dynamic range, and harmonic distortion [6]. First, the chapter starts with a core amplifier design for use in both the baseband channel selection filter and the variable gain amplifier (VGA). A fully balanced differential difference amplifier (FBDDA) is employed as a core amplifier in this design. And the design of the channel selection filter and the VGA using the FBDDA follow. 5.2 Fully Balanced Differential Difference Amplifier A differential difference amplifier (DDA) [33][34][35] has been adopted as the core amplifier in the design of the analog baseband chain including a channel selection filter and a variable gain amplifier (VGA). The DDA is a versatile building block for analog signal processing and has been utilized in many applications [33][34][35]. In particular, a fully balanced version of the DDA [36][37] has been employed in this design to implement a fully differential analog baseband chain. 46

64 V i V o Figure 5.1: A buffer configuration The fully balanced differential difference amplifier (FBDDA) is an attractive choice in implementing fully differential op-amp circuits where both the op-amp inputs are floating [37]. Especially, the FBDDA is quite useful in realization of a fully differential buffer. Fig. 5.1 shows a common buffer configuration using a single-ended op-amp. This buffer configuration cannot be converted to a fully differential buffer configuration by the steps described in [38] because none of the op-amp inputs are grounded. Normally, one can use two single-ended op-amps to build a fully differential buffer, that is, one for the positive input and the other for the negative input, in which case the number of elements are doubled and the matching between the two paths is difficult to achieve. However, as shown in Fig. 5.2, a FBDDA has four inputs so that a fully differential buffer can be readily constructed using a single FBDDA, which results in a smaller area and a better matching. This is the reason why the FBDDA was chosen in this implementation of an analog baseband chain. As it will be discussed in Section 5.3 and Section 5.5, the FBDDA is very suitable for implementing fully differential Sallen-Key filters as well as fully differential variable gain amplifiers. Once a FBDDA is designed, we can extensively use it in implementing a baseband filter and a variable gain amplifier. 47

65 Vpp Vpn Vop Vnp Von Vnn Figure 5.2: Fully balanced differential difference amplifier (FBDDA) symbol As shown in Fig. 5.2, the FBDDA has four inputs. The outputs of the FBDDA can be written as V op V on = A o [(V pp V pn ) (V np V nn )] (5.1) where A o is the open-loop gain of the FBDDA and it is ideally infinite. From (5.1), when a negative feedback is applied, the two differential inputs have the following relation: (V pp V pn )=(V np V nn ) (5.2) as A o [36][37], that is, the differential voltages of the two inputs become equal as the open-loop gain A o approaches infinity. Therefore, the open-loop gain A o should be made as large as possible to achieve a good performance, which is also the case in the op-amp design. Now that a FBDDA has four inputs and two outputs, two outputs can be fed back to construct a fully differential buffer as shown in Fig In the figure, in order to make negative feedbacks, the positive output V + o is connected to the negative input V pn and the negative output V o is connected to the positive input V nn.inthiscase, 48

66 Vi V o V i V o Figure 5.3: Fully differential buffer configuration using FBDDA V nn should be considered as a positive input because it is a double negative in the notation. This fully differential buffer configuration will be utilized in the design of a Sallen-Key low pass filter in Section Circuit Implementation Fig. 5.4 shows a circuit implementation of the FBDDA with two common-mode feedback (CMFB) circuits. As shown in the figure, the core of the FBDDA is a twostage amplifier. The first input stage of the amplifier has two differential pairs instead of one to accommodate four inputs. The PMOS input stages (M1 through M4) are employed with NMOS current source loads (M5 and M6). The PMOS input stage has been chosen for a better noise performance against the NMOS counter part [39]. The second output stages consist of NMOS common-source stages (M9 and M10) and PMOS current source loads (M11 and M12). To ensure the stability, compensating capacitors (C c ) and resistors (R c ) [40][41] are included. The small-signal voltage gain 49

67 of the FBDDA is given as A o = g m1 (r o1 r o5 ) g m9 (r o9 r o11 ) (5.3) where g m and r o denote the transconductance and the output resistance of MOS transistors, respectively. So, in order to increase the gain, the transconductance of the input and output common-source stages should increase. The input-referred thermal noise can be obtained as Vn 2 = 16 ( 2 3 kt + g ) m5 g m1 gm1 2 (5.4) where k is the Boltzmann s constant ( J/K) and T is the temperature in Kelvin [42] [37]. This suggests that large input PMOS devices and small NMOS load devices are preferable to achieve low noise. Two CMFB circuits are used to keep the common-mode output voltages from drifting [43]. Normally, one CMFB circuit is employed for setting the output voltage of the second stage, but it was found out through corner simulations that the output voltage of the first stage also needs a CMFB circuit. Two different types of CMFB circuits are utilized. The circuit in Fig. 5.4(b) is used to set the second-stage commonmode output voltages (V op and V on ) and the circuit in Fig. 5.4(c) is used to set the firststage common-mode output voltage (V op1 and V on1 ) [44]. The CMFB1 in Fig. 5.4(b) senses the second stage output common-mode voltage which is the average voltage of V op and V on through two equal size resistors (R cm ). The voltage between the two resistors, V oc,is V oc = V op + V on 2 (5.5) and the desired common-mode voltage V cm is subtracted from the detected commonmode voltage V oc. Then, the output voltage of the differential amplifier consisting 50

68 M11 Vb3 M7 Vb1 M8 Vb3 M12 Von Vpn M1 M2 Vpp Vnp M3 M4 Vnn Vop Cc Rc Rc Cc Vop1 Von1 M9 M5 Vb2 M6 M10 (a) FBDDA core Vb3 M3c M4c Rcm Ccm Vop Vcm M1c M2c Voc Vbcm1 M5c Ccm Rcm Von (b) CMFB1 M6cc Vb1 M7cc Von1 M1cc M2cc Vcm2 M3cc M4cc Vop1 Vb2 M5cc (c) CMFB2 Figure 5.4: Realization of FBDDA with common-mode feedback (CMFB) circuits 51

69 of M1c through M5c controls the gate voltages of the second stage PMOS current sources, M11 and M12, in Fig. 5.4(a). The CMFB1 circuit can control the commonmode voltage quite well so that the output common-mode voltage is very close to the V cm provided. from loading effect. But due to the resistors (R cm ) and capacitors (C cm ), it suffers On the other hand, the CMFB2 in Fig. 5.4(c) [43] uses only transistors and it does not have as much loading effect as the CMFB1 does. In CMFB2, the differential pairs M1cc through M4cc are matched and the first stage output common-mode voltage in Fig. 5.4(a) is detected through M1cc through M4cc. Here, the drain current in M2cc and the drain current in M3cc are proportional to the voltage differences V op1 V cm2 and V on1 V cm2, respectively. These currents are summed in diode-connected NMOS M5cc and mirrored by M5 and M6 in Fig. 5.4(a) to consequently control the first stage output common-mode voltage. The CMFB2 circuit is still capacitively loaded by the PMOS M1cc and M4cc but it is suitable to control the first stage output common-mode voltage. The CMFB1 cannot be used in place because its resistive load can severely affect the performance. The FBDDA circuit has been designed using the AMI 0.5 μm standard digital process available through MOSIS [45]. It is a twin-well CMOS technology on P- substrate. The process has two poly and three metal layers. The Poly-Insulator-Ploy (PiP) capacitors consisting of the two poly layers has capacitance of 950 af/μm 2. The resistors can be made using a high resistance poly (HRP) layer, one of the two poly layers. The threshold voltage is about 0.71V for NMOS and about 0.99V for PMOS. The value of μ n C ox for NMOS is about 100 μa/v 2 and that of μ p C ox for PMOS is about 40 μa/v 2. The nominal supply voltage of the process is 5V but the FBDDA was designed with 3V supply voltage. Fig. 5.5 shows the layout view of 52

70 the FBDDA in the buffer configuration shown in Fig This FBDDA is used in both the baseband filter and the variable gain amplifier implementation which will be described in the later sections Simulation Results The FBDDA was simulated using the BSIM3v3 models in Cadence environment. Table 5.1 summarizes the open-loop performance of the FBDDA in the typical corner. The amplifier was loaded with 2pF capacitance. The DC gain was traded off for the bandwidth. In the buffer configuration, the gain-bandwidth product is 126.7MHz. The spot noise was measured at 20MHz where the minimum occurs. The spot noise at 1MHz was 15.2nV/ Hz. The 1dB input compression point in the buffer configuration is 15dBm. The AC response of the open-loop configuration is shown in Fig. 5.6 and that of the buffer configuration in Fig Fig. 5.8 illustrates the noise performance. For stability test, the step input was applied into the amplifier in the buffer configuration and its step response is shown in Fig The plot of the 1dB input compression point in the buffer configuration is illustrated in Fig

71 Figure 5.5: Layout view of the FBDDA in the buffer configuration 54

72 Figure 5.6: AC response of the fully balanced differential difference amplifier 55

73 Figure 5.7: AC response of the FBDDA in the buffer configuration 56

74 Figure 5.8: Noise response of the FBDDA 57

75 Figure 5.9: Step response of the FBDDA in the buffer configuration 58

76 Figure 5.10: Input 1dB compression point of the FBDDA in the buffer configuration 59

77 Parameter Result Unit Technology 0.5 μm Supply voltage 3 V Open loop gain 60.4 db Phase margin 67-3dB bandwidth 73.6 KHz Gain-bandwidth product 77.3 MHz Noise at 20MHz 9.4 nv/ Hz Input compression point 15 dbm Current consumption 2.77 ma Power consumption 8.3 mw Area μm μm Table 5.1: Performance of the fully balanced differential difference amplifier 5.3 Channel Selection Filter The main purpose of the channel selection filters in wireless receivers is to filter out the blockers and relax the linearity requirement of the receiver. Active RC and gm-c filters are popular choices of channel selection filters. The gm-c filters are more suitable for high frequency applications but it is difficult to achieve high linearity with gm-c filters. On the other hand, active RC filters have better linearity. In this baseband design, an active RC filter topology is employed. Among various kinds of active RC filters, the Sallen-Key filter has been chosen because it has a simple topology and thus occupies less area Fully Differential Sallen-Key Low Pass Filter Fig shows a third-order Sallen-Key low pass filter topology [46][47][48]. It has only one amplifier in the buffer configuration. The unity-gain buffer can be just 60

78 C 2 V i R 3 R 1 R 2 C 3 C 1 V o Figure 5.11: Third-order Sallen-Key low pass filter a source follower in the simplest form of implementation [49]. Fig. 5.11, without R 3 and C 3, it is a second-order Sallen-Key low pass filter. Thus, using the second-order and the third-order Sallen-Key sections, a higher order filter can be most efficiently built with a smaller number of amplifiers. The transfer function of the third-order Sallen-Key low pass filter shown in Fig can be found as V o (s) V i (s) = 1 R 3 C 1 C 2 C 3 s 3 +2R 2 (C 1 C 3 + C 1 C 2 )s 2 + R(3C 1 + C 3 )s +1 (5.6) where R = R 1 = R 2 = R 3. The Sallen-Key filter can be designed with an amplifier whose gain is more than unity [38][48]. However, it is reported that the damping ratio in this case is dependent on the values of resistors that set the closed-loop amplifier gain, thus poles may be less reliably located [48]. Consequently, it is more popular to use a buffer in the Sallen-Key filter implementations so that the filter section has 0dB gain. In the analog baseband systems for wireless communication receivers, usually the gain is obtained by variable gain amplifiers and the channel selection filter has 0 db gain. Now that the single-ended filter structure in Fig cannot be straightforwardly extended to a differential version using a differential op-amp as we discussed 61

79 in Section 5.2, a fully balanced differential difference amplifier (FBDDA) presented in Section 5.2 is employed here to build a fully differential Sallen-Key low pass filter. As shown in Fig. 5.12(a), a third-order fully differential Sallen-Key low pass filter can be readily implemented with a FBDDA in the buffer configuration. To tune the filter, MOS transistors operating in the triode region can be placed in parallel with resistors as shown in Fig. 5.12(b) [6]. That is, the filter tuning can be achieved by varying the gate voltages of the MOS resistors operating in triode region. In addition, the filter can be designed to be programmable for multistandard operation by having another set of resistor chains connected in parallel and reconfigured using switches as shown in Fig So, by varying resistors, we can obtain both the filter tuning and the multistandard operation. Now, by cascading the two fully differential third-order Sallen-Key low-pass filters, a fully differential sixth-order Sallen-Key low-pass filter suitable for multistandard operation is realized in Fig The filter was designed to work with three wireless standards such as Bluetooth, IEEE a, and IEEE b/g. So, R was set to 3.1KΩ for a/b/g and to 48KΩ for Bluetooth. Capacitance values don t change with the standard. C 1 was set to 0.3pF, C 2 to 7pF, and C 3 to 2.77pF Simulation Results The fully differential sixth-order Sallen-Key low-pass filter was designed using the AMI 0.5 μm standard digital process available through MOSIS [45], and simulated using the BSIM3v3 models in Cadence environment. The filter was loaded with 2pF capacitance at each output node. The filter performance in the typical corner is summarized in Table 5.2. The spot noise was 34.5nV/ Hz at 1MHz. The 1dB input 62

80 C 2 R 3 R 1 R 2 V i C 3 C 1 Vo V cm C 3 C 1 V o V i R 3 R1 R2 (a) C 2 C 2 V i R 3 R1 R 2 C 3 C 1 V o V cm C 3 C 1 Vo V i R 3 R 1 R 2 (b) C 2 Figure 5.12: Fully differential third-order Sallen-Key low pass filter using FBDDA 63

81 C 2 R 3 R 1 R 2 V i R 3 R 1 R 2 C 3 C 1 V o V cm C 3 C 1 Vo V i R 3 R 1 R 2 R 3 R 1 R 2 C 2 Figure 5.13: Fully differential third-order Sallen-Key low pass filter for multistandard operation C 2 C 2 R 3 R 1 R 2 R 3 R 1 R 2 R 3 R 1 R 2 R 3 R 1 R 2 V i C 3 C 1 C 3 C 1 V o V cm V cm C 3 C 1 C 3 C 1 V o V i R 3 R 1 R 2 R 3 R 1 R 2 R 3 R 1 R 2 R 3 R 1 R 2 C 2 C 2 Figure 5.14: Fully differential sixth-order multistandard Sallen-Key low pass filter 64

82 compression point in the buffer configuration was 15dBm and the third order input intercept point was 19dBm. The AC response of the fully differential sixth-order Sallen-Key low-pass filter is shown in Fig The frequency response of the filter shows the cut-off frequencies for three wireless standards: 500 KHz for Bluetooth, 10 MHz for IEEE a, and 11 MHz for IEEE b/g. Fig shows a group delay response. Group delay has minimum of 48nsec and 59nsec maximum, so the group delay ripple is 11 nsec. Fig illustrates the noise performance. To test the linearity of the filter, the input 1dB compression point and the third input intercept point (IIP3) were simulated and illustrated in Fig and in Fig. 5.19, respectively. For stability test, the step input was applied into the filter and its step response is shown in Fig One 3rd order filter occupies 617 μm 475 μm and consumes 2.77mA of current. Parameter Result Unit Technology 0.5 μm Supply voltage 3 V Passband gain db -3dB bandwidth 0.5,10,11 MHz Group delay minimum 48 nsec Group delay maximum 59 nsec Noise at 1MHz 34.5 nv/ Hz Input compression point 15 dbm IIP3 19 dbm Current consumption 5.55 ma Area μm μm Table 5.2: Performance of the fully differential sixth-order Sallen-Key low pass filter 65

83 Figure 5.15: AC response of the sixth-order Sallen-Key low pass filter 66

84 Figure 5.16: Group delay response of the sixth-order Sallen-Key low pass filter 67

85 Figure 5.17: Noise response of the sixth-order Sallen-Key low pass filter 68

86 Figure 5.18: Input 1dB compression point of the sixth-order Sallen-Key low pass filter 69

87 Figure 5.19: IIP3 of the sixth-order Sallen-Key low pass filter 70

88 Figure 5.20: Step response of the sixth-order Sallen-Key low pass filter 71

89 5.3.3 Measurement Results A test chip containing the fully differential third-order Sallen-Key low-pass filter with a buffer for measurement was fabricated and measured. Fig shows the schematic view of the submitted chip. The FBDDA was used here for the measurement buffer. Die size was 1.5 mm 1.5 mm, and packaging was done with DIP40 (40 lead dual-inline package), a standard ceramic package by Kyocera available through MOSIS [45]. The chip photo taken from the cavity at the top of the package is shown in Fig and its magnified die photo is shown in Fig The chip was measured on a standard breadboard. The measured frequency responses for a/b/g are shown in Fig The cut-off frequencies were 8MHZ for IEEE802.11a and 8.3MHz for b/g which was reduced by about 20 % due to process variations. Fig shows the third order intermodulation distortion test. Two tones, 1MHz and 2MHz sinusoidal inputs, were applied to the filter and the third order harmonic was measured at 3MHz. The measured IM3 was about -42dBc. 72

90 C 2 R 3 R 1 R 2 V i R 3 R 1 R 2 V cm C 3 C 3 C 1 C 1 Vo V o V i R 3 R 1 R 2 R 3 R 1 R 2 C 2 Figure 5.21: Fully differential third-order Sallen-Key low pass filter with a buffer for measurement 73

91 [db] frequency [Hz] Figure 5.22: Measured frequency response of the fully differential Sallen-Key low pass filter 74

92 [db] frequency [Hz] x 10 6 Figure 5.23: Measured intermodulation test of the fully differential Sallen-Key low pass filter 75

93 Figure 5.24: Die photo of the fully differential Sallen-Key low pass filter with a measurement buffer 76

94 Figure 5.25: Magnified die photo of the fully differential Sallen-Key low pass filter with a measurement buffer 77

95 g m C g m Vin g m i LPF Vout Figure 5.26: Static DC offset canceller 5.4 Static DC Offset Cancellation using DC Feedback Loop In Chapter 4, two kinds of DC offsets were studied and cancellation methods for each kind were discussed. In this section, the design of a DC feedback loop as a static DC offset cancellation is presented. DC feedback loops [13][26][27] are capable of canceling static DC offset as well as slowly varying dynamic DC offset. A DC feedback loop is designed to have the output of the Sallen-Key low pass filter fed back into the input of the filter through a very narrow band feedback element, so the overall transfer function with the DC feedback loop has a high pass pole close to DC. A Gm-C filter provides the narrow band feedback. By varying the value of C, wecan control the high pass cut-off frequency DC Feedback Loop Design Fig is the detailed block diagram of the DC feedback loop which is the static DC offset canceller implemented in this dissertation. The LPF represents the channel selection filter. transconductance cell g mi Often, the output of the mixer is current-mode, so the is to produce the input current for the static DC offset 78

96 M12 Vcmfb Vb1 M5 Vcmfb M13 M10 Vb3 Vn M1 M2 Vp Vb3 M11 Von Vop M8 Vb2 Vb2 M9 M6 M3 M4 M7 (a) Operational transconductance amplifier M5c M6c Vcmfb VCM M1c M2c Von VCM M3c M4c Vop M7c Vbc1 M8c (b) Common-mode feedback circuit Figure 5.27: Implementation of g m cell in the static DC offset canceller 79

97 Figure 5.28: Implementation of capacitance canceller. Another transconductance cell g m included in the feedback path is also to convert the g m -C integrator output into the current so that the feedback current is subtracted from the input current. It is also possible to subtract the signal in the voltage mode if the mixer output is voltage, in which case the additional g m cells are not used. We implemented this DC feedback loop around a fully differential 3rd-order Sallen-Key low pass filter [50]. A fully differential transconductance cell g m used in the static DC offset canceller is shown in Fig. 5.27(a). To increase the output resistance r o, a cascode configuration is employed to achieve the DC gain of 85dB and the -3dB frequency of 11Hz with 10pF. The common-mode feedback circuit shown in Fig. 5.27(b) is used to control the common-mode output voltage. To reduce the parasitic capacitance, the capacitors in the static DC offset canceller have been implemented the way shown in Fig Simulation Results The static DC offset canceller was designed in a standard 0.5 μm CMOSprocess. The frequency response of the gm cell designed is illustrated in Fig which shows the DC gain of 85dB and the -3dB frequency of 11Hz with 10pF. The frequency response of the static DC offset canceller is illustrated in Fig The cut-off frequency of the Sallen-Key low pass filter was set to 10MHz, and the location of the high pass pole was made programmable. By varying the value of capacitance, we can 80

98 change the high pass cut-off frequency easily from 1KHz (with 14pF) to 10KHz (with 1pF) with the reasonable value of capacitance for monolithic integration Measurement Results A test chip containing the static DC offset canceller with a fully differential third-order Sallen-Key low-pass filter and a buffer for measurement was fabricated and measured. Fig shows the schematic view of the submitted chip. The capacitor chain has the capacitance such as C d1 =1pF,C d1 = 3pF, and C d1 = 10pF. The FBDDA was used here for the measurement buffer. Die size was 1.5 mm 1.5 mm, and packaging was done with DIP40 (40 lead dual-inline package), a standard ceramic package by Kyocera available through MOSIS [45]. The static DC offset canceller occupies 330 μm 280 μm and gm cell occupies 112 μm 80 μm. The chip photo taken from the cavity at the top of the package is shown in Fig and its magnified die photo is shown in Fig The chip was measured on a standard breadboard. The measured frequency responses are shown in Fig The high pass cut-off frequencies were 6KHz and 8KHz. 81

99 Figure 5.29: Frequency response of the OTA 82

100 Figure 5.30: Frequency response of the static DC offset canceller 83

101 g m C d1 C d2 C d3 gm C 2 R 3 R 1 R 2 R 3 R 1 R 2 V i g m i C 3 C 1 Vo V cm C 3 C 1 V o V i g m i R 3 R 1 R 2 R 3 R 1 R 2 C 2 Figure 5.31: Static DC offset canceller around the Sallen-Key low pass filter with measurement buffer 84

102 [db] frequency [Hz] Figure 5.32: Measured frequency response of the static DC offset canceller 85

103 Figure 5.33: Die photo of the static DC offset canceller 86

104 Figure 5.34: Magnified die photo of the static DC offset canceller with a buffer for measurement 87

105 5.5 Variable Gain Amplifiers Variable gain amplifiers (VGA) or programmable gain amplifiers (PGA) are one of key blocks in analog baseband systems. The variation of the amplifier gain is necessary in wireless communication receivers because the received signal strength is changing according to the distance between a receiver and a transceiver as well as the wireless channel environment including interferences. The most common and simplest way of implementing a variable gain amplifier using a single amplifier is to employ an inverting amplifier configuration or non-inverting amplifier configuration [37]. As pointed out in Section 5.2, a non-inverting amplifier configuration cannot be converted into a fully differential version easily by the steps described in [38] because none of the op-amp inputs are grounded. One can still use two single-ended op-amps to build a fully differential non-inverting amplifier, which increases area, mismatch, and power consumption. A fully balanced differential difference amplifier (FBDDA) presented in Section 5.2 can ease the design of a fully differential non-inverting amplifier. Thus, a variable gain amplification can be readily designed using the FBDDA as shown in Fig By varying the values of resistors, either R 1 or R 2, we can control the gain of the non-inverting amplifier. For the gain control to be programmable, the resistors need to be controlled by switches. It is easy to develop but the drawback is that the -3 db bandwidth of the VGA is also varying, which is not desirable especially in broadband applications. Fig illustrates the problem of bandwidth reduction in high gain modes. Therefore, it is proposed in this dissertation to use attenuators, in which case the bandwidth is fixed in all gain control modes. 88

106 V cm R1 R2 V i V o V i Vo V cm R 1 R 2 Figure 5.35: Fully differential variable gain amplifier using non-inverting amplifier Fully Differential Variable Gain Amplifier Using Attenuators To have the bandwidth of the VGA unchanged according to the gain variation, we use attenuators in this implementation. The current-mode approach can also give us the constant bandwidth in higher gain modes, we explore the attenuators in this dissertation because it is also easy to realize gain steps below 0 db. As described in Chapter 3, the VGA should be designed to have both amplification and attenuation of the signals to be used for both the receive path and the transmit path, respectively. Fig shows the fully differential VGA designed using attenuators and the FBDDA. To have gains, a fully differential non-inverting amplifier consisting of FBDDA, R 1 and R 2 has been designed. In this design, attenuators consisting of MOS switches and poly resistors have been employed and differential inputs are applied through the attenuators as shown in Fig As we can see in the figure, the attenuator 89

107 Figure 5.36: Frequency response of the VGA using non-inverting amplifier 90

108 V cm R 1 R 2 V i V cm Vo Vo V i V cm V cm R 1 R 2 Figure 5.37: Fully differential variable gain amplifier (VGA) using attenuators and FBDDA is just a voltage divider consisting of resistors. To control the gain, we control the MOS switches so that the input signals to the FBDDA could be attenuated according to the gain setting from the digital signal processing block. At the maximum gain setting, the input signals just go to the amplifier without any attenuation, in which case the signal is amplified by the non-inverting amplifier gain determined by the ratio of R 1 and R 2. Therefore, in this scheme, the -3 db frequency does not change when the gain is varying. By cascading the VGA shown in Fig. 5.37, we can achieve the baseband chain with large gain range Simulation Results The single stage of the fully differential VGA using attenuators as shown in Fig was designed using the AMI 0.5 μm standard digital process and then the 91

109 V cm R 1 R 2 V cm R 1 R 2 V i V cm V cm V i V cm V cm V cm R 1 R 2 V cm R 1 R 2 V cm R 1 R 2 V cm R 1 R 2 V cm R 1 R 2 V cm V cm V cm V o V o V cm V cm Vcm V cm R 1 R 2 V cm R 1 R 2 V cm R 1 R 2 Figure 5.38: Fully differential variable gain amplifier (VGA) chain using attenuators and FBDDAs single stage is cascaded to implement a fully differential VGA having -16 db to 38 db gain range with 6 db gain step. Fig is the schematic view of the fully differential VGA chain. The first three stages are the fully differential VGAs using attenuators and the following two non-inverting FBDDAs are to increase the gain for achieving the necessary gain range. The single VGA stage was loaded with 2 pf capacitance at each output node and simulated using the BSIM3v3 models in Cadence environment. It was designed to have 7.8 db of gain and 33.7 MHz of -3 db bandwidth. The small gain was chosen for the single stage to have enough bandwidth. The resistance values used are such that R 1 =1.7KΩandR 2 = 2.5 KΩ. The single VGA stage consumes 2.77 ma of current and occupies 580 μm 290 μm. The simulation results of the cascaded VGA chain shown in Fig in the typical corner are summarized in Table

110 Parameters Result Unit Technology 0.5 μm Supply voltage 3 V Gain range (6dB step) db -3dB bandwidth 10 MHz Noise at 10MHz 13 nv/ Hz Input compression point 12 dbm IIP3 23 dbm Current consumption 13.9 ma Table 5.3: Performance of the fully differential variable gain amplifier Fig is the frequency response showing the gain range of -16 db to 38 db with 6 db gain step. We can see that the -3 db frequency set to 10 MHz for the IEEE a wireless LAN is the same for all gain settings. The spot noise in the highest gain mode (38 db) at 6 MHz is 13 nv/ Hz and the noise plot is shown in Fig The spot noise at 6 MHz is 386 nv/ Hz with 2 db gain setting. The 1 db input compression point was 12 dbm as shown in Fig and the third order input intercept point was 23 dbm in Fig The step input was applied into the VGA chain at 2 db gain setting and its step response is shown in Fig Measurement Results For a test chip, a fully differential VGA consisting of two single stage fully differential VGAs using attenuators and one non-inverting FBDDA was fabricated and measured. The FBDDA buffer was included for measurement at the end of the VGA chain as shown in Fig The gain range of this VGA chain is -13 db to 23 db with 6dB gain step. The fully differential VGA occupies μm μm and the measurement buffer does μm μm. Die size was 1.5 mm 1.5 mm, and 93

111 Figure 5.39: AC response of the VGA 94

112 Figure 5.40: Noise response of the VGA 95

113 Figure 5.41: Input 1dB compression point of the VGA 96

114 Figure 5.42: IIP3 of the VGA 97

115 Figure 5.43: Step response of the VGA 98

116 V cm R 1 R 2 V cm R 1 R 2 V i V cm V cm V i V cm Vcm V cm R 1 R 2 V cm R 1 R 2 V cm R 1 R 2 V o V o V cm R 1 R 2 Figure 5.44: Fully differential VGA using attenuators and FBDDAs with a measurement buffer packaging was done with DIP40 (40 lead dual-inline package), a standard ceramic package by Kyocera available through MOSIS [45]. The chip photo taken from the cavity at the top of the package is shown in Fig and its magnified die photo is shown in Fig The chip was simulated with 40 pf of capacitive load before submission. The fabricated chip was measured on a standard breadboard. Fig shows the measured frequency responses. Fig shows the third order intermodulation distortion test. Two tones, 1MHz and 2MHz sinusoidal inputs, were applied to the VGA and the third order harmonic was measured at 3MHz. The measured IM3 was about -43.2dBc. 99

117 gain [db] frequency [Hz] Figure 5.45: Measured frequency response of the fully differential variable gain amplifier 100

118 [db] frequency [Hz] x 10 6 Figure 5.46: Measured intermodulation test of the fully differential variable gain amplifier 101

119 Figure 5.47: Die photo of the fully differential variable gain amplifier 102

120 Figure 5.48: Magnified die photo of the fully differential variable gain amplifier with a buffer for measurement 103