DESIGN AND ANALYSIS OF NOVEL CHARGE PUMP ARCHITECTURE FOR PHASE LOCKED LOOP

Transcription

1 DESIGN AND ANALYSIS OF NOVEL CHARGE PUMP ARCHITECTURE FOR PHASE LOCKED LOOP A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology in VLSI Design and Embedded Systems By SWANAND VISHNU SOLANKE ROLL NO. 207EC208 Department of Electronics and Communication Engineering National Institute Of Technology Rourkela

2 DESIGN AND ANALYSIS OF NOVEL CHARGE PUMP ARCHITECTURE FOR PHASE LOCKED LOOP A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology in VLSI Design and Embedded Systems By SWANAND VISHNU SOLANKE ROLL NO. 207EC208 Under the Guidance of Prof. D. P. ACHARYA Department of Electronics and Communication Engineering National Institute Of Technology Rourkela ii

3 National Institute Of Technology Rourkela CERTIFICATE This is to certify that the thesis entitled, Design and Analysis of Novel Charge Pump Architecture For Phase Locked Loop submitted by Swanand Vishnu Solanke in partial fulfilment of the requirements for the award of Master of Technology Degree in Electronics & Communication Engineering with specialization in VLSI Design and Embedded System at the National Institute of Technology, Rourkela is an authentic work carried out by him under my supervision and guidance. To the best of my knowledge, the matter embodied in the thesis has not been submitted to any other University / Institute for the award of any Degree or Diploma. Date: Prof. D. P. Acharya Dept. of Electronics & Communication Engg. National Institute of Technology Rourkela iii

4 Acknowledgement This project is by far the most significant accomplishment in my life and it would be impossible without people (especially my family) who supported me and believed in me. I am thankful to Prof. D. P. Acharya, Professor in the department of Electronics and Communication Engineering, NIT Rourkela for giving me the opportunity to work under him and lending every support at every stage of this project work. I truly appreciate and value him esteemed guidance and encouragement from the beginning to the end of this thesis. I am indebted to his for having helped me shape the problem and providing insights towards the solution. His trust and support inspired me in the most important moments of making right decisions and I am glad to work with him. I want to thank all my teachers Prof. K. K. Mahapatra, Prof. S.K. Patra, Prof. G.Panda, Prof. G.S. Rath, and Prof. S. Meher for providing a solid background for my studies and research thereafter. I am also very thankful to all my classmates and seniors of VLSI lab-i especially Sushant Kr. Pattnaik, Jitendra K Das, Ayaskanta Swain, K Sudeendra Kumar and all my friends especially, Somyakant, Vikas, Pyari Mohan, Prashanth and Dinesh, who always encouraged me in the successful completion of my thesis work. SWANAND VISHNU SOLANKE ROLL No: 207EC208

5 Contents Certificate.ii Acknowledgement...iii Abstract v List of Figures.vi List of Tables.viii Chapter 1 Introduction... 1 Chapter 2 Overview of PLL Theory of PLL Dynamics of Simple PLL Terminology of PLL Types of PLL Non Ideal Effects in PLL Jitter Phase Noise Reference Spur Applications of PLL Chapter 3 Charge Pump PLL Introduction Phase frequency Detector The Charge Pump Theory of Basic Charge Pump PLL Voltage Controlled Oscillator Basic Charge Pump Simulation Simulation Results Non Ideal Effects in Charge Pump Single Ended and Differential Charge Pump Advantages of Differential Charge Pump v

6 3.8.2 Limitations of Differential Charge Pump Limitations of Single ended Charge Pump Analysis of Different Charge Pump Architectures Source Charge Pump a. Design of Current Mirrors for charge Pump b. Simulation Results c. Observations d. Limitations of Source CP Transmission Gate Charge Pump a. Design and Simulation Results b. Observations c. Limitations Chapter 4 Novel CP Architecture Introduction to Self Biased High Swing Cascode Current Mirror Proposed Charge Pump Design and Simulations Observations Limitations Chapter 5 Conclusions Publications References vi

7 Abstract Modern wireless communication systems employ Phase Locked Loop (PLL) mostly for synchronization, clock synthesis, skew and jitter reduction. The performance of PLL affects significantly the signal recovery and system functionality in these systems. Charge pump being one of the important components, decides the functional parameters of PLL. This thesis simulates and analyses some of the major reported charge pump architectures. The present work also proposes an efficient architecture of CMOS charge pump and analyses the design considerations for the proposed circuit. The novel charge pump is designed in Cadence Virtuoso environment and implemented using GPDK090 library of 0.1µm technology and a supply voltage of 1.8V. The performance parameters are compared with other standard and latest charge pump based architectures of PLL. The PLL implemented using proposed charge pump is found to exhibit very low acquisition time of 850ns and consume substantially low power of mW. vii

8 List of Figures Chapter Basic PLL Block Diagram Phase Detector Characteristics Basic Operation of PLL Linear Model of Type I PLL Basic Concepts of PLL Ideal and Jittery Waveforms Frequency Multiplication Use of PLL to Eliminate Skew 19 Chapter Concept of Phase Frequency Detector (PFD) Implementation of PFD PFD Response Basic Charge Pump Architecture PFD-CP-Lop Filter Combination Response of PFD-CP Combination Simple Charge Pump PLL Addition of R p and C 2 to Improve Stability Current Starved VCO VCO Characteristics Implementation of Basic Charge Pump Transient Response of Basic Charge Pump PLL Time Verses Frequency Response of Basic CP-PLL..35 viii

9 3.14 Example of Differential Charge Pump Source Charge Pump Transient Response of Source CP-PLL Time Verses Frequency Response of Source CP-PLL Transmission Gate Charge Pump Transient Response of TG-CP-PLL Time Verses Frequency Response of TG-CP-PLL...46 Chapter Self Biased High Swing Cascode Current Mirror input Output Response of SBHSCCM Proposed SBHSCCM CP transient Response of Proposed CP-PLL Time Verses frequency Response of Proposed CP-PLL 54 ix

10 List of Tables Chapter 4 4(a) Bias current Verses Pull In Time.55 4(b) Comparison of CP Architectures 56 x

11 Chapter 1 Introduction

12 Motivation Phase locked loop, popularly known as PLL [1] is one of the important constituent of modern electronic systems. Having wide range of applications over a broad frequency spectrum PLL has become one of the most essential element [2] in microprocessor boards of complex systems, wired and wireless communication systems and many other systems. Earliest research towards what became known as the phase-locked loop goes back to 1932 [3], when British researchers developed an alternative to Edwin Armstrong's super heterodyne receiver, the Homodyne or direct-conversion receiver. In the homodyne or synchrodyne system, a local oscillator was tuned to the desired input frequency and multiplied with the input signal. The resulting output signal included the original audio modulation information. The intent was to develop an alternative receiver circuit that required fewer tuned circuits than the super heterodyne receiver. Since the local oscillator would rapidly drift in frequency, an automatic correction signal was applied to the oscillator, maintaining it in the same phase and frequency as the desired signal. The technique was described in 1932, in a paper by Henri de Bellescize, in the French journal Onde Electrique. In analog television receivers since at least the late 1930s, phase-locked-loop horizontal and vertical sweep circuits are locked to synchronization pulses in the broadcast signal. When Signetics introduced a line of monolithic integrated circuits that were complete phase-locked loop systems on a chip in 1969, applications for the technique multiplied. A few years later RCA introduced the "CD4046" CMOS Micropower Phase-Locked Loop, which became a popular integrated circuit. Since its invention, the design of PLL has remained challenging because of requirement of fast, low power consuming and less noisy electronic equipments. Charge Pump is one essential part of PLL. Charge pump (CP) converts the phase or frequency 2

13 difference information of two input signal into a voltage which is used to tune a Voltage Controlled Oscillator toward reference input frequency. Other elements of PLL are Phase Frequency Detector (PFD), Low Pass Filter (LPF) and Voltage Controlled Oscillator (VCO). Implementation of LPF is very easy while PFD and VCO can be implemented in static CMOS logic. But being a current driven system, charge pump finds to be more challenging for implementation, since performance of CP directly affects the speed, power consumption and noise behaviour of PLL. Clock feed through, charge sharing, current mismatch are some of the challenges in design of CP. Charge pump is one of the most popular topics in research of solid state electronics, wireless communication etc. and so many different architectures are proposed which claim to be robust and more efficient. The challenges in design of efficient charge pump motivated me towards the research in this field. In this work a novel architecture of CP which is efficient in terms of power consumption, speed and noise is proposed. Outline of the Thesis It is important to understand the whole PLL system before going into the details of CP. Chapter 2 briefly describes the basics of PLL. A mathematical model of PLL is produced in section 2.1 which makes understanding of PLL easier. Since PLL is feedback system, a control theory approach is used to form the mathematical model of PLL. Section 2.2 gives the basic terminology of PLL while in consecutive sections types of PLL, non ideal effects related to PLL, its applications are discussed in brief. Chapter 3 builds the concepts of charge pump. Section 3.2 and 3.3 gives the brief outline of concept of building a charge pump and necessity of PFD. Section 3.4 describes the mathematical theory related to the charge pump PLL. After discussing the basic charge pump architecture in 3.6, its non ideal effects are discussed in section 3.7. In section 3.8 comparison 3

14 between single ended and differential charge pump is given. Section 3.9 briefly discusses the different architectures of charge pump and their performance. The proposed charge pump architecture is described in Chapter 4. An introduction to self biased high swing cascode current mirror is given in section 4.1. Section 4.2 briefly discusses the design and simulation of proposed charge pump. Chapter 5 provides the conclusions that can be inferred out of this work. 4

15 Chapter 2 An overview of PLL 5

16 2.1 Theory of PLL PLL is simple feedback system [4] that compares the output phase with the input phase and produces the output frequency which is proportional to the input phase difference. Since its invention in1932, the basic phase locked loop has remained nearly the same but its implementation in different technologies and for different applications continues to challenge designers. This topic deals with basics of PLL. Fig. 2.1 shows the basic block diagram of PLL. Reference Input Phase Detector Φ LPF V cont VCO F out Fig. 2.1 Basic PLL Block Diagram A phase detector is a circuit whose average output voltage is proportional to the phase difference ϕ, between two inputs. In the ideal case relation between average output voltage and input phase difference is linear, crossing the origin for ϕ=0 as shown in figure 2.2. V out V 1 Φ 1 Φ Fig. 2.2 Phase detector characteristics 6

17 Called the gain of PD is the slope of line, K PD, which is expressed in V/rad. The output of PD is then passed through a low pass filter, so as to remove the high frequency content in PD output voltage. This is required because; the control voltage of oscillator must remain quit in steady state. Filter also provides a memory for the loop in case lock is momentarily lost due to large interference transient. This filtered control voltage is then applied to the input of Voltage Controlled Oscillator. Control voltage forces the VCO to change the frequency in the direction that reduces the difference between input frequency and output frequency. If two frequencies are sufficiently close, the PLL feedback mechanism forces the two PD input frequency frequencies to be equal and the VCO is locked with incoming frequency. This is called as locked state of PLL. Fig. 2.3 depicts the basic operation of PLL. Fig. 2.3 Basic operation of PLL Once the loop is in locked state, there will be small phase difference between the two PD input phase signals. This phase difference results in a dc voltage at the phase detector 7

18 output which is required to shift the VCO from its free running frequency to input frequency and keeps the loop in locked state Dynamics of simple PLL A linear model of PLL can be constructed mathematically by considering figure 2.4, which shows the linear model of type I PLL. Low pass filter is assumed to be of first order for simplicity. PD LPF VCO Φ in K PD s ω LPF K VCO s Φ out Fig. 2.4 Linear model of type I PLL The PD output contains a dc component equal to K PD (Φ out -Φ in ) as well as high frequency components which are filtered by the LPF. PD is simply modeled as a subtractor whose output is amplified by K PD. The overall PLL model consists of the phase subtractor, the LPF transfer function 1/(1+ s/ω LPF ), where ω LPF is the 3 db bandwidth and the VCO transfer function K VCO /s. Here, Φ in and Φ out are the excess phases of input and output waveforms, respectively. The open loop transfer function is given by H s open = Φ out Φ in s open = K PD 1 1+ s K VCO s ω LPF (2.1) 8

19 From (2.1) closed loop transfer function can be obtained as: H s closed = K PD K VCO (2.2) s 2 +s+k ω PD K VCO LPF Here H(s) closed is simply denoted by Φ out / Φ in. Further, since the frequency and phase are related by a linear operator, the transfer function of (2.2) can be expressed as: ω out K (s) = PD K VCO (2.3) ω s 2 in +s+k ω PD K VCO LPF This is second order transfer function of type I PLL. Using the control theory approach the natural frequency and damping ratio are given by: ω n = ω LPF K PD K VCO (2.4) ζ = 1 2 ω LPF K PD K VCO (2.5) The step response is given by: ω out t = ζ 2 e ζω n t sin ω n 1 ζ 2 t + θ Δωu t (2.6) Where ω out denotes the change in output frequency and θ = sin 1 1 ζ 2. Thus, as per control theory approach, we can say that, the step response will contain a sinusoidal component with frequency ω n 1 ζ 2 that will decay with time constant ζω n 1. 9

20 Referring to above discussion it can be concluded that: 1. Settling speed of PLL is of great concern in most applications. Equation (2.6) thus, shows that the exponential decay determines how fast the output approaches its final value, provided that ζω n is maximized. Using equation (2.4) and (2.5), yields, ζω n= 1 2 ω LPF (2.7) This result shows the critical tradeoff between settling speed and ripple on the VCO control line. If we reduce the cutoff frequency of filter, greater high frequency components are suppressed but at the same time pull in time increases. 2. In addition to value of ζω n, value of ζ is also important. If ζ is less than typically 0.5, step response exhibits high amplitude oscillations before settling. Hence in order to avoid this ringing, the value of damping ratio is normally kept or even greater than or equal to Equation (2.5) shows that both phase error and ζ are inversely proportional to K PD and K VCO. Hence lowering the phase error makes the system less stable. Thus in summary the simple PLL (type I) has a drawback of trade off between the pull in time, the ripple on the control voltage, the phase error and the stability. 2.2 Terminology of PLL 1. Lock range: The range of input signal frequencies over which the loop can maintain the lock is called as Lock Range or Tracking Range of PLL. 10

21 2. Capture range: The range of input signal frequencies over which PLL can acquire a lock is called as Capture Range or Acquisition Range of PLL. Capture range depends on the amount of the gain in a loop itself and the loop filter bandwidth. Reducing the loop filter bandwidth thus improves the rejection of the out of band signals, but at the same time the capture range decreases, pull in time becomes larger and phase margin becomes poor. Fll Lock Range Flu Capture Range VCO natural Frequency Fcl Fcu Fn Fig.2.5 Illustration of Terminologies of PLL 11

22 3. Pull in time: The total time taken by the PLL to capture the signal (or to establish the lock) is called as Pull in Time of PLL. It is also called as Acquisition Time of PLL. 4. Band width of PLL Bandwidth is the frequency at which the PLL begins to lose the lock with reference. 2.3 Types of PLL Several types of PLL [5] architectures are available in market. The architectures broadly range according to the application. These different architectures of PLL can be considered as different types of PLL. Following types of PLL are classified according to their application. 1. Programmable PLL: This type of PLL can be programmed for wide range of signals. 2. Single and multi-phase PLL: These can control a single or many phases. They are used in digital clock networks. 3. Digital Phase Locked Loop: They are used digital input signals for application like Manchester coding. 4. PLL with lock detector: It uses a lock on one of the pins and is used in frequency modulation. 5. PLL frequency synthesizer: These are used to synthesize the frequency of different range and band. 6. PLL FM/AM demodulator: The FM/AM radio frequencies are modulated and demodulated using this type of PLL. 7. Single RF/ Multi RF PLL: It is used for controlling single or multiple radio frequencies. 12

23 8. Super PLL: It is used for frequency synthesizing of radios, networks of GSM, cordless phones, etc. PLLs are also classified according to the type of loop filter used in architecture. The order of loop filter is the type of PLL. For example, if 1 st order loop filter is used, then it is called as type I PLL. If 2 nd order filter is used, it is called as type II PLL and so on. If PLL uses simple Phase detector in its architecture, it is called as simple PLL. But if PLL uses Phase Frequency Detector accompanied with Charge Pump, it is called as Charge Pump PLL. 2.4 Non Ideal Effects in PLL So many imperfections always remain in practical PLL circuit. These lead to high ripple on the control voltage even when the loop is locked. These ripples modulate the VCO frequency, which results in non periodic waveform. This section considers these non ideal effects in PLL [4] [6] [7] Jitter in PLL A jitter is the short term-term variations of a signal with respect to its ideal position in time. This problem negatively impacts the data transmission quality. Deviation from the ideal position can occur on either leading edge or trailing edge of signal. Jitter may be induced and coupled onto a clock signal from several different sources and is not uniform over all frequencies. Excessive jitter can increase bit error rate (BER) of communication signal. In digital system Jitter leads to violation in time margins, causing circuits to behave improperly. Common sources of jitter include: Internal circuitry of PLL Random Thermal noise from crystal 13

24 Other resonation devices Random mechanical noise from crystal vibration Signal transmitters Traces and cables Connectors Receivers The response of PLL to jitter is very important in most applications. Figure 2.6 explains the jitter in PLL. As shown in figure 2.6, a strictly periodic waveform, x1(t), contains zero crossings that are evenly spaced in time. Now consider nearly periodic signal x2(t), whose period experiences a small changes, deviating the zero crossing from their ideal points. Hence we can say that x2(t) suffers from jitter. If the instantaneous frequency of signal varies slowly from one period to next period, then it is called as slow jitter, and if the variation is fast, it is called as fast jitter. Fig. 2.6 Ideal and Jittery Waveforms 14

25 In PLL two types of phenomena are considered. a) The input exhibits jitter and b) The VCO produces jitter. In first case, the transfer function derived for type I and type II PLLs have a low-pass characteristics, indicating that if Φ in (t) varies rapidly, then Φ out (t) does not fully track the variations. That means, slow jitter at the input propagates to the output unattenuated but fast jitter does not. That is, PLL low pass filters Φ in (t). Now suppose VCO suffers from jitter. If PLL is modelled for transfer function of Φ out /Φ VCO for type II, the transfer function depicts the high pass characteristics. That is, slow jitter components generated by VCO are suppressed but fast jitter components are not. If Φ VCO changes slowly, then the comparison with perfectly periodic input waveform generates slowly varying error that propagates through LPF and adjusts the VCO frequency, thereby counteracting the change in Φ VCO. On other hand if Φ VCO varies rapidly, then error produced by the phase detector is heavily attenuated by the poles in loop, failing to correct the change Phase Noise Phase noise is random variation of phase of the signal. It is the frequency domain representation of rapid, short term fluctuations in the phase of the wave, caused by time domain instabilities ( jitter ). Generally the phase noise and jitter are closely related. Or more specifically, radio engineer call it as phase noise, but digital system engineer call it as jitter of the clock. Phase noise is of very much concern in PLL, since it directly affects the entire performance of the system. Following are the common sources of phase noise in PLL. i) Oscillator noise: There are two oscillators that contribute to the phase noise of the PLL. One is the reference oscillator and other is the VCO. Although both oscillators can be modelled similarly, their effects on the output noise are distinct just due to their position in the loop. Suppose a noise less VCO is added with AWGN with 15

26 DSPSD of N o /2. Then the output power spectrum is given by KVCO 2 (N o /2ω 2 ). Though it is very simplified equation, it clearly gives the idea of output noise of PLL in the presence of VCO noise. The reference oscillator is also assumed to have sufficient behaviour with different constant of proportionality. ii) Frequency Divider noise: The excess noise of a digital divider can be modelled as additive noise source at its output. In a PLL, this noise directly appears at the input of phase detector and experiences the same transfer function as the noise on the input terminal. iii) Phase detector noise: Usually phase detectors are not major sources of noise in PLLs. As the work of PD is to detect the phase difference, any random variation in the phase of input signal makes the phase detector to produce wrong output, which is get transferred through filter and tunes the VCO wrongly Reference spur Reference spurs are spurious emissions that occur from the carrier frequency at an offset equal to the channel spacing. These are usually caused by leakage and mismatch in charge pump of PLL. Though they occur outside the band of interest, they can enter the mixers and be translated back onto band of interest. Reference spur mainly occurs in Charge Pump PLL. Though there is no phase difference between reference and feedback signal, in the locked state, the phase detector (or phase frequency detector) produces very narrow pulse width error voltage which drives the charge pump. Although these pulses have a very narrow width, the fact that they exist means that the dc voltage driving the VCO is modulated by a signal of frequency equal to input reference frequency. This produces reference spurs in the RF output occurring at offset frequencies that are integer multiples of input reference frequency. A spectrum analyzer can be used to detect reference spurs. Simply increase the span to greater than twice the reference frequency. 16

27 Let I cp is charge pump current, I leak is leakage current in CP then the phase offset is given by: Φ ε = 2π I leak I cp [rad] (2.8) Now if f REF is the input reference frequency, f BW is loop bandwidth, f pl is the frequency of pole in loop filter and N is the division value then the amount of reference spur in 3 rd order PLL is given by: P r = 20 log 1 2 f BW f ref N Φ ε 20 log f ref f pl [dbc] (2.9) If reference spur is not enough to meet the requirement, the loop bandwidth should be further narrowed or charge pump current should be increased. It is also helpful to reduce the division value to relax the charge pump design. 2.5 Applications of PLL Since its invention, PLL continues to find new applications in electronics, communication and instrumentation. Examples include memories, microprocessors, hard disk drive electronics, RF and wireless transceivers, clock recovery circuits on microcontroller boards and optical fibre receivers. Some of the applications are as follows [4]. Frequency multiplication and synthesis A PLL can be modified such that it multiplies its input frequency by factor of M. Figure 2.7 shows basic frequency multiplication concept. 17

28 f in PFD CP/LPF VCO f out f D M Fig. 2.7 Frequency Multiplication Just like a voltage divider is used in feedback in voltage amplifier, as shown in figure 2.7, output frequency of PLL is divided by M and applied to the phase detector, we get, f out =M f in. Also, since f in and f D must be equal, PLL multiplies f in by M. Some systems require a periodic waveform whose frequency (a) must be very accurate and (b) can be varied in very fine stapes. Hence to synthesise a required frequency, a channel control word (digital) is applied to divider block in feedback that varies the value of M. Since f out = M f REF, the relative accuracy of f out is equal to that of f REF. It is also notable that f out varies in stapes equal to f REF if M changes by one each time. Skew reduction This is one of the very popular and earliest uses of PLL. Suppose synchronous pair of data and clock lines enter a large digital chip. Since clock typically drives a large number of transistors and logic interconnects, it is first applied to large buffer. Thus, the clock distributed on chip may suffer from substantial skew (delay due to buffer insertion) with respect to data. This is an undesirable effect which reduces the timing budget for on-chip operations. Now consider the circuit as shown in figure 2.8. Here input clock CK in is applied to on chip PLL and buffer is placed inside the loop. Since PLL guarantees a nominally zero phase 18

29 difference between CK in and C KB, the skew is eliminated. That is, the constant phase shift introduced by the buffer is divided by infinite loop gain of the feedback system. Alignment of V VCO with CK in is not important since V VCO is not used. Fig 2.8 Use of PLL to Eliminate Skew. 19

30 Chapter 3 Charge Pump PLL

31 3.1 Introduction Charge pump is one of the important parts of PLL which converts the phase or frequency difference information into a voltage, used to tune the VCO. Before arriving at the concept of charge pump, the problem of simple PLL which uses phase detector is discussed here. Limitations of Simple PLL architecture For type I PLL there are always trade-offs between damping ratio of loop filter, loop filter bandwidth and the phase error. Hence the performance of PLL cannot improve beyond certain limit. Apart from this, a simple PLL suffers from a critical drawback i.e. limited acquisition range [4] Suppose when a PLL circuit is turned on, its oscillator operates at a frequency far from the input frequency, i.e., the loop is not locked. Now PLL starts acquiring a lock. The transition of the loop from unlocked to locked condition is very nonlinear process because phase detector senses unequal frequency. Also for this kind of PLL, the acquisition range is on the order of ω LPF, that is, the loop locks only if the difference between ω in and ω out is less than roughly ω LPF. If ω LPF is reduces to suppress the ripple on control voltage, the acquisition range decreases. Even if the input frequency has a precisely controlled value, a wide acquisition range is often necessary because the VCO frequency may vary considerably with the process and temperature. Hence in order to remove this problem, frequency detection is also incorporated in addition to phase detection. The concept is such that let the two frequencies (reference and VCO output frequency) be equal, once these two frequencies are equal, phases are compared and VCO is tuned such that phases of reference and feedback waveform are equal. Frequencies are compared using frequency detector which generates a dc voltage equal to the difference of two input frequency and drives the VCO such that ω in = ω out. When ω in -ω out is 21

32 sufficiently small, phase locked loop takes over, acquiring lock. Such scheme increases the acquisition range to the tuning range of VCO. 3.2 Phase frequency detector For the periodic signal it is possible to merge the phase and frequency detector, such that it can detect both phase and frequency. It is called as phase-frequency detector (PFD) [4] [8] and illustrated conceptually in figure 3.1. Suppose two waveforms A and B arrive at input pins with equal frequency but unequal phases such that A leads B. As A goes high, output Q A goes high. When leading edge of B comes, Q A goes to zero while Q B does not show any change and remains low. Exactly opposite thing happens when B leads A. Thus output QA continues to produce pulses whose width is proportional to Φ A - Φ B while Q B remains at zero. Now as shown in figure 3.1(b), suppose A has higher frequency than B and also A leads B, then Q A continues to produce the pulses with unequal width and Q B remains quite and vice versa. Thus, the dc contents of Q A and Q B provide information about phase or frequency difference. Outputs Q A and Q B are called the UP and DOWN pulses, respectively. Fig. 3.1 Concept of Phase Frequency Detector (PFD) 22

33 VDD A D SET Q Q A CLR Q Reset AND B D SET Q Q B CLR Q Fig. 3.2 Implementation of PFD Figure 3.2 shows the implementation of PFD. It consists of two edge triggered resettable D flipflops with their D inputs tied to logical ONE. Inputs A and B serve as clock of flipflops. If QA=QB=0 and A goes high, QA rises. If this event is followed by a rising transition on B, QB also goes high and the AND gate resets both flipflops. In other words, QA and QB are simultaneously high for a short time but the difference between their average values still represents the input phase or frequency difference correctly. Figure 3.3 shows the operation of phase frequency detector. Fig. 3.3 PFD Response 23

34 It is just seen, that PFD effectively converts the input phase or frequency difference information into the proportional UP and DOWN pulses. But, how to utilise this information to generate a voltage which is used to the VCO? Since the difference between the average values of QA and QB is of interest, the two outputs can be low pass filtered and sensed differentially. However a more common approach is to interpose a CHARGE PUMP between PFD and LPF. 3.3 The Charge Pump A charge pump [4] [9] is a three position electronic switch which is controlled by the three states of PFD. When switch is set in UP or DOWN position, it delivers a pump voltage ±V P or a pump current ±I P to the loop filter. When both UP and DOWN of PFD are off, i.e. N position, the switch is open, thus isolating the loop filter from the charge pump and PFD. Figure 3.4 shows the basic charge pump. VDD I up UP S1 Vcont C p DOWN S2 I dn Fig. 3.4 Basic Charge Pump Architecture. Figure 3.4 shows the combined architecture of the charge pump and loop filter. Current sources I up and I dn are identical. Two outputs of PFD Q A and Q B are given to the UP and DOWN inputs of charge pump (CP) respectively. Capacitor C p serves the purpose of loop filter. Figure 3.5 shows the CP accompanied with PFD and loop filter. 24

35 VDD Iup VDD A D SET Q Q A UP S1 CLR Q Reset AND Vcont C p B D SET Q Q B DOWN S2 CLR Q Idn Fig. 3.5 PFD-CP-Loop Filter Combination If Q A =Q B =0, then S1 and S2 are off and V out (or V cont ) remains constant. If Q A is high and Q B is low, then I up (UP current) charges C p. Conversely if Q A is low and Q B is high, then I dn (DOWN current) discharges C p. Hence, if suppose, A leads B, then Q A continues to produce pulses and V cont rises steadily. Figure 3.6 shows the response of PFD-CP combination. Fig. 3.6 Response of PFD-CP combination 25

36 3.4 Theory of Basic Charge Pump PLL The basic PLL using charge pump PLL [4] is discussed here. Figure 3.7 shows such construction. VDD VDD Iup V in Φ in ω in D SET CLR Q A Q Q Reset AND UP S1 Vcont C p VCO V out Φ out ω out D SET Q Q B DOWN S2 CLR Q Idn Fig. 3.7 Simple Charge Pump PLL The reference input is given to the one of the PFD while VCO output is given to another input. This implementation senses the transition at the input and output detects phase or frequency difference and activates the charge pump accordingly. When loop is turned on, ω out may be far ω in, and the PFD and charge pump vary the control voltage such that ω out approaches ω in. When input and output frequencies are sufficiently close, the PFD operates as phase detector, performing phase lock. Now consider a case, that Φ out Φ in drops to zero. In this case PFD simply produce Q A = Q B = 0. The charge pump thus remains idle and Cp sustains a constant control voltage. But this does not mean that PFD and CP are no longer needed. If V cont remains constant for a long time, the VCO frequency and phase begin to drift. In particular, the VCO create random variations in the oscillation frequency that can result in large accumulation of phase error. The PFD then detects the phase difference, produces corrective pulses on Q A or Q B that 26

37 adjusts the VCO frequency through charge pump and filter. Also, as phase comparison is performed in every cycle, the VCO phase and frequency cannot drift substantially. Let`s construct the mathematical model for simple CP-PLL. Let the two different signals arriving at A and B have equal frequency but unequal phase. Let T ref is time period of reference input and Δt is the time difference between signal A and signal B. The phase difference (or phase error) between two input signals is given by: ΔΦ = Δt T ref (3.1) The phase difference is zero when loop is locked. Hence referring the Fig. 2.2, the output voltage of PFD is given by: V PFD = VDD 0 4π ΔΦ (3.2) Hence the gain of PFD is given by: K PFD = VDD 4π [volts/rad] (3.3) The output of the PFD is then given to the charge pump. The operation of which is already described in section 3.2. Referring to this discussion we say that the characteristic of I P (charge pump current, Up or Down) is of Signam function I P = I P sgn(δφ). That is, I P is +I P if ΔΦ is positive and Ip is -I P if this phase error is negative. Now in locked condition of PLL, the ON time of UP or DOWN switch is given by: t p = ΔΦ 2πf in s (3.4) Then the current delivered to the filter C p for the time t p on each cycle is given by: 27

38 I d = I P ( I P ) 4π ΔΦ (3.5) K PFD = I P 2π (3.6) Thus the control voltage generated across the CP is given by: V c s = I d s Z c s = I P 2π 1 Z c s ΔΦ = K PFD CP ΔΦ (3.7) K PFD CP = I P 2πC p [Volts/rad] (3.8) Now suppose in a locked condition, suddenly ΔΦ = ΔΦ o u(t) phase difference is introduced. Q A will produce the pulses which are Δt =ΔΦ T/2π sec wide which leads to output to rise by (I P /C P ) (T/2π) (ΔΦ) in every period. Approximating this to a ramp voltage we can write: V c t = I P 2πC p ΔΦ t u(t) (3.9) This leads to impulse response: t = I P 2πC p u(t) (3.10) Hence the transfer function of PFD-CP-Filter combination is given by: V cont ΔΦ s = I P 2πC p 1 s (3.11) This output of PFD-CP-Filter combination is then given to the VCO with transfer function as (K VCO /s). Hence referring the model given in section 2.1 with Figure 2.4 we can write the open loop transfer function of simple Charge Pump PLL as: 28

39 Φ out Φ in s open = I P 2πC p K VCO s 2 (3.12) Since the open loop gain has two poles at origin, this topology is called as type II PLL. The closed loop transfer function is given by: H s = I P K VCO 2πCp s 2 + I P K VCO 2πCp (3.13) This result is alarming, because closed loop system contains two imaginary poles and therefore unstable. In order to stabilise the system, we add a zero in the loop gain by adding a resistor R p in series with the loop filter capacitor. This system is shown in figure 3.7 with additional capacitor C 2 whose purpose will be explained later. The PFD-CP-Filter now has the transfer function: V cont ΔΦ s = I P 2π R p + 1 C p s (3.14) Thus the closed loop transfer function of this system becomes: H s = I P K VCO 2πCp (R p c p s+1) s 2 + I P 2π K VCO R p s+ I P 2πCp K VCO (3.15) The closed loop system contains a zero at s z = -1/(R p C p ). The natural frequency and the damping ratio are given as: ω n = I P K VCO 2πC p (3.16) ζ = R p 2 I P C p K VCO 2π (3.17) 29

40 As expected, if R p =0, then ζ =0. With complex poles, the decay time constant is given by 1/(ζ ω n ) = 4π /(R p I P K VCO ). As seen from the equation 3.15 if we decrease the I P K VCO, the gain crossover frequency decreases (or shifts toward the origin), degrading the phase margin. But this compensated type PLL suffers from a drawback. Since the charge pump drives the series combination of R p and C p, each time a current is injected into the loop filter, the control voltage experiences a large jump. Even in the locked condition, mismatches between I up and I down and the charge pump injection and clock feed through of S 1 and S 2 introduce voltage jump in V cont. VDD VDD Iup V in Φ in ω in D SET CLR Q A Q Q Reset AND UP S1 C p Vcont VCO V out Φ out ω out D SET Q Q B DOWN S2 R p C 2 CLR Q Idn Fig. 3.8 Addition of R P and C 2 to Improve Stability The resulting ripple severely disturbs the VCO, corrupting the output phase. To solve this problem, a second capacitor C 2 is usually added in parallel with R p and C p, suppressing the initial step. The loop filter is now of second order, yielding a PLL of type III. Generally C 2 if about one-fifth to one-tenth of C p and does not affect the closed loop time and frequency response. Figure 3.8 shows the third order PLL construction. 30

41 3.5 Voltage Controlled Oscillator Voltage controlled oscillator [10] is one of the important elements of PLL. Since, here our aim is to study charge pump, without going into the details of VCO theory, its parameters used in design, are directly given. VCO type: Current Starved 5 stage VCO Range of VCO: 170 KHz to 170 MHz approximately. Central frequency: 110 MHz VCO gain: MHz/V for the range 0.7 V to 0.9V MHz/V for the range 0.2 V to 1.8V Central frequency bias current: 60 μa. W/L ratios: M6, M4, M10 : 0.4μ /3μ M3, M9 : 1.2μ/0.1μ M2, M8 : 0.6μ/0.1μ M5, M1, M7.: 0.4μ/2μ Figure 3.9 shows the circuit diagram and Figure 3.10 shows the characteristics of VCO VDD M6 M4 M10 M3 M9 F out M2 M8 V cont M5 M1 M7 Fig. 3.9 Current starved VCO 31

42 Frequency (Mhz) 180 VCO output characteristics Control voltage (V) Fig VCO characteristics 3.6 Basic Charge Pump The properties and problems related to charge pump architectures are discussed here. It is well known that a transistor biased with a constant voltage in saturation, works as constant current source. Also a MOSFET can work as a high speed switch. Using these basic concepts, the basic charge pump constructed is shown in figure As shown in figure 3.11, switch S 1 is implemented using PMOS M3 while UP current source is implemented using the fixed biased M4. Similarly for discharging circuit M2 serves as switch S 2 and M1 serves as DOWN current source. Inverter is inserted so that M3 will be on when Q A is high. But insertion of inverter introduces a delay in path thereby introducing a skew between Q A and Q B. To eliminate this effect, a pass transistor gate is inserted between QB and M2. Hence delays of inverter and pass transistor gate become equal. 32

43 VDD V bp M4 I up A QA UP S 1 M3 B PFD QB VDD S2 M2 DOWN Vcont C1 R1 C2 I down V bn M1 Fig Implementation of Basic Charge Pump Simulation Studies All circuits in this work are implemented using Cadence tool in Virtuoso Analog Design Environment. The library used is GPDK090 with 100nm technology. All the circuits are simulated using Spectre simulator tool. The voltage supply used is 1.8V. Reference frequency is kept at 40MHz and simulation is run for 10μs Results and Discussion The PLL is implemented using the basic charge pump shown in figure The simulation is run for 10μs transient time period. Figure 3.12 shows the transient response of basic charge pump PLL while figure 3.13 shows the time verses frequency response of PLL. As seen in figure 3.12, the output frequency of PLL is initially away from the reference input frequency. The PFD then produces the pulses, such that CP-LPF combination drives the VCO towards the reference input frequency. Control voltage starts increasing and once the loop is locked, it remains relatively stable. As discussed earlier, this transition is nonlinear 33

44 phenomenon which is clearly seen in figure It can also be seen that the loop is locked at 20MHz instead of 40MHz, which it should. Causes of this behaviour will be discussed in the next section. To conclude, we say that the basic charge pump and PLL is implemented using the Cadence tool and simulation is run. PLL is in fact failed to acquire a lock. The power consumption is found as mW and current mismatch is found to be around 76μA. The value of reference spur is found to be dbc. Fig Transient Response of Basic Charge Pump PLL Fig Time Verses Frequency Response of Basic CP-PLL 34

45 3.7 Non Ideal Effects in Charge Pump If observed carefully in Fig. 3.12, it is clear that, PLL is locking at 20MHz rather than at 40MHz, which it should. Why is it happening? This is the result of non ideal effects in CP [4] [11]. This issue discussed below. 1. As shown in Fig switches are constructed using PMOS and NMOS. The inherent mismatches between these two switches results in mismatch in charging and discharging current in addition to timing mismatch. Hence there is variation in control voltage at the output. In fact the W/L ratios are adjusted so as to have equal UP and DOWN currents. Even though, about 73μA mismatching is observed between these currents in simulation. That means, since two current sources are themselves mismatched, the control voltage experiences the random changes in it. 2. There is also problem of charge sharing between output node of CP (in fact between filter capacitor) and the parasitic capacitances between drain and source of switch transistors. This results in sudden change in control voltage which may disturb the VCO. 3. Another effect is clock feed through. The high frequency signal provided at the gate of switch transistor passes to the output node via gate to drain parasitic capacitor C gd. This also results in jumps in control voltage. Since the VCO sensitivity is high, even a small jump in control voltage results a large jump in output frequency. If we observe the control voltage in figure 3.12, after roughly 3.5μs loop stabilizes. Though control voltage is relatively stable, there are small jumps in it which can be clearly seen in the transient response. This is the effect of clock feed through as well as charge sharing. The result is sudden jump in output frequency which we can see in the figure 3.13 after 4μs approximately. 35

46 4. Another effect is limited output voltage. If we want higher output voltage the current source value must be increased. This is not possible in every condition, since that increases power consumption also. In fig. 3.12, control voltage rises only up to some 550mV, but desired value is around 632mV for 40MHz. Hence PLL fails to acquire the lock. Apart from this reference spur in PLL is also one of the critical problem which arises due to current mismatches in charge pump. Referring to the section 2.4 (c) of reference spur, equation 2.8 can be modified as: Φ ε = 2π Δt on T ref Δi I (3.18) Where Δt on is turn on time of PFD, T ref is reference time period, Δi is charge pump current mismatch and I is charge pump current. The equation 2.9 remains unchanged. To remove the non ideal effects in CP, so many different architectures are proposed. In practice charge pumps are roughly classified into two categories. Single ended charge pump and Differential charge pump. 3.8 Single Ended and Differential Charge Pumps In single ended charge pump [11] only two inputs UP and DOWN are given to the respective switches, while in differential charge pump two outputs of PFD are given to the two differential switches with each input inverted and given to the second input of the respective switch[11]. Figure 3.14 shows one of the examples of differential charge pump. 36

47 VDD M5 M6 V out UP M3 VDD M4 UPb DNb VDD M2 M1 DN DC I CP DC I CP Fig Example of Differential Charge Pump Without going into the details of differential charge pump, the advantages and limitations of differential charge pump are listed below Advantages of Differential Charge Pumps 1. The switching mismatch between NMOS and PMOS does not affect the overall performance substantially. The matching requirement between NMOS and PMOS transistors are relaxed to the matching between NMOS or between PMOS transistors respectively. 2. The differential CP uses switches using NMOS and the inverter delays for UPb and DNb signals do not generate any offset due to its fully symmetric operation. 3. This configuration doubles the range of output voltage compliance compared to single ended charge pump. 4. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. 37

48 3.8.2 Limitations of Differential Charge Pumps Though differential CP has many advantages listed above, they suffer from critical drawbacks. They require two loop filters and common mode feedback circuitry. Since more number of transistors are required, with two or more current sources, they occupy large silicon area. This also leads to higher power consumption Limitations of Single Ended Charge Pumps 1. Switch mismatch, clock feed through, charge sharing problems are still not eliminated fully. 2. Limited output voltage compliance range. For source CP shown above if we want higher output voltage we have to increase the charging and discharging current values. 3. Switch mismatch also results in timing mismatch as well as dead zone. 4. Parasitic capacitances are dominant in single ended CP. Using of OPAmp may solve above mentioned problems; but designing of OPAmp it itself tedious process and also increases unnecessary hardware. Even though single ended charge pump has these disadvantages, they are more popular than differential design, because they do don t require two loop filter and offer tri state operation with lower power consumption. Also the problems listed above are not those much difficult to handle. With proper modification into the architecture, these problems can be eliminated or minimised easily. Also, single ended charge pumps require fewer components than differential charge pumps; hence they occupy less area in a chip. In the next session we will discuss the different architectures of single ended charge pumps with their simulation and comparison. 38

49 3.9 Analysis Different Single Ended Charge Pump Architectures To remove the non ideal effects in basic charge pump as well as in single ended charge pump many topologies are proposed. Here we will discuss two topologies among them which briefly cover all required aspects of charge pump Source Charge Pump Figure 3.15 shows the source charge pump [11]. The topology uses simple current mirrors to generate charging and discharging current from two identical current sources. Switches are placed at the source of current mirror MOS transistor as shown in figure. VDD UP M4 M2 I DN DC V out I UP DC M1 M3 DN Fig Source Charge Pump The advantage of this kind of topology is that, transistors M1 and M2 are always guaranteed to be in saturation, since combinations M1-M3 and M2-M4 form the current mirrors. The g m (transconductance) of M3 and M4 does not affect the switching time. This architecture gives the faster switching time than other topologies in which switches are implemented at the drain or gate terminals of the transistors; since the switch is connected to single transistor with lower parasitic capacitance. 39

50 a. Design of current mirrors for source CP The gate terminal of both M3 and M4 are tied to their respective drain terminal. Hence these two transistors go into hard saturation. Here we use the principle that, if gate source potentials of two identical MOS transistors are equal, the channel currents should be equal. Now, V DS3 = V GS3 = V GS1, (assuming negligible switch resistance). Thus from circuit, neglecting channel length modulation, we can write that: I DN = k 3 W 3 V 2L GS3 V 2 T = I D1 = k 1 W 1 V 3 2L GS1 V 2 T (3.19) 1 Since transistors are identical, hence we can write that: I DN I D1 = W 3/L 3 W 1 /L 1 (3.20) By similar ideology we can write that: I UP I D2 = W 4/L 4 W 2 /L 2 (3.21) The small signal output resistance is given as: r out = 1 g ds (3.22) From equation 3.22 it is clear that simple current mirror exhibits poor output resistance. b. Simulation results Simulation is performed for source charge pump in Spectre simulator. Reference input frequency is kept at 40MHz. Figure 3.16 shows the transient response while figure 3.17 shows the time verses frequency response of source CP-PLL 40

51 Fig Transient Response of Source CP-PLL Fig Time Verses Frequency Response of Source CP-PLL c. Discussions a. If figure 3.16 is carefully observed, it will be seen that the ripples in the control voltage in the locked state of PLL are drastically reduced. b. Also CP builds enough voltage (632 mv in fact) to tune the VCO to the reference input frequency. 41

52 c. Loop roughly locks into 4μs. d. The power consumption was found to be mw, which is quite higher. The bias current requirement is found to be 500μA. e. Mismatch in UP and DOWN currents is found to be 70μA. The reference spur value is found to be dbc. d. Limitations of Source CP a. The simple current mirror used in this topology has low output impedance. To have output current constant over a supply range the output impedance of current mirror must be high. b. Also it is observed that, if we want optimum output voltage across the CP as well as optimum pull in time of PLL, the bias current requirement is also high (500μA current is required here). c. Two current sources are required here, which add further power consumption, because large number of transistors are required building a constant current source. d. The mismatch between PMOS and NMOS is not fully removed. Also the clock feed through effect is not minimised fully. Considering all these limitations, in next section we will consider a new topology in which these limitations are tried to remove Transmission Gate Charge Pump Many architectures were proposed to reduce the non ideal effects in charge pump. Transmission gate charge pump is one of such proposed topology. Following points were considered while designing this topology. 42

53 1. If we derive both UP and DOWN current from same current source, the inherent current mismatch can be minimised. This also removes requirement of two current sources, hence also reduces power consumption. 2. Use of high output impedance current mirror, so that there is no variation in charging and discharging currents. 3. If we use transmission gate switches instead of normal NMOS or PMOS switches, switching time will increase as well as we can remove switching mismatch. Figure 3.18 shows the Transmission Gate CP topology [12]. VDD T3 T UP UP UPb M4 M5 I Ref DC REF Op Amp V out M3 M1 M2 T1 VDD T2 T DN C1 DN DNb Fig Transmission Gate Charge Pump (TGCP) The figure 3.18 shown is obviously the source charge pump but with modifications for reducing the non ideal effects. This topology tries to bring the advantages of differential charge pumps. The switches in this circuit are implemented using transmission gates (TG) which are driven by complementary clock signals. The usage of TG almost eliminates the 43

54 clock feed through. Both UP and DOWN currents are derived from same reference current source (20 μa) via current mirrors. So, it can avoid the current mismatch caused by the case in which these two currents are derived from two different sources. The high gain folded cascode operational amplifier (OP Amp) is added to CP to make the voltage V REF at REF node, to follow the voltage V C (voltage at output node or across capacitor) at the output of the CP branch. In other words, OP Amp and Current mirror combination forms the regulated input current mirror in which the V DS of current mirrors are forced to be the same, which makes CP immune to channel length modulation effects. To shun the current mirror mismatch caused by inserting T UP and T DN, T1, T2 and T3 are inserted into the circuit. A large bypass capacitor C 1 is added to the charge pump to further attenuate the glitches since it provide additional path to the ground. a. Design and simulation results The sizes of transistors and gates should be properly adjusted to maximise the effective output voltage range, to expand the tuning range of CP-PLL, to minimise the turn on time of PFD to reduce the in band noise contribution of the PLL to the output. The required reference current IREF is found to be only 20μA. The W/L of M3 and T1 is equal to that of M1 and T2 respectively. But W/L of T3, M4, M1 and T2 are 3 times of that T UP, M5, M2 and T DN respectively. The specifications of folded cascode OP Amp are as follows: Slew Rate: 10 V/μs C L = 10 pf V out = ± 1.2 V VDD= -VSS = 1.8V GB= 10MHz Minimum input common mode voltage: -1V 44

55 Maximum input common mode voltage: 1V A d = 5000 v/v Figure 3.19 shows the transient response while figure 3.20 shows the times verses frequency response of TG CP-PLL. Fig Transient Response of TGCP-PLL b. Discussion a. No ripple in the control voltage after loop is locked. This can be seen clearly in figure 3.18 after approximately 3μs. b. The pull in time is found as 1.2μs approximately which is well below the pull in time of source CP-PLL c. Power consumption is found to be 1.298mW, which is less than source CP-PLL. 45

56 Fig Time Verses Frequency Response of TGCP-PLL d. The current mismatch between UP and DOWN current found as 12μA only. The value of reference spur is found as dbc. c. Limitations Though TG CP removes almost all non ideal effects in charge pump, certain limitations are found in this topology. a. Though the pull in time of PLL is improved (reduced, as it is primary requirement), the power consumption has not reduced in that proportion. b. The reason is that, this topology uses OP Amp, which contributes to the major power consumption of the circuit. c. Further, design of OP Amp is itself tedious process. Hence if requirement of OP Amp are not met, total circuit malfunctions. 46

57 d. Considering efficiency, it is clear that this circuit consumes large area on silicon wafer since design of OP Amp needs resistors and capacitors which are major area consumption elements in chip. A large by pass capacitor used also consumes more area on chip. e. The value of reference spur is higher than source CP reference spur. Hence we can say that relative to source CP`s noise performance is poor. Considering these limitations, a new topology has been thought, which should have all advantages of TG-CP, but it should be more area efficient, fast as well as should consume less power than current topology. In the next chapter, proposed topology is discussed along with comparison with all topologies considered in this thesis. 47

58 Chapter 4 Novel CP Architecture

59 4.1 An Introduction to Self Biased High Swing Cascode Current Mirror A new topology which will remove the disadvantages of TGCP at the same time retain its advantages is proposed here. The main component of any charge pump is the current mirror used in it. An efficient current mirror exhibits the following properties [13]. 1. It has very high output impedance. Hence there will be very less variation in output current for small change in output voltage. 2. It has high output voltage compliance. That is the range of the voltage over which output current remains constant should be high. 3. It consumes less power. 4. It is immune to power supply variation as well as noise. Many architectures of current mirrors are available in the literature e.g. Cascode current mirror, Wilson current mirror, High Swing Cascode current mirror and others. Some architectures use the OP Amp in their circuit, but as discussed earlier it unnecessarily increases hardware complexity. Considering many topologies in literature, it is decided to use Self Biased High Swing Cascode Current Mirror [14]. The reason behind this choice is in the advantages of this topology. 1. Very easy to design. Does not require extra current source for biasing. 2. Can work efficiently even if very less amount of bias current is provided. 3. Very high output impedance. (10MΩ approximately) 4. Good output voltage compliance. 5. Consumes very less power. 6. Suitable for working in sub 1V environment. The self biased high swing cascode current mirror circuit is depicted in figure

60 I Ref R V ON I out V T + 2 V ON M2 M4 V ON V out M1 M3 V T + V ON V ON Fig. 4.1 Self Biased High Swing Cascode Current Mirror As shown in figure 4.1, a resistor R is used to create the bias by dividing the voltage across it. All the transistors are in saturation. The W/L values of M1 and M3 are calculated using the normal drain current formula of MOSFET in saturation. The gates of M2 and M4 are get back biased by V ON (here bulks of all transistors are grounded). Hence the threshold voltages for M2 and M4 can be calculated as: V T4,2 = V To + γ 2Φ F + V SB 2Φ F (4.1) Hence gate voltage for M2 and M4 can be given as: V G4,2 = V T4,2 + 2V ON (4.2) Gate voltage of M1 and M3 can be given as: V G1,3 = V To + V ON (4.3) 50

61 Now it is easy to calculate value of R: R = V G4 V G1 I Ref (4.4) Figure 4.2 shows the input output characteristics of self biased high swing cascode current mirror (SBHSCCM). Fig. 4.2 Input Output Response of SBHSCCM. 4.2 Proposed Charge Pump Figure 4.3 shows the proposed topology for charge pump. This is also a charge pump with switch at source. Transistors M1 to M6 accompanied with T1, T2 and T DN form the DOWN circuit of charge pump, while transistors M7-M10 with T3 and T UP form the complementary UP part of the circuit. This circuit does not include slow path nodes which need complex circuit to speed up. The current mirror used in this topology is designed such that all transistors are guaranteed to be in saturation. As in previous case, switches are implemented using transmission gates (TG) driven by complementary clock signals. So, it 51

62 almost removes the clock feed through effect. The output none of CP is not floating, when switches are off. VDD T3 UP T UP UP b M10 M9 I Ref DC M8 M7 R1 R2 I UP V out I DN M4 M2 M5 M3 M1 M6 T1 VDD T2 DN T DN DNb Fig. 4.3 Proposed SBHSCCM Charge Pump Both charging and discharging currents are derived from same reference current source. Hence current mismatch is avoided. TGs T1, T2 and T3 are inserted to shun the mismatch caused due to insertion of T UP and T DN. The remnant current glitches which occur at the sources of output transistors (M5 and M7) while switching T UP or T DN would not be conveyed to the output node because of insertion of M6 and M9 as well as M5 and M7 are still of when glitches occur. Transistors M5 and M7 would be turned on softly, since rise and fall time of current pulses are controlled by the RC time constants at their sources. Hence this CP is therefore high speed CP avoiding switch errors. This statement will be clearer when simulation result will be discussed next section. 52

63 4.2.1 Design and simulation The charge pump is design according to the procedure given in section 4.1. The reference current used is only 20μA. The W/L values of M1 to M4 are equal and also sizes of T1 and T2 are equal. But W/L values of M5- M6 and T DN are 5 times smaller than M1 and T1 respectively. Similarly, sizes of M8 and M10 are equal but 5 times higher than M7 and M9. T3 is 3 times larger than T UP. All this sizing has been done so as to have maximization of effective output voltage, to remove current glitches and to reduce the turn on time of PFD. Value of bias current is chosen such that charge pump helps to give minimum optimum pull in time for PLL. Figure 4.4 shows the transient response of proposed architecture while figure 4.5 shows the time verses frequency response. Fig. 4.4 Transient Response of Proposed CP-PLL 53